8/20/2019 Circuit & Electronics.pdf
1/414
6.002 CIRCUITS AND ELECTRONICS
Introduction and Lumped Circuit Abstraction
6.002 Fall 2000 Lecture 1 1
8/20/2019 Circuit & Electronics.pdf
2/414
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal Textbook: Agarwal and Lang (A&L
Readings are important!
Handout no. 3 Assignments —
Homework exercisesLabs
QuizzesFinal exam
6.002 Fall 2000 Lecture 1 2
8/20/2019 Circuit & Electronics.pdf
3/414
Two homework assignments canbe missed (except HW11).
Collaboration policyHomework
You may collaborate withothers, but do your ownwrite-up.
LabYou may work in a team oftwo, but do you own write-up.
Info handout
Reading for today —Chapter 1 of the book
6.002 Fall 2000 Lecture 1 3
8/20/2019 Circuit & Electronics.pdf
4/414
What is engineering?
Purposeful use of science
What is 6.002 about?Gainful employment ofMaxwell’s equations
From electrons to digital gatesand op-amps
6.002 Fall 2000 Lecture 1 4
8/20/2019 Circuit & Electronics.pdf
5/414
6 .
0 0 2
Simple amplifier abstraction
Instruction set abstraction
Pentium, MIPS
Software systemsOperating systems, Browsers
Filters
Operationalamplifier abstractionabstraction
-+
Digital abstraction
Programming languagesJava, C++, Matlab 6.001
Combinational logic f
Lumped circuit abstraction
R S
+ –
Nature as observed in experiments
…0.40.30.20.1 I
…12963V
Physics laws or “abstractions” Maxwell’s Ohm’s
V = R I
abstraction fortables of data
Clocked digital abstraction
Analog system
components:Modulators,oscillators,RF amps,power supplies 6.061
Mice, toasters, sonar, stereos, doom, space shuttle
6.1706.455
6.004
6.033
M LCV
6.002 Fall 2000 Lecture 1 5
8/20/2019 Circuit & Electronics.pdf
6/414
Lumped Circuit Abstraction
Consider I
The Big Jumpfrom physics
to EECS
+
-
V
?
Suppose we wish to answer this question:
What is the current through the bulb?
6.002 Fall 2000 Lecture 1 6
8/20/2019 Circuit & Electronics.pdf
7/414
We could do it the Hard Way…
Apply Maxwell’s
Differential form Integral form
Faraday’s ∇ × E = −∂ B
∫ E ⋅ dl = −∂φ B
∂t ∂t
Continuity ∇ ⋅ J = −
∂
∂
ρ
t ∫ J ⋅ dS = −
∂
∂
q
t
Others ∇ ⋅ E = ρ
∫ E ⋅ dS = q
ε 0 ε 0
6.002 Fall 2000 Lecture 1 7
8/20/2019 Circuit & Electronics.pdf
8/414
Instead, there is an Easy Way…
First, let us build some insight:
Analogy
F
a ?
I ask you: What is the acceleration?
You quickly ask me: What is the mass?
I tell you: m F
You respond: a = m
Done ! ! !
6.002 Fall 2000 Lecture 1 8
8/20/2019 Circuit & Electronics.pdf
9/414
Instead, there is an Easy Way…
First, let us build some insight:
F
a ?
Analogy
In doing so, you ignored the object’s shape its temperature
its color point of force application
Point-mass discretization
6.002 Fall 2000 Lecture 1 9
8/20/2019 Circuit & Electronics.pdf
10/414
The Easy Way…
Consider the filament of the light bulb.
A
B
We do not care about
how current flows inside the filament its temperature, shape, orientation, etc.
Then, we can replace the bulb with a
discrete resistorfor the purpose of calculating the current.
6.002 Fall 2000 Lecture 1 10
8/20/2019 Circuit & Electronics.pdf
11/414
The Easy Way…
A
B
Replace the bulb with a
discrete resistorfor the purpose of calculating the current.
+
–V
A I
R and I =
V
R
BIn EE, we do things
the easy way…
R represents the only property of interest
Like with point-mass: replace objects F
with their mass m to find a = m
6.002 Fall 2000 Lecture 1 11
8/20/2019 Circuit & Electronics.pdf
12/414
The Easy Way…
+
–V
A I
R and I = V
R
BIn EE, we do things
the easy way…
R represents the only property of interest
R relates element v and i
V I =
R
called element v-i relationship
6.002 Fall 2000 Lecture 1 12
8/20/2019 Circuit & Electronics.pdf
13/414
R is a lumped element abstraction
for the bulb.
6.002 Fall 2000 Lecture 1 13
8/20/2019 Circuit & Electronics.pdf
14/414
R is a lumped element abstractionfor the bulb.
Not so fast, though …
A
B
S
B S
I
+
–
V
black box
Although we will take the easy wayusing lumped abstractions for the restof this course, we must make sure (atleast the first time) that ourabstraction is reasonable. In this case,ensuring that V I
are definedfor the element
6.002 Fall 2000 Lecture 1 14
8/20/2019 Circuit & Electronics.pdf
15/414
A
V I
must be defined B
A S
B S
I
+
–
V
for the element
black box
6.002 Fall 2000 Lecture 1 15
8/20/2019 Circuit & Electronics.pdf
16/414
l
I must be defined. True when
I into S A = I out of S B
True only when
∂q =
0 in the filament!∂t
∫
J
⋅
dS S A
∫ J ⋅ dS S B
∫ J ⋅ dS − ∫ J ⋅ dS = ∂q
S A
S B
∂t
I A I B
I A = I B only if 0 = ∂
∂
t
q
So let’s assume this
6.002 Fall 2000 Lecture 1 16
f r o m
M a x w e
l
8/20/2019 Circuit & Electronics.pdf
17/414
V Must also be defined.
s e e
A & L
So let’s assume this too
V AB
So V AB = ∫ AB E ⋅ dl
defined when 0= ∂
∂
t B φ
outside elements
6.002 Fall 2000 Lecture 1 17
8/20/2019 Circuit & Electronics.pdf
18/414
Lumped Matter Discipline (LMD)
0= ∂
∂
t B
φ outside
0= ∂
∂
t
q inside elementsbulb, wire, battery
Or self imposed constraints:
More inChapter 1of A & L
Lumped circuit abstraction applies whenelements adhere to the lumped matterdiscipline.
6.002 Fall 2000 Lecture 1 18
8/20/2019 Circuit & Electronics.pdf
19/414
Demo Lumped element exampleswhosecaptured by their V – Irelationship.
only for thesorts ofquestions we
as EEs wouldlike to ask!
is completelybehavior
DemoExploding resistor demo
can’t predict that!Pickle demo
can’t predict light, smell
6.002 Fall 2000 Lecture 1 19
8/20/2019 Circuit & Electronics.pdf
20/414
So, what does this buy us?
Replace the differential equationswith simple algebra using lumped
circuit abstraction (LCA).
For example —a
+ –
1
2
3b d
R4
V
R5
c
What can we say about voltages in a loopunder the lumped matter discipline?
6.002 Fall 2000 Lecture 1 20
8/20/2019 Circuit & Electronics.pdf
21/414
What can we say about voltages in a loopunder LMD?
+ –
1
2
3
a
b d
R4
V
R5
c
∫
E ⋅ dl = t B
∂∂−
φ under DMD0
∫
E ⋅ dl + ∫
E ⋅ dl + ∫
E ⋅ dl = 0 ca ab bc
+ V ca + V ab + V bc = 0
Kirchhoff’s Voltage Law (KVL):
The sum of the voltages in a loop is 0.
6.002 Fall 2000 Lecture 1 21
8/20/2019 Circuit & Electronics.pdf
22/414
What can we say about currents?
Consider
S I ca I da
ba I
a
6.002 Fall 2000 Lecture 1 22
8/20/2019 Circuit & Electronics.pdf
23/414
What can we say about currents?
ca
da
ba I
a
I
S I
S J ⋅ dS =
t
q
∂
∂−
under LMD0
∫
I ca +
I da +
I ba =
0
Kirchhoff’s Current Law (KCL):
The sum of the currents into a node is 0.
simply conservation of charge
6.002 Fall 2000 Lecture 1 23
8/20/2019 Circuit & Electronics.pdf
24/414
KVL and KCL Summary
KVL: ∑ jν j = 0
loop
KCL:
∑ j i j = 0
node
6.002 Fall 2000 Lecture 1 24
8/20/2019 Circuit & Electronics.pdf
25/414
6.002 Fall 2000 Lecture 12
6.002 CIRCUITS ANDELECTRONICS
Basic Circuit Analysis Method(KVL and KCL method)
8/20/2019 Circuit & Electronics.pdf
26/414
6.002 Fall 2000 Lecture 22
0=∂
∂
t
Bφ
0=∂
∂
t
q
Outside elements
Inside elements
Allows us to create the lumped circuitabstraction
wires resistors sources
Review
Lumped Matter Discipline LMD:Constraints we impose on ourselves to simplifyour analysis
8/20/2019 Circuit & Electronics.pdf
27/414
6.002 Fall 2000 Lecture 32
LMD allows us to create thelumped circuit abstraction
Lumped circuit element+
-
v
i
power consumed by element = vi
Review
8/20/2019 Circuit & Electronics.pdf
28/414
6.002 Fall 2000 Lecture 42
KVL:
loop
KCL:
node
0=∑ j jν
0=∑ j ji
ReviewReview
Maxwell’s equations simplify toalgebraic KVL and KCL under LMD!
8/20/2019 Circuit & Electronics.pdf
29/414
6.002 Fall 2000 Lecture 52
KVL0=++ bcabca vvv
0=++ badaca iii KCLDEMO
1
2
4
5
3
a
b
d
c
+
–
Review
8/20/2019 Circuit & Electronics.pdf
30/414
6.002 Fall 2000 Lecture 62
Method 1: Basic KVL, KCL method ofCircuit analysis
Goal: Find all element v’s and i’s
write element v-i relationships(from lumped circuit abstraction)
write KCL for all nodeswrite KVL for all loops
1.
2.3.
lots of unknownslots of equationslots of funsolve
8/20/2019 Circuit & Electronics.pdf
31/414
6.002 Fall 2000 Lecture 72
Method 1: Basic KVL, KCL method ofCircuit analysis
For R,
For voltage source,
For current source,
Element Relationships
IRV =
0V V =
0 I =
3 lumped circuit elements
0V
o I
+ –
8/20/2019 Circuit & Electronics.pdf
32/414
6.002 Fall 2000 Lecture 82
KVL, KCL Example
The Demo Circuit
+ –
1
2
4
5
3
a
b d
c
00 V =ν +
–
1ν +–
5ν
+
–
3ν + –
2ν +
–
4ν +–
8/20/2019 Circuit & Electronics.pdf
33/414
6.002 Fall 2000 Lecture 92
Associated variables discipline
ν
i +
-
Element e
Then power consumed
by element e
iν = is positive
Current is taken to be positive goinginto the positive voltage terminal
8/20/2019 Circuit & Electronics.pdf
34/414
6.002 Fall 2000 Lecture 102
KVL, KCL Example
The Demo Circuit
+ –
1
2
4
5
3
a
b d
c
00 V =ν +
–
1ν +–
5ν
+
–
3ν + –
1 L
2 L
4 L
3 L2ν
+
–
4ν +–
2i
1i
0i
5i
3i
4i
8/20/2019 Circuit & Electronics.pdf
35/414
6.002 Fall 2000 Lecture 112
Analyze12 unknowns
5050 , ι ι ν ν ……
1. Element relationships
3. KVL for loops
00 V v =111 iv =
222 iv =
333 iv =444 iv =
555 iv =
given
2. KCL at the nodes
redundant
0431 =−+ vvv
0210 =++− vvv
0253 =−+ vvv0540 =++− vvv redundant
0410 =++ iii0132 =−+ iii0435 =−− iii0520 =−−− iii
a:b:
d:
e:
6 equations
3 independentequations
3 independentequations
1 2 u n k n o w n
s
1 2 e q u a
t i o n s
u g h @ # !
( )iv,
L1:
L2:
L3:
L4:
8/20/2019 Circuit & Electronics.pdf
36/414
6.002 Fall 2000 Lecture 122
Other Analysis MethodsMethod 2— Apply element combination rules
B
C
D
⇔+++ 21
⇔1G 2G N G GGG ++ 21
i
i R
G 1=
⇔+ – + – + –1V 2V 21 V V +
⇔
1 2 21 +
A 1 2 3 N
…
Surprisingly, these rules (along with superposition, which you will learn about later) can solve the circuit on page 8
8/20/2019 Circuit & Electronics.pdf
37/414
6.002 Fall 2000 Lecture 132
Other Analysis MethodsMethod 2— Apply element combination rules
V
32
32
R R +
V
32
32
1 R R R R
++=
+ –
V
?=
1
32
+ –
+ –
Example
1
R
V I =
8/20/2019 Circuit & Electronics.pdf
38/414
6.002 Fall 2000 Lecture 142
1.
2.
3.
4.
5.
Select reference node ( ground)from which voltages are measured.
Label voltages of remaining nodeswith respect to ground.These are the primary unknowns.
Write KCL for all but the ground
node, substituting device laws andKVL.
Solve for node voltages.
Back solve for branch voltages andcurrents (i.e., the secondary unknowns)
Particular application of KVL, KCL method
Method 3—Node analysis
8/20/2019 Circuit & Electronics.pdf
39/414
6.002 Fall 2000 Lecture 152
Example: Old Faithfulplus current source
0V
1
2
4
5
3
1 I
0V
+ – 1e
2e
Step 1Step 2
8/20/2019 Circuit & Electronics.pdf
40/414
6.002 Fall 2000 Lecture 162
Example: Old Faithfulplus current source
0)()()( 21321101 =+−+− GeGeeGV eKCL at 1e
0)()()( 152402312 =−+−+− I GeGV eGee
KCL at 2e
for
conveniencewrite
i
i R
G 1=
0V
1
2
4
5
3
1e
1
0V
+ –
2e
Step 3
8/20/2019 Circuit & Electronics.pdf
41/414
6.002 Fall 2000 Lecture 172
Example: Old Faithfulplus current source
0)()()( 21321101 =+−+− GeGeeGV e
KCL at 1e
0)()()( 152402312 =−+−+− I GeGV eGeeKCL at 2l
move constant terms to RHS & collect unknowns
)()()( 10323211 GV GeGGGe =−+++
140543231 )()()( GV GGGeGe +=+++−
i
i R
G 1=
2 equations, 2 unknowns Solve for e’s(compare units)
0V
1
2
4
5
3
1e
1
0V
+ –
2e
Step 4
8/20/2019 Circuit & Electronics.pdf
42/414
6.002 Fall 2000 Lecture 182
In matrix form:
+=
++−
−++
104
01
2
1
5433
3321
I V G
V G
e
e
GGGG
GGGG
conductivitymatrix
unknownnode
voltages
sources
( )( ) 23543321
104
01
3213
3543
2
1
GGGGGGG
I V G
V G
GGGG
GGGG
e
e
−++++
+
++
++
=
Solve
5G3G4G3G2
3G5G2G4G2G3G2G5G1G4G1G3G1G
1 I 0V 4G3G
0V 1G5G4G3G
1e
++++++++
++++=
( )( ) ( )( )
5343
2
3524232514131
1043210132
GGGGGGGGGGGGGGGGG
I V GGGGV GGe
++++++++
++++=
(same denominator)
Notice: linear in , , no negativesin denominator
0V 1
8/20/2019 Circuit & Electronics.pdf
43/414
6.002 Fall 2000 Lecture 192
Solve, given
K 2.8
1
G
G
5
1
=
K 9.3
1
G
G
4
2
=
K 5.1
1G3 =
01 = I
( ) ( ) 23G5G4G3G3G2G1G
10
V
4
G
3
G
2
G
1
G
0
V
1
G
3
G
2e −+++++
++++
=
15.1
1
9.3
1
2.8
1
3G2G1G =++=++
12.81
9.31
5.11GGG 543 =++=++
0
2
2 V
5.1
11
9.3
115.1
1
2.8
1
e
−
×+×=
02 6.0 V e =
If , thenV V 30 = 02 8.1 V e =
Check out the
DEMO
8/20/2019 Circuit & Electronics.pdf
44/414
6.002 Fall 2000 Lecture 13
6.002 CIRCUITS ANDELECTRONICS
Superposition, Thévenin and Norton
8/20/2019 Circuit & Electronics.pdf
45/414
6.002 Fall 2000 Lecture 23
0=∑loop
iV
Review
Circuit Analysis Methods
Circuit composition rules
Node method – the workhorse of 6.002KCL at nodes using V ’s referencedfrom ground(KVL implicit in “ ”) ji ee − G
KVL: KCL:
0=∑node
i
VI
8/20/2019 Circuit & Electronics.pdf
46/414
6.002 Fall 2000 Lecture 33
Consider
Linearity
Write node equations –
V I
1
2+ –
021
=−+−
I R
e
R
V e
Notice:linear in V e ,,
VI ,eV No
terms
e
8/20/2019 Circuit & Electronics.pdf
47/414
6.002 Fall 2000 Lecture 43
Consider
Linearity
Write node equations --
Rearrange --
V I
1
2+ –
021
=−+−
I R
e
R
V e
I R
V e R R +=
+121
11
e S =
conductance
matrix
node
voltages
linear sum
of sources
linear in IV e ,,
8/20/2019 Circuit & Electronics.pdf
48/414
6.002 Fall 2000 Lecture 53
Linearity
or I R RV R Re21
21
21
2
+++=
…… +++++= 22112211 bbV aV ae
Write node equations --
Rearrange --
021
=−+−
I R
e
R
V e
I RV e
R R+=
+
121
11
e S =
conductancematrix nodevoltages linear sumof sources
linear in IV e ,,
Linear!
8/20/2019 Circuit & Electronics.pdf
49/414
6.002 Fall 2000 Lecture 63
LinearityHomogeneitySuperposition⇒
8/20/2019 Circuit & Electronics.pdf
50/414
6.002 Fall 2000 Lecture 73
LinearityHomogeneitySuperposition
Homogeneity
1 x2
x y...
1 xα 2 xα yα ...
⇓
⇒
8/20/2019 Circuit & Electronics.pdf
51/414
6.002 Fall 2000 Lecture 83
LinearityHomogeneitySuperposition
Superposition
a x1a x2 a y... ...
b x1b x2 b y
⇒
ba x x 11 +
ba x x 22 + ba y y +
⇓
...
8/20/2019 Circuit & Electronics.pdf
52/414
6.002 Fall 2000 Lecture 93
LinearityHomogeneitySuperposition
Specific superposition example:
1V 0 1 y 02V 2 y
01 +V
20 V + 21 y +
⇓
⇒
8/20/2019 Circuit & Electronics.pdf
53/414
6.002 Fall 2000 Lecture 103
Method 4: Superposition method
The output of a circuit is
determined by summing theresponses to each sourceacting alone.
i n d e p e n d e n
t s o u rc e s
o n l y
8/20/2019 Circuit & Electronics.pdf
54/414
6.002 Fall 2000 Lecture 113
i
+ –0=V
+
-
v
i
short
+
-
v
i
0= I
+
-
v
i
open
+
-
v
8/20/2019 Circuit & Electronics.pdf
55/414
6.002 Fall 2000 Lecture 123
Back to the exampleUse superposition method
V
1
2+ –
e
8/20/2019 Circuit & Electronics.pdf
56/414
6.002 Fall 2000 Lecture 133
Back to the exampleUse superposition method
V
acting alone
V 0= I
2+ –
e
1
I acting alone
0=V
1
2
e
V R R
eV 21
2
+=
I R R
e I 21
21
+=
I R R
V R R
eee I V 21
21
21
2
++
+=+=
sum superposition
Voilà !
8/20/2019 Circuit & Electronics.pdf
57/414
6.002 Fall 2000 Lecture 143
saltwater
output showssuperposition
Demo
constant
+ –
sinusoid
+ –
?
8/20/2019 Circuit & Electronics.pdf
58/414
6.002 Fall 2000 Lecture 153
Consider Yet another method…
resistors
nounits
By setting
0
,0
=
=∀
i
nn
0
,0
=
=∀
i
V mm
All
0
,0=∀=∀
mm
nn
V
+ –
mV n
A r b i t r a r
y n e t w o r k N
By superpositioni I V v n
nnm
mm ++= ∑∑ β α
+
-v
i
i
resistanceunits
independent of externalexcitation and behaves like avoltage “ ”TH v
alsoindependentof externalexcitement &behaves likea resistor
8/20/2019 Circuit & Electronics.pdf
59/414
6.002 Fall 2000 Lecture 163
Orivv TH TH +=
As far as the external world is concerned(for the purpose of I-V relation),
“Arbitrary network N” is indistinguishable
from:
i + –
TH
TH v
+
-
v
Théveninequivalentnetwork
TH
TH v open circuit voltageat terminal pair (a.k.a. port)
resistance of network seenfrom port( ’s, ’s set to 0)
mV n
N
8/20/2019 Circuit & Electronics.pdf
60/414
6.002 Fall 2000 Lecture 173
Method 4:
The Thévenin Method
Replace network N with its Thévenin
equivalent, then solve external network E.
E
Thévenin equivalent
+ –
TH
TH v
+
-
v
i
E
+ –
+ –
i
+
-v
N
8/20/2019 Circuit & Electronics.pdf
61/414
6.002 Fall 2000 Lecture 183
Example:1
V +
–
1i
1
V
+
–
1i
TH
TH
R RV V i
+−=
1
1
2
TH
TH V + –
8/20/2019 Circuit & Electronics.pdf
62/414
6.002 Fall 2000 Lecture 193
Example:
:TH
:TH V
2 IRV TH =
2TH =
+
-TH V 2
+
-TH 2
8/20/2019 Circuit & Electronics.pdf
63/414
6.002 Fall 2000 Lecture 203
Graphically, ivv TH TH +=
i
Open circuit( )0≡i
TH vv = OC V
Short circuit( )0≡v TH
TH
R
vi −=
SC I −
v
TH R
1
TH v
SC I −
OC V “ ”
8/20/2019 Circuit & Electronics.pdf
64/414
6.002 Fall 2000 Lecture 213
Method 5:
The Norton Method
in recitation,see text
+ –
+ –
i
+
-v
Nortonequivalent
TH
TH N
R
V I =
N TH = N
8/20/2019 Circuit & Electronics.pdf
65/414
6.002 Fall 2000 Lecture 223
Summary
… 101100 …
Discretize matterLMD LCA
Physics EE
R, I, V Linear networks
Analysis methods (linear)KVL, KCL, I — VCombination rulesNode methodSuperpositionThéveninNorton
NextNonlinear analysis
Discretize voltage
8/20/2019 Circuit & Electronics.pdf
66/414
6.002 Fall 2000 Lecture 14
6.002 CIRCUITS ANDELECTRONICS
The Digital Abstraction
8/20/2019 Circuit & Electronics.pdf
67/414
6.002 Fall 2000 Lecture 24
Review
Discretize matter by agreeing toobserve the lumped matter discipline
Analysis tool kit: KVL/KCL, node method,superposition, Thévenin, Norton
(remember superposition, Thévenin,Norton apply only for linear circuits)
Lumped Circuit Abstraction
8/20/2019 Circuit & Electronics.pdf
68/414
6.002 Fall 2000 Lecture 34
Discretize value Digital abstraction
Interestingly, we will see shortly that thetools learned in the previous threelectures are sufficient to analyze simpledigital circuits
Reading: Chapter 5 of Agarwal & Lang
Today
8/20/2019 Circuit & Electronics.pdf
69/414
6.002 Fall 2000 Lecture 44
Analog signal processing
But first, why digital?In the past …
By superposition,
The above is an “adder” circuit.
2
21
11
21
20
V R R
V R R
V +
+
+
=
If ,21 R R =
2
21
0
V V V
+=
1V
1
2+ –
2V + –
0V
and
might represent the
outputs of two
sensors, for example.
1V 2V
8/20/2019 Circuit & Electronics.pdf
70/414
6.002 Fall 2000 Lecture 54
Noise Problem
… noise hampers our ability to distinguishbetween small differences in value —e.g. between 3.1V and 3.2V.
Receiver:
huh?
add noise onthis wire
t
8/20/2019 Circuit & Electronics.pdf
71/414
6.002 Fall 2000 Lecture 64
Value Discretization
Why is this discretization useful?
Restrict values to be one of two
HIGH
5V
TRUE
1
LOW
0V
FALSE
0
…like two digits 0 and 1
(Remember, numbers larger than 1 can berepresented using multiple binary digits andcoding, much like using multiple decimal digits torepresent numbers greater than 9. E.g., thebinary number 101 has decimal value 5.)
8/20/2019 Circuit & Electronics.pdf
72/414
6.002 Fall 2000 Lecture 74
Digital System
sender receiverS
V RV
noise
S V
“0” “0”“1”
0V
2.5V
5V HIGH
LOW
t
RV
“0” “0”“1”
0V
2.5V
5V
t
V V N
0=
N V
S V
“0” “0”“1”
2.5V t
With noiseV V
N 2.0=
S V
“0” “0”“1”
0V
2.5V
5V
t
0.2V
t
8/20/2019 Circuit & Electronics.pdf
73/414
6.002 Fall 2000 Lecture 84
Digital System
Better noise immunityLots of “noise margin”
For “1”: noise margin 5V to 2.5V = 2.5V For “0”: noise margin 0V to 2.5V = 2.5V
8/20/2019 Circuit & Electronics.pdf
74/414
6.002 Fall 2000 Lecture 94
Voltage Thresholdsand Logic Values
1
0
1
0
sender receiver
1
0
0V
2.5V
5V
8/20/2019 Circuit & Electronics.pdf
75/414
6.002 Fall 2000 Lecture 104
forbidden
region
VH
V L
3V
2V
But, but, but …
What about 2.5V?
Hmmm… create “no man’s land”or forbidden region
For example,
sender receiver
0V
5V
1 1
0 0
“1” V 5V
“0” 0V V
H
L
8/20/2019 Circuit & Electronics.pdf
76/414
6.002 Fall 2000 Lecture 114
sender receiver
But, but, but …Where’s the noise margin?
What if the sender sent 1: ?VHHold the sender to tougher standards!
5V
0V
11
00
V
0H
V0L
VIH
VIL
8/20/2019 Circuit & Electronics.pdf
77/414
6.002 Fall 2000 Lecture 124
sender receiver
VH
But, but, but …Where’s the noise margin?
What if the sender sent 1: ?Hold the sender to tougher standards!
5V
0V
“1” noise margin:
“0” noise margin:
VIH
- V0H
VIL
- V0L
11
00
V
0H
V0L
VIH
VIL
Noise margins
8/20/2019 Circuit & Electronics.pdf
78/414
6.002 Fall 2000 Lecture 134
Digital systems follow static discipline: ifinputs to the digital system meet valid inputthresholds, then the system guarantees itsoutputs will meet valid output thresholds.
sender
receiver
0 1 0 1
t
5VV
0H
V0L
0V
VIH
VIL
0 1 0 1
t
5VV
0H
V0L
0V
VIH
VIL
8/20/2019 Circuit & Electronics.pdf
79/414
6.002 Fall 2000 Lecture 144
Processing digital signals
Recall, we have only two values —
Map naturally to logic: T, F
Can also represent numbers
1,0
8/20/2019 Circuit & Electronics.pdf
80/414
6.002 Fall 2000 Lecture 154
Processing digital signalsBoolean Logic
If X is true and Y is trueThen Z is true else Z is false.
Z = X AND YX, Y, Z
are digital signals“0” , “1”
Z = X • YBoolean equation
Enumerate all input combinations
Truth table representation:
ZX Y
AND gateZX
Y
0 0 0
0 1 01 0 0
1 1 1
8/20/2019 Circuit & Electronics.pdf
81/414
6.002 Fall 2000 Lecture 164
Adheres to static discipline Outputs are a function of
inputs alone.
Combinational gateabstraction
Digital logic designers do not
have to care about what is
inside a gate.
8/20/2019 Circuit & Electronics.pdf
82/414
6.002 Fall 2000 Lecture 174
Demo
Noise
ZXY
Z = X • Y
Z
Y
X
8/20/2019 Circuit & Electronics.pdf
83/414
6.002 Fall 2000 Lecture 184
Z = X • Y
Examples for recitation
X
t
Y
t
Z
t
8/20/2019 Circuit & Electronics.pdf
84/414
6.002 Fall 2000 Lecture 194
In recitation…
Another example of a gateIf (A is true) OR (B is true)
then C is true
else C is false
C = A + B Boolean equation
OR
OR gate
CA
B
ZX
Y NAND
Z = X • Y
More gates
B B
Inverter
8/20/2019 Circuit & Electronics.pdf
85/414
6.002 Fall 2000 Lecture 204
Boolean Identities
AB + AC = A • (B + C)
X • 1 = XX • 0 = XX + 1 = 1X + 0 = X
1 = 0
0 = 1
output
BC B • C
A
Digital Circuits
Implement: output = A + B • C
8/20/2019 Circuit & Electronics.pdf
86/414
6.002 Fall 2000 Lecture 15
6.002 CIRCUITS ANDELECTRONICS
Inside the Digital Gate
8/20/2019 Circuit & Electronics.pdf
87/414
6.002 Fall 2000 Lecture 25
Review
Discretize value 0, 1
Static disciplinemeet voltage thresholds
Specifies how gates must be designed
sender receiver
forbiddenregion
OLV
OH V
LV
IH V
The Digital Abstraction
8/20/2019 Circuit & Electronics.pdf
88/414
6.002 Fall 2000 Lecture 35
Review
C A B
0 0 10 1 11 0 11 1 0
A
B C
NAND
Combinational gate abstractionoutputs function of input alonesatisfies static discipline
8/20/2019 Circuit & Electronics.pdf
89/414
6.002 Fall 2000 Lecture 45
For example:a digital circuit
Demo
D
A
B
C
A Pentium III class microprocessoris a circuit with over 4 million gates !!
The RAW chipbeing built at theLab for Computer Science at MIThas about 3 million gates.
3 gates here
( )( ) B AC D ⋅⋅=
B A ⋅
8/20/2019 Circuit & Electronics.pdf
90/414
6.002 Fall 2000 Lecture 55
How to build a digital gate
Analogy
A B
C
li ke po wer
s u p p l y
( l i ke s w i tc he
s )
taps
if A=ON AND B=ON
C has H 0
else C has no H 0
2
2
Use this insight to build an AND gate.
8/20/2019 Circuit & Electronics.pdf
91/414
6.002 Fall 2000 Lecture 65
How to build a digital gate
C
B
A
OR gate
8/20/2019 Circuit & Electronics.pdf
92/414
6.002 Fall 2000 Lecture 75
Electrical Analogy
+ –
Bulb C is ON if A AND B are ON,else C is off
Key: “switch” device
V
BC
8/20/2019 Circuit & Electronics.pdf
93/414
6.002 Fall 2000 Lecture 85
Electrical Analogy
Key: “switch” device
C
in
out
control
3-Terminal deviceif C = 0
short circuit between in and outelse
open circuit between in and out
For mechanical switch,control mechanical pressure
in
out
1=C
equivalent ck
0=C
in
out
8/20/2019 Circuit & Electronics.pdf
94/414
6.002 Fall 2000 Lecture 95
Consider
=S
V “1”
+ – S
V
L R
C
IN
OUT
OUT V
S V
0=C
OUT V
S V
1=C
OUT V
S V
L R
C
OUT V
Truth table for
C
0 1
1 0
OUT V
8/20/2019 Circuit & Electronics.pdf
95/414
6.002 Fall 2000 Lecture 105
What about?Truth table for
OV 2c
0 0 10 1 11 0 1
1 1 0
1c
Truth table for
OV 2c
0 0 1
0 1 01 0 01 1 0
1c
S V
OUT V
1c
2c
S V
OUT V
1c
2c
8/20/2019 Circuit & Electronics.pdf
96/414
6.002 Fall 2000 Lecture 115
What about?
can also build compound gates
S V
D
B
C ( ) C B A D +⋅=
8/20/2019 Circuit & Electronics.pdf
97/414
6.002 Fall 2000 Lecture 125
The MOSFET Device
3 terminal lumped elementbehaves like a switch
Metal-OxideSemiconductorField-EffectTransistor
: control terminal: behave in a symmetricmanner (for our needs)
G
S D,
gate≡
source
D
S
G
drain
8/20/2019 Circuit & Electronics.pdf
98/414
6.002 Fall 2000 Lecture 135
The MOSFET Device
Understand its operation by viewing it
as a two-port element —
“Switch” model (S model) of the MOSFET
D
S
Gi
G
GS v+
–
DS v
DS i +
–
Ch ec k o u t
th e t e x t b
o o k
f o r i t s i n
t e r n a l
s t r uc t u r
e.
T GS V v <
T GS V v ≥
V V T 1≈ typically
onG
D
S
DS i
G off
D
S
8/20/2019 Circuit & Electronics.pdf
99/414
6.002 Fall 2000 Lecture 145
Check the MOS deviceon a scope.
Demo
GS v+
–
DS v
DS i
+
–
T GS V v ≥
DS i
DS v
T GS V v <
DS i
DS vvs
8/20/2019 Circuit & Electronics.pdf
100/414
6.002 Fall 2000 Lecture 155
A MOSFET Inverter
S V
L
IN
B
B
V 5=
Note the power of abstraction.
The abstract inverter gate representationhides the internal details such as powersupply connections, , , etc.
(When we build digital circuits, theand are common across all gates!)
L GND
vOUT
8/20/2019 Circuit & Electronics.pdf
101/414
6.002 Fall 2000 Lecture 165
The T1000 model laptop desires gates that satisfythe static discipline with voltage thresholds. Doesout inverter qualify?
IN v
OUT v
OUT v
IN v
5V
5V
0V=1VT V
= 0.5VOL
V
= 4.5VOH
V
= 0.9V IL
V
= 4.1V IH
V
Our inverter satisfies this.
receiver
OLV
OH V
LV
IH V
54.5
0.5
0
sender
5
4.1
0.9
0
1:
0:
1
0
Example
8/20/2019 Circuit & Electronics.pdf
102/414
6.002 Fall 2000 Lecture 175
E.g.:
Does our inverter satisfy the staticdiscipline for these thresholds:
= 0.2VOL
V
= 4.8VOH V
= 0.5V IL
V
= 4.5V IH V
= 0.5VOLV
= 4.5VOH
V
= 1.5V L
V
= 3.5V H
V
yes
no
x
8/20/2019 Circuit & Electronics.pdf
103/414
6.002 Fall 2000 Lecture 185
Switch resistor (SR) modelof MOSFET
…more accurate MOS model
D
S
G
D
S T GS
V v <
G
T GS V v ≥
ON
D
S
G
e.g. Ω= K ON
5
8/20/2019 Circuit & Electronics.pdf
104/414
6.002 Fall 2000 Lecture 195
SR Model of MOSFET
MOSFET S model
T GS V v ≥
T GS V v <
DS i
DS v
MOSFET SR model
T GS V v ≥
T GS V v <
DS i
DS v
ON R
1
D
S
G
D
S T GS
V v <
G
T GS V v ≥
ON
D
S
G
8/20/2019 Circuit & Electronics.pdf
105/414
6.002 Fall 2000 Lecture 205
Using the SR model
=S
V “1”
+ – S
V
L R
C
IN
OUT
OUT v
S V
0=C
OUT v
S V
1=C OUT
v
S V
L R
C
OUT v
Truth table for
C
0 11 0
OUT
V
T GS V v ≥
ON
ON OLV
RON
R
ON R
S V
OUT v ≤
+=
L R
L R Choose RL, RON, VS such that:
8/20/2019 Circuit & Electronics.pdf
106/414
6.002 Fall 2000 Lecture 16
6.002 CIRCUITS ANDELECTRONICS
Nonlinear Analysis
8/20/2019 Circuit & Electronics.pdf
107/414
6.002 Fall 2000 Lecture 26
Discretize matter LCA
m1 KVL, KCL, i-v
m2 Composition rules
m3
Node methodm4 Superposition
m5 Thévenin, Norton
anycircuit
linearcircuits
Review
8/20/2019 Circuit & Electronics.pdf
108/414
6.002 Fall 2000 Lecture 36
Discretize value
Digital abstraction Subcircuits for given “switch”
setting are linear! So, all 5methods (m1 – m5) can be
applied
1
1
=
=
B
B
S V
L
C
S V
L
C
ON ON
SR MOSFET Model
Review
8/20/2019 Circuit & Electronics.pdf
109/414
6.002 Fall 2000 Lecture 46
Today
Nonlinear Analysis
Analytical methodbased on m1, m2, m3
Graphical method
Introduction to incremental analysis
8/20/2019 Circuit & Electronics.pdf
110/414
6.002 Fall 2000 Lecture 56
How do we analyze nonlinearcircuits, for example:
Dv+ -
D
Di
Dv
Di
0,0
Dbv
D aei =
a
Dv+
-V +
–
Hypotheticanonlineardevice D
Di
(Expo Dweeb ☺)
(Curiously, the device supplies power whenv D is negative)
8/20/2019 Circuit & Electronics.pdf
111/414
6.002 Fall 2000 Lecture 66
Method 1: Analytical Method
Using the node method,(remember the node method applies for linear ornonlinear circuits)
Dbv
D aei = 2
0=+−
D D i
V v1
2 unknowns 2 equations
Solve the equation by trial and error numerical methods
8/20/2019 Circuit & Electronics.pdf
112/414
6.002 Fall 2000 Lecture 76
Method 2: Graphical Method
Notice: the solution satisfies equations
and 21
Dv
Di
a
Dbv D aei =2
Dv
Di 1 vV
i D D −=
V
V
slope 1−=
8/20/2019 Circuit & Electronics.pdf
113/414
6.002 Fall 2000 Lecture 86
Combine the two constraints
1
4
1
1
1
=
=
=
=
b
a
R
V e.g.
Ai
V v
D
D
4.0
5.0
=
=
Dv
Di
5.0~
4.0~
V
V 1
1
a¼
called “loadline”for reasons youwill see later
8/20/2019 Circuit & Electronics.pdf
114/414
6.002 Fall 2000 Lecture 96
Method 3: Incremental AnalysisMotivation: music over a light beam
Can we pull this off?
LED: LightEmittingexpoDweep ☺
Dv+
-
)(t v + –
Di
LED
i
AMP
light intensity I Rin photoreceiver
Ri ∝lightintensity
D D i I ∝
I v
t
music signal
)(t v I light sound)(t i R)(t i D
nonlinearlinear
problem! will result in distortion
8/20/2019 Circuit & Electronics.pdf
115/414
6.002 Fall 2000 Lecture 106
Problem:The LED is nonlinear distortion
D vv =
Dv
Di
vD
t
t
Di v D
Di
t
8/20/2019 Circuit & Electronics.pdf
116/414
6.002 Fall 2000 Lecture 116
If only it were linear …
vD
t
Di
Dv
Di
it would’ve been ok.What do we do?
Zen is the answer
… next lecture!
8/20/2019 Circuit & Electronics.pdf
117/414
6.002 Fall 2000 Lecture 17
6.002 CIRCUITS ANDELECTRONICS
Incremental Analysis
8/20/2019 Circuit & Electronics.pdf
118/414
6.002 Fall 2000 Lecture 27
Nonlinear Analysis
Analytical method
Graphical method
Today
Incremental analysis
Reading: Section 4.5
Review
8/20/2019 Circuit & Electronics.pdf
119/414
6.002 Fall 2000 Lecture 37
Method 3: Incremental AnalysisMotivation: music over a light beam
Can we pull this off?
LED: LightEmittingexpoDweep ☺
Dv+
-
)(t v + –
Di
LED
i
AMP
light intensity I Rin photoreceiver
Ri ∝lightintensity
D D i I ∝
I v
t
music signal
)(t v I light sound)(t i R)(t i D
nonlinearlinear
problem! will result in distortion
8/20/2019 Circuit & Electronics.pdf
120/414
6.002 Fall 2000 Lecture 47
Problem:The LED is nonlinear distortion
D vv =
Dv
Di
vD
t
t
Di v D
Di
t
8/20/2019 Circuit & Electronics.pdf
121/414
6.002 Fall 2000 Lecture 57
Insight:
D
v
Di
D I
DV
DC offsetor DC bias
Trick:
d D D ii +=
I V
Dv+
-
)(t vi+ –
LED+ –
v
d D D vV v +=
I V iv
small regionlooks linear(about V D , I D)
8/20/2019 Circuit & Electronics.pdf
122/414
6.002 Fall 2000 Lecture 67
Result
v d very small
Di
Dv
d i
D
DV
8/20/2019 Circuit & Electronics.pdf
123/414
6.002 Fall 2000 Lecture 77
Result
t
Dv DV
I D vv =
t
D
Di
~linear!
Demo
d v
d i Di
8/20/2019 Circuit & Electronics.pdf
124/414
6.002 Fall 2000 Lecture 87
total
variable
DC
offset
small
superimposedsignal
The incremental method:(or small signal method)
1. Operate at some DC offsetor bias point V D, I D .
2. Superimpose small signal vd (music) on top of V D .
3. Response id to small signal vd is approximately linear.
Notation:
d D D i I i +=
8/20/2019 Circuit & Electronics.pdf
125/414
6.002 Fall 2000 Lecture 97
( ) D D v f i =
What does this meanmathematically?
Or, why is the small signal responselinear?
We replaced
D D D vV v ∆+=
using Taylor’s Expansion to expand
f(v D ) near v D=V D :( ) D
V v D
D D D v
dv
vdf V f i
D D
∆⋅+=
=
)(
+∆⋅+
=
2
2
2 )(
!2
1 D
V v D
D
vdv
v f d
D D
large DC
incrementabout V D
nonlinear
d v
neglect higher order terms
because is small Dv∆
8/20/2019 Circuit & Electronics.pdf
126/414
6.002 Fall 2000 Lecture 107
( ) DV v D
D D D v
vd
v f d V f i
D D
∆⋅+≈
=
)(
equating DC and time-varying parts,
D
V v D
D D v
vd
v f d i
D D
∆⋅=∆
=
)(
constantw.r.t. ∆v D
constant w.r.t. ∆v Dslope at V D, I D
( ) D D V f = operating point
constant w.r.t. ∆v D
X :We can write
( ) DV v D
D D D D v
vd
v f d V f i I
D D
∆⋅+≈∆+
=
)(
so, D D vi ∆∝∆
By notation,
d D ii =∆
d D vv =∆
8/20/2019 Circuit & Electronics.pdf
127/414
6.002 Fall 2000 Lecture 117
Equate DC and incremental terms,
Dbv
D eai =
From X :
constant
In our example,
d
bV bV
d D vbeaeai I D D ⋅⋅+≈+
DbV
D ea I =
d
bV
d vbeai D ⋅⋅=
operating point
d Dd vbi ⋅⋅=
small signalbehaviorlinear!
aka bias pt.aka DC offset
8/20/2019 Circuit & Electronics.pdf
128/414
6.002 Fall 2000 Lecture 127
DbV
D ea I = operating point
d Dd vb I i ⋅⋅=
Dv
Di
D I
DV
slope at
V D, I D
operating
point
we areapproximatingA with B
A
B
d v
d i
Graphical interpretation
8/20/2019 Circuit & Electronics.pdf
129/414
6.002 Fall 2000 Lecture 137
We saw the small signal
D I
I V DV +
-
+ – LED DbV
D ea I =
Large signal circuit:
Small signal response: d Dd vbi =
graphically
mathematically
now, circuit
small signal circuit:
Linear!
d i
iv d v+
- b I D
1+ –
behaves like:d v+ -
d i
b I
1 R
D
=
8/20/2019 Circuit & Electronics.pdf
130/4146.002 – Fall 2002: Lecture 8 1
6.002 CIRCUITS ANDELECTRONICS
Dependent Sources
and Amplifiers
8/20/2019 Circuit & Electronics.pdf
131/4146.002 – Fall 2002: Lecture 8 2
Nonlinear circuits — can use thenode method
Small signal trick resulted in linearresponse
Today
Dependent sources
Reading: Chapter 7.1, 7.2
Review
Amplifiers
8/20/2019 Circuit & Electronics.pdf
132/4146.002 – Fall 2002: Lecture 8 3
Dependent sources
+ –v
ivi =Resistor
2-terminal 1-port devices
+ –v
i i = I
IndependentCurrent source
Seen previously
controlport
outputport
i
I v
Oi
Ov
+
–
+
–
New type of device: Dependent source
2-port device
E.g., Voltage Controlled Current SourceCurrent at output port is a function of voltage
at the input port
)v( f I
8/20/2019 Circuit & Electronics.pdf
133/4146.002 – Fall 2002: Lecture 8 4
Dependent Sources: Examples
independentcurrentsource
Example 1: Find V
0=
+
–V
V 0
=
8/20/2019 Circuit & Electronics.pdf
134/4146.002 – Fall 2002: Lecture 8 5
voltagecontroledcurrent
source
Example 2: Find V
( ) V K
V f I ==
+
–V
i
I v
Oi
Ov
+
–
+
–
+
–V
( ) I
I v
K v f =
Dependent Sources: Examples
8/20/2019 Circuit & Electronics.pdf
135/4146.002 – Fall 2002: Lecture 8 6
voltagecontroledcurrentsource
RV
K IRV ==
KRV =2
KRV =33
1010 ⋅= −
Volt 1=
oror
Example 2: Find V
( ) V K
V f I ==
+
–V
e.g. K = 10-3 Amp·Volt R = 1k Ω
Dependent Sources: Examples
8/20/2019 Circuit & Electronics.pdf
136/4146.002 – Fall 2002: Lecture 8 7
Another dependent source example
v + –
( ) IN D v f i =
L
+ –S
V
e.g. ( ) N D v f i =
( )2 IN 1v2
K −= for v IN ≥ 1
IN i
IN v
Di
Ov
+
–
+
–
otherwise0i D =
Find vO as a function of v I .
8/20/2019 Circuit & Electronics.pdf
137/4146.002 – Fall 2002: Lecture 8 8
Another dependent source example
v + –
( ) IN D v f i =
L
S V
e.g. ( ) N D v f i =
( )2 IN 1v2
K −= for v IN ≥ 1
IN i
IN v
Di
Ov
+
–
+
–
otherwise0i D =
Find vO as a function of v I .
8/20/2019 Circuit & Electronics.pdf
138/4146.002 – Fall 2002: Lecture 8 9
Another dependent source example
Find vO as a function of v I .
I v + –
I v
S V
Ov
L
( )2 IN D 1v2
K i −= for v IN ≥ 1
otherwise0i D =
8/20/2019 Circuit & Electronics.pdf
139/4146.002 – Fall 2002: Lecture 8 10
Another dependent source example
0=++− O L DS viV
KVL
L DS O iV v −=
( ) L I S O Rv K
V v 2
12
−−= for v I ≥ 1
S O V v = for v I < 1
I v + –
I v
S V
Ov
L
( )2 IN D 1v2
K i −= for v IN ≥ 1
otherwise0i D =
Hold that thought
8/20/2019 Circuit & Electronics.pdf
140/4146.002 – Fall 2002: Lecture 8 11
Next, Amplifiers
8/20/2019 Circuit & Electronics.pdf
141/4146.002 – Fall 2002: Lecture 8 12
Why amplify?Signal amplification key to both analogand digital processing.
Analog:
Besides the obvious advantages of being
heard farther away, amplification is keyto noise tolerance during communication
AMP IN OUT
InputPort
OutputPort
8/20/2019 Circuit & Electronics.pdf
142/4146.002 – Fall 2002: Lecture 8 13
Why amplify?
Amplification is key to noise toleranceduring communication
usefulsignal
huh?
1 mV n o i
s e10 mV
No amplification
8/20/2019 Circuit & Electronics.pdf
143/4146.002 – Fall 2002: Lecture 8 14
AMP
Try amplification
not bad!
n o i s e
8/20/2019 Circuit & Electronics.pdf
144/4146.002 – Fall 2002: Lecture 8 15
Why amplify?Digital:
IN OUT
Digital System
LV IH V
5V
0V OLV
OH V 5V
0V
t
5V
0V
ILV
IH V
IN OUT
t
5V
0V OL
V
OH V
Valid region
8/20/2019 Circuit & Electronics.pdf
145/4146.002 – Fall 2002: Lecture 8 16
Why amplify?Digital:
Static discipline requires amplification!
Minimum amplification needed:
ILV IH V
OLV
OH V
L H
OLOH
V V
V V
−
−
8/20/2019 Circuit & Electronics.pdf
146/4146.002 – Fall 2002: Lecture 8 17
An amplifier is a 3-ported device, actually
We often don’t show the power port.
Also, for convenience we commonly observe“the common ground discipline.”
In other words, all ports often share acommon reference point called “ground.”
How do we build one?
POWER
IN OUT
Amplifier
Power port
Inputport
Outputport
i
I v
Oi
Ov+ –
+
–
8/20/2019 Circuit & Electronics.pdf
147/4146.002 – Fall 2002: Lecture 8 18
Remember?
0=++− O L DS viV
KVL
L DS O iV v −=
( ) L I S O Rv K
V v 2
12
−−= for v I ≥ 1
S O V v = for v I < 1
Claim: This is an amplifier
I v + –
I v
S V
Ov
L
( )2 IN D 1v2
K i −= for v IN ≥ 1
otherwise0i D =
8/20/2019 Circuit & Electronics.pdf
148/4146.002 – Fall 2002: Lecture 8 19
So, where’s the amplification?
Let’s look at the vO versus v I curve.
amplification1>∆
∆ O
v
v
Ω===
k 5 R ,V
mA
2 K ,V 10V L2S e.g.
Ov∆
I v∆
( )212
−−= I LS O v R K
V v
( )21510 −−=O vv
( )233 110510
2
210 −⋅⋅⋅−=
−
I v
1 I v
S V
Ov
8/20/2019 Circuit & Electronics.pdf
149/4146.002 – Fall 2002: Lecture 8 20
Plot vO versus v I
( )
2
O 1v510v −−=
10.001.0
~ 0.002.4
1.502.3
2.802.2
4.002.1
5.002.0
8.751.5
10.000.0
vOv I
0.1 changein v I
1V changein vO
Gain!
Measure vO .Demo
8/20/2019 Circuit & Electronics.pdf
150/4146.002 – Fall 2002: Lecture 8 21
One nit …
1
v
Ov
Mathematically,
( )212
−−= I LS O v R K V v
Whathappenshere?
So is mathematically predicted behavior
8/20/2019 Circuit & Electronics.pdf
151/4146.002 – Fall 2002: Lecture 8 22
One nit …
Di
S V
Ov L
VCCS
1
v
Ov
For vO>0, VCCS consumes power: vO i DFor vO
8/20/2019 Circuit & Electronics.pdf
152/4146.002 – Fall 2002: Lecture 8 23
If VCCS is a device that can sourcepower, then the mathematicallypredicted behavior will be observed —
( )212
−−= I LS O v R K
V vi.e.
where vO goes -ve I v
Ov
8/20/2019 Circuit & Electronics.pdf
153/4146.002 – Fall 2002: Lecture 8 24
If VCCS is a passive device,then it cannot source power,so vO cannot go -ve.So, something must give!
Turns out, our model breaks down.
( )212
−= I D v K
iCommonly
will no longer be valid when vO ≤ 0 .
e.g. i D saturates (stops increasing)
and we observe:
I v
Ov
1
8/20/2019 Circuit & Electronics.pdf
154/414
6.002 Fall 2000 Lecture 19
6.002 CIRCUITS ANDELECTRONICS
MOSFET Amplifier
Large Signal Analysis
8/20/2019 Circuit & Electronics.pdf
155/414
6.002 Fall 2000 Lecture 29
Amp constructed using dependent source
Superposition with dependent sources:one way leave all dependent sources in;solve for one independent source at a
time [section 3.5.1 of the text] Next, quick review of amp …
Reading: Chapter 7.3–7.7
+ –+
–a′
a
v
b′
b
)(vi =
a′a
b′bcontrol
port DS outputport
Dependent source in a circuit
Review
8/20/2019 Circuit & Electronics.pdf
156/414
6.002 Fall 2000 Lecture 39
Amp review
L DS O iV v −=
( )2 I 1v2
K −
forv I ≥ 1V
= 0 otherwise
S V
Ov
L
+ –
( )2 I D 1v2
K i −=
v
VCCS
8/20/2019 Circuit & Electronics.pdf
157/414
6.002 Fall 2000 Lecture 49
Key device Needed:
Let’s look at our old friend, the MOSFET …
A
Bv
C
( )v f i =voltage controlled
current source
8/20/2019 Circuit & Electronics.pdf
158/414
6.002 Fall 2000 Lecture 59
Key device Needed:
Our old friend, the MOSFET …
First, we sort of lied. The on-state behavior of theMOSFET is quite a bit more complex than either theideal switch or the resistor model would have you believe.
D
S
G
D
S
T GS V v <
G
T GS V v ≥?
8/20/2019 Circuit & Electronics.pdf
159/414
6.002 Fall 2000 Lecture 69
Graphically
DS v
DS i
T GS V v ≥
T GS V v <
T GS
V v ≥
1GS v
Saturationregion
T r i o
d e
r e g i o
n
S MODEL
DS v
DS i
SR MODEL
Dv
DS i
Demo
T GS V v <
T GS V v <
2GS v
3GS v
+ – DS v
+
–
DS iGS v
.
.
.
GS DS Vvv −=
Cutoff
region
8/20/2019 Circuit & Electronics.pdf
160/414
6.002 Fall 2000 Lecture 79
Graphically
DS v
DS i
T GS V v ≥
T GS V v <
T GS
V v ≥
1GS v
Saturationregion
T r i o
d e
r e g i o
n
S MODEL
DS v
DS i
SR MODEL
DSv
DS i
T GS V v <
T GS V v <
2GS v
3GS v
+ – DS v
+
–
DS iGS v
.
.
.
TGS DS V vv −=
Notice thatMOSFETbehaves like a
current source
whenT GS DS V vv −≥
8/20/2019 Circuit & Electronics.pdf
161/414
6.002 Fall 2000 Lecture 89
MOSFET SCS Model
D
S
G
D
S
T GS V v <
G
( )22
T GS V v K
−=
whenT GS DS V vv −≥
( )GS DS v f i =
T GS V v ≥
D
S
G
When
the MOSFET is in its saturation region, and theswitch current source (SCS) model of the MOSFET ismore accurate than the S or SR model
T GS DS V vv −≥
8/20/2019 Circuit & Electronics.pdf
162/414
6.002 Fall 2000 Lecture 99
Reconciling the models…
T GS DS V vv −≥
T GS DS V vv −<use SCS modeluse SR model
Note: alternatively (in more advanced courses)
or, use SU Model (Section 7.8 of A&L)
S MODEL SR MODEL SCS MODELfor fun!
for digitaldesigns
for analogdesigns
When to use each model in 6.002?
DS v
DS i
T GS V v ≥
T GS V v <
T GS V v ≥
1GS v
Saturationregion
T r i o
d e
r e g i o
n
DS v
DS i
Dv
DS i
T GS V v <
T GS V v <
2GS v
3GS v .
.
.
GS DS
Vvv −=
8/20/2019 Circuit & Electronics.pdf
163/414
6.002 Fall 2000 Lecture 109
Back to Amplifier
in saturationregion
I
v O
v MP
S V
S V
L
I v
Ov
G D
S
( )2
2 T I DS V v
K i −=
To ensure the MOSFET operates as a VCCS
we must operate it in its saturation regiononly. To do so, we promise to adhere to the
“saturation discipline”
8/20/2019 Circuit & Electronics.pdf
164/414
6.002 Fall 2000 Lecture 119
MOSFET Amplifier
in saturationregion
S V
L
I v
Ov
G D
S ( )2
2 T I DS V v
K i −=
To ensure the MOSFET operates as a VCCS,
we must operate it in its saturation regiononly. We promise to adhere to the“saturation discipline.”
In other words, we will operate the amp
circuit such that
vGS
≥ V T
and v DS
≥ vGS
– V T
at all times.vO ≥ v
I – v
T
8/20/2019 Circuit & Electronics.pdf
165/414
6.002 Fall 2000 Lecture 129
Let’s analyze the circuitFirst, replace the MOSFET with its
SCS model.
forT I O V vv −≥GS
vv =
G
I v+
–
+ –
S V
Ov
L
D
S
A( )22
T I DS V v K
i −=
8/20/2019 Circuit & Electronics.pdf
166/414
6.002 Fall 2000 Lecture 139
Let’s analyze the circuit
forT I O V vv −≥GS
vv =
G
I v+
–
+ –
S V
Ov
L
D
S
A( )2
2
T I DS V v K
i −=
or ( ) LT I S O RV v K
V v2
2−−= for T I V v ≥
T O V vv −≥
S O V v =for T V v <
(MOSFET turns off)
L DS S O iV v −= B1 Analytical method: I O vvsv
(vO = v DS DS in our examplein our example ) )
8/20/2019 Circuit & Electronics.pdf
167/414
6.002 Fall 2000 Lecture 149
2 Graphical method
:B
From A ( ) ,2
2
T I DS V v K
i −=:
2
O DS
DS O
T I O
v2
K i
K
i2v
V vv
≤
⇓
≥
⇓
−≥for
I O vvsv
L
0
L
S DS
R
v
R
V i −=
8/20/2019 Circuit & Electronics.pdf
168/414
6.002 Fall 2000 Lecture 159
2 Graphical method
:B
Constraints and must be metA B
A ( ) ,2
2
T I DS V v K
i −=:
S V
DS i
Ov
2
2 O DS v
K i ≤
L
S
R
V
L o a d l i n e
B
for
GS v=
I v
A
2
2 O DS v
K i ≤
L
O
L
S DS
R
v
R
V i −=
I O vvsv
8/20/2019 Circuit & Electronics.pdf
169/414
6.002 Fall 2000 Lecture 169
2 Graphical method
Constraints and must be met.Then, given V I , we can find V O, I DS .A B
S V
DS i
Ov
L
S
R
V
B I v
A
2
2 O DS v
K i ≤
I O vvsv
I V DS I
OV
8/20/2019 Circuit & Electronics.pdf
170/414
6.002 Fall 2000 Lecture 179
Large Signal Analysisof Amplifier
(under “saturation discipline”)
1 vO versus v I
2 Valid input operating range andvalid output operating range
8/20/2019 Circuit & Electronics.pdf
171/414
6.002 Fall 2000 Lecture 189
Large Signal Analysis
1 vO versus v I
v
S V
( ) LT I S RV v K
V 2
2
−−Ov
T V
gets intotriode region
T O V vv −=
8/20/2019 Circuit & Electronics.pdf
172/414
6.002 Fall 2000 Lecture 199
2 What are valid operating ranges
under the saturation discipline?
DS i
Ov
2
2 O DS v
K i ≤
S V
L
S
R
V
L
O
L
S DS
R
v
R
V i −=
Large Signal Analysis
T I O
T I
V vv
V v
−≥
≥2
2 O DS v
K i ≤
OurConstraints
=T I
0=
DS i=
S O V v
V v
and
?
I v
( )22
T I DS V v K
i −=
8/20/2019 Circuit & Electronics.pdf
173/414
6.002 Fall 2000 Lecture 209
=T I
0= DS i= S O V v
V v
and
2 What are valid operating rangesunder the saturation discipline?
DS i
Ov
2
2 O DS v
K i ≤
L
O
L
S DS
R
v
R
V i −=
Large Signal Analysis
I v
( )2
2 T I DS V v
K i −=
L
S LT I
KR
V KRV v
211 ++−+=
L
S LO
KR
V KRv
211 ++−=
L
O
L
S DS
R
v
R
V i −=
8/20/2019 Circuit & Electronics.pdf
174/414
6.002 Fall 2000 Lecture 219
Valid input range:
L
S L
T KR
V KR
V
211 ++−+
v I : V T to
corresponding output range:
L
S L
KR
V KR211 ++−
vO : V S to
2 Valid operating ranges under thesaturation discipline?
Large Signal AnalysisSummary
1 vO versus v I
( ) L2
T I S O RV v2
K V v −−=
8/20/2019 Circuit & Electronics.pdf
175/414
6.002 CIRCUITS AND ELECTRONICS
Amplifiers --
Small Signal Model
6.002 Fall 2000 Lecture 10 1
8/20/2019 Circuit & Electronics.pdf
176/414
Review
MOSFET amp
SV
L
DSi
vO
v I
Saturation discipline — operateMOSFET only in saturation region
Large signal analysis1. Find vO vs v I under saturation discipline.
2. Validv I, v
O ranges under saturation discipline.
Reading: Small signal model -- Chapter 8
6.002 Fall 2000 Lecture 10 2
8/20/2019 Circuit & Electronics.pdf
177/414
Large Signal Review
1 vO vs v I
vO = V S − K
(v I −1)2 R L
2
valid for v I ≥ V TandvO ≥ v I – V T(same as i DS ≤
KvO
2 )2
6.002 Fall 2000 Lecture 10 3
8/20/2019 Circuit & Electronics.pdf
178/414
Large Signal Review
2 Valid operating ranges
v
V
5V corresponding v I −V T
interesting v I −V Tregion for vO v I −V T
S
O
Ov =
Ov >
Ov
8/20/2019 Circuit & Electronics.pdf
179/414
But…
S V
Ov
Ov =
I v
5V
1V
v I −V T
v I
vO
Demo
V T 1V 2V
Amplifies alright,but distortsv I
vO
t
Amp is nonlinear … /
6.002 Fall 2000 Lecture 10 5
8/20/2019 Circuit & Electronics.pdf
180/414
Small Signal Model
~ 5V V S
~1V
Hmmm …
( ) L
T I
SO R
V v K
V v 2
2−
−
=
Amp all right, but nonlinear!
Iv
Ov
TV
V1 V2~
Insight:
( )
O I V ,V
Focus on this line segment
So what about our linear amplifier ???
But, observe v I vs vO about somepoint (V I , V O) … looks quite linear !
6.002 Fall 2000 Lecture 10 6
8/20/2019 Circuit & Electronics.pdf
181/414
Trickov
iv
I V
OV
(
)OV V ,Ov∆
lookslinear
∆v I
Operate amp at V I
, V O
Æ
DC “bias” (good choice: midpointof input operating range)
Superimpose small signal on top of V I Response to small signal seems to be
approximately linear
6.002 Fall 2000 Lecture 10 7
8/20/2019 Circuit & Electronics.pdf
182/414
Trickov
iv
I V
OV
(
)OV V ,Ov∆
lookslinear
∆v I Operate amp at V I , V OÆ
DC “bias” (good choice: midpointof input operating range)
Superimpose small signal on top of V I Response to small signal seems to be
approximately linear
Let’s look at this in more detail —I
III from a circuit viewpoint
graphically nextII mathematically week
6.002 Fall 2000 Lecture 10 8
8/20/2019 Circuit & Electronics.pdf
183/414
I Graphically
We use a DC bias V I to “boost” interesting inputsignal above V T , and in fact, well above V T .
interestinginput signal
+
–
+ –
SV
L
vO
∆v I
V I
Offset voltage or bias
6.002 Fall 2000 Lecture 10 9
8/20/2019 Circuit & Electronics.pdf
184/414
Graphically
interesting
vO∆v I
SV
L
+ –
+ –
input signal
V I
SV Ov
OV
operatingpoint
O I V V ,
IV
TV
O vv =
0
I −V Tv
I
Good choice for operating point:midpoint of input operating range
6.002 Fall 2000 Lecture 10 10
8/20/2019 Circuit & Electronics.pdf
185/414
Small Signal Modelaka incremental modelaka linearized model
Notation —Input:
total
v I = V I + vi
DC smallvariable bias signal (like ∆v I )
bias voltage aka operating point voltage
Output: vO = V O + vo
Graphically,v vvi vo
V IV O
O
0
t 0
t
6.002 Fall 2000 Lecture 10 11
8/20/2019 Circuit & Electronics.pdf
186/414
II Mathematically(… watch my fingers)
vO =
V S −
R L K
(v I −V T )2
V O =
V S −
R L
K
(V I −V T2 2
substituting v I = V I + vi vi
8/20/2019 Circuit & Electronics.pdf
187/414
Mathematically
vo = − R L K ( T I )V −V vi
g m related to V I
vo = − g m R L vi
For a given DC operating point voltage V I ,
V I – V T is constant. So,
vo = − A vi
constant w.r.t. vi
In other words, our circuit behaves like a linear amplifier
for small signals
6.002 Fall 2000 Lecture 10 13
8/20/2019 Circuit & Electronics.pdf
188/414
Another way
vO
= V S
− R L K (v
I
−V T
)2
2
vo =
dv
d
I
V S
− R
L2
K(v I
−V T
)2
⋅ vi
Iv = V
slope at V I
vo = − R L K (V I −V T ) ⋅ vi
g m = K (V I −V T )
A = − g m R L amp gain
Also, see Figure 8.9 in the course notes
for a graphical interpretation of this result
6.002 Fall 2000 Lecture 10 14
8/20/2019 Circuit & Electronics.pdf
189/414
More next lecture …
Demo DS i
I V
Ov
load line
operating pointinput signal response
V O
How to choose the bias point:
1. Gain component g m ∝ V I2. vi gets big Æ distortion.
So bias carefully3. Input valid operating range.
Bias at midpoint of input operatingrange for maximum swing.
6.002 Fall 2000 Lecture 10 15
8/20/2019 Circuit & Electronics.pdf
190/414
6.002 Fall 2000 Lecture 111
6.002 CIRCUITS ANDELECTRONICS
Small Signal Circuits
8/20/2019 Circuit & Electronics.pdf
191/414
6.002 Fall 2000 Lecture 211
Small signal notation
v A = V A + va
total operatingpoint
smallsignal
( ) iV v
I
I
out
I OUT
vv f dv
d v
v f v
I I
⋅=
=
=
)(
S V
L
oOO vV v +=
I V
+ –
+ –
i I I vV v +=
iv
Review:
8/20/2019 Circuit & Electronics.pdf
192/414
6.002 Fall 2000 Lecture 311
I Graphical view
(using transfer function)
behaves linear
for smallperturbations
I v
Ov
Review:
8/20/2019 Circuit & Electronics.pdf
193/414
6.002 Fall 2000 Lecture 411
II Mathematical view
( ) L
T I S O R
V v K V v
2
2−
−=
( )
i
V v
LT I S
I
o v
RV v K
V
dv
d v
I I
⋅
−−
=
=
2
2
related to V Iconstant for fixed
DC bias
( ) i LT I o vV V K v ⋅−−=
g m
Review:
8/20/2019 Circuit & Electronics.pdf
194/414
6.002 Fall 2000 Lecture 511
Demo
Choosing a bias point:
DS i
Ov
L
S LT I
KR
V KRV v
211 ++−+=
T I V v =
2
O DS v2
i <
load line L
O
L
S DS
R
v
R
V i −=
How to choose the bias point,using yet another graphical viewbased on the load line
OV
I V
input signalresponse
I Lm V ∝1. Gain
2. Input valid operating range for amp.
3. Bias to select gain and input swing.
8/20/2019 Circuit & Electronics.pdf
195/414
6.002 Fall 2000 Lecture 611
III The Small Signal Circuit View
We can derive small circuit equivalentmodels for our devices, and thereby conductsmall signal analysis directly on circuits
( )2T I D V v2
K i −=
+
–OUT v V S
+ –
v 1
e.g. large signalcircuit modelfor amp
We can replace large signal models withsmall signal circuit models.
Foundations: Section 8.2.1 and also in the
last slide in this lecture.
8/20/2019 Circuit & Electronics.pdf
196/414
6.002 Fall 2000 Lecture 711
Small Signal Circuit Analysis
1 Find operating point using DC bias
inputs using large signal model.
Develop small signal (linearized)models for elements.
Replace original elements with smallsignal models.
2
3
Analyze resulting linearized circuit…
Key: Can use superposition and otherlinear circuit tools with linearizedcircuit!
8/20/2019 Circuit & Electronics.pdf
197/414
6.002 Fall 2000 Lecture 811
Small Signal Models
MOSFET A
largesignal ( )
2
2 T GS DS V v
K i −=
D
S
GS v
Small signal?
8/20/2019 Circuit & Electronics.pdf
198/414
6.002 Fall 2000 Lecture 911
Small Signal Models
MOSFET A
largesignal ( )
2
2 T GS DS V v
K i −=
D
S
GS v
Small signal:
smallsignal
D
S
gsv
( ) gsT GS ds vV V K i −=
gsmds vi =
( )22
T GS DS V v K
i −=
( ) gsV v
T GS GS
ds
vV v K
vi
GS GS
⋅
−∂
∂=
=
2
2
( ) gsT GS ds vV V K i ⋅−=
g m
ids is linear in v gs !
8/20/2019 Circuit & Electronics.pdf
199/414
6.002 Fall 2000 Lecture 1011
DC Supply V S
B
largesignal
S S V v =
s
I iS
S s i
i
V v
S S
⋅∂
∂=
=
0v s =
+ – S S
V v =
S i
+
– sv
si
DC source behaves
as short to smallsignals.
Small signal
8/20/2019 Circuit & Electronics.pdf
200/414
6.002 Fall 2000 Lecture 1111
Similarly, RC
largesignal
smallsignal
+
–
vi
+
–r v
r i
R iv =
( )r
I i R
Rr i
i
Riv
R R
⋅∂
∂=
=
r r iv ⋅=
8/20/2019 Circuit & Electronics.pdf
201/414
6.002 Fall 2000 Lecture 1211
Large signal
( )22
T I DS V v K
i −=
( ) LT I S O RV v K
V v2
2−−=
L
Ov
+ – I v
+ – S V
DS i
L
ov
+ – i
v dsi
( ) iT I ds vV V K i ⋅−=
0=+ o Lds vi
Ldso iv −=
( ) i LT I o vV V K v ⋅−−=
i Lm v g ⋅−=
Small signal
Amplifier example:
Notice, first we need to find operatingpoint voltages/currents.
Get these from a large signal analysis.
8/20/2019 Circuit & Electronics.pdf
202/414
6.002 Fall 2000 Lecture 1311
To find the relationship between the small signal parameters ofa circuit, we can replace large signal device models withcorresponding small signal device models, and then analyze theresulting small signal circuit.
Foundations: (Also see section 8.2.1 of A&L)
KVL, KCL applied to some circuit C yields:
III The Small Signal Circuit View
b Bout OUT a A vV vV vV +++++++
Replace total variables withoperating point variables plus small signal variables
Operating point variables themselves satisfy thesame KVL, KCL equations
BOUT A V V V ++++ so, we can cancel them out
BOUT A vvv ++++++ 1
bout a vvv ++++
Leaving
2
Since small signal models are linear, our linear tools will nowapply…
But is the same equation as with small signalvariables replacing total variables, so must reflect sametopology as in C, except that small signal models are used.
2 1
2
8/20/2019 Circuit & Electronics.pdf
203/414
6.002 Fall 2000 Lecture 112
6.002 CIRCUITS ANDELECTRONICS
Capacitorsand First-Order Systems
8/20/2019 Circuit & Electronics.pdf
204/414
6.002 Fall 2000 Lecture 212
5V
0V
C
A
B
5V
A
B
C
5
0
5
0
5
0
Reading:
Chapters 9 & 10
Demo 5V
Expected
Observed
Expect this, right?But observe this!
Delay!
Motivation
8/20/2019 Circuit & Electronics.pdf
205/414
6.002 Fall 2000 Lecture 312
The Capacitor
G
D
S
n-channel MOSFET symbol
n-channelMOSFET
n-channel
s
i
l
i
co
n
n
met
al
++++++
oxi
de
drain
gate
source
C GS
G D
S
n
p
8/20/2019 Circuit & Electronics.pdf
206/414
6.002 Fall 2000 Lecture 412
Ideal Linear Capacitor
obeys DMD!
total charge oncapacitor0qq =−+=
d
EAC =
+ ++ + + +
- -- - - - -
A
E
d
coulombs farads volts
vC q =
i
C
q +
–v
8/20/2019 Circuit & Electronics.pdf
207/414
6.002 Fall 2000 Lecture 512
Ideal Linear Capacitor
dt dqi =
( )dt
Cvd =
dt dvC =
i
vC q =
C q +
–v
A capacitor is an energy storage device memory device history matters!
= 22
1Cv E
8/20/2019 Circuit & Electronics.pdf
208/414
6.002 Fall 2000 Lecture 612
Apply node method:
C
+
–( )t vC
( )t v I + –
Thévenin Equivalent:
0=+−dt dv