Chapter 6
Sequential System Design
Computer Engineering KhonKaen University
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Digital Logic Design @Department of Computer Engineering KKU
Topic
❑Shift Registers
❑Synchronous & Asynchronous
Counters
❑Programmable Logic Devices (PLD)
❑Hardware Design Languages
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Shift Register
▪ data is often stored in registers, rather than
individual flip-flops.
▪ A register is just a collection of flip-flops,
often with a common name (using subscripts
to indicate the individual flip-flops) and
usually with a common clock.
▪ A shift register is a set of flip-flops, such that
the data moves one place to the right on
each clock or shift input.
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Digital Logic Design @Department of Computer Engineering KKU
A simple shift register
and its timing trace
x 1 0 1 1 1 0 1 1 1 1 0 0 0
Q10 1 0 1 1 1 0 1 1 1 1 0 0 0
Q2 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0
Q3 0 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0
Q4 0 0 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0
Clock
S
R
q1
q2
S q1
q2R
S q1
q2R
S q1
q2R
X
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Digital Logic Design @Department of Computer Engineering KKU
Shift Register (cont.)
▪ Serial-in / Parallel-in Shift Registers
▪ Serial-out / Parallel-out Shift Registers
▪ Right / Left Shift Registers
▪ Leading-edge / Trailing-edge Shift Registers
▪ Enable, Clear, Load pins
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74164
Serial-in parallel-out shift register
Serial-in
Parallel-out
AQD
SET
CLR
Q
D Q
SET
CLR
Q
SET
D Q
CLR
Q
SET
QD
CLR
Q
QD
SET
CLRQ
SET
QD
CLR
Q
SET
QD
CLR
Q
D
SET
Q
CLR
Q
B
Clock
Clear'
q1 q2 q3 q4 q5 q6 q7 q8
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Digital Logic Design @Department of Computer Engineering KKU
Parallel-in Shift Register
loading is donestatically
loading is donesynchronously
Clock
(a) 74165
Q
SET
S
CLR
QREnable'
Load'
q1
q1'
q2
q2'
IN2
Clock
Q
SET
S
CLR
QR
q2
q2'
Enable'
q1
IN2
Load'Clear'
(b) 74166
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Clear’ S0 S1 q1* q2* q3* q4*
Static clear 0 X X 0 0 0 0
Hold 1 0 0 q1 q2 q3 q4
Shift left 1 0 1 q2 q3 q4 LS
Shift right 1 1 0 RS q1 q2 q3
Load 1 1 1 IN1 IN2 IN3 IN4
Figure 6.7 Right/left shift register.
Table 6.1 Right/left shift register.
Clock
S q2
CLR'
q'2R
q1
IN2
q3
Clear'
S1
S0
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Clock
Clear'
CJ
CLR'
C'K
Load'
B
A
ENP
ENT
INC z
x
y
w
Figure 6.8 The 74161 counter.
ENT
74161
C B ADENP
CLR'
Load'INAINBINCIND
Clock
OV
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Digital Logic Design @Department of Computer Engineering KKU
Figure 6.9 8-bit counter.
8-bit counter from two 74161 counters
can count to 255 (28 - 1)
12-bit counter from three 74161 counterscan count to 4095 (212 - 1)
Clear'
High
D C B A
OV
CLR' LD' ENT ENP
Low
D C B A
OV
CLR' LD' ENT ENP
Clock
1
O7 O6 O5 O4 O3 O2 O1 O0
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Digital Logic Design @Department of Computer Engineering KKU
Figure 6.10 Typical bit of the 7419 Down/Up’ counter.
LD’ EN’ D/U’
0 X X Static load
1 1 X Do nothing
1 0 0 Clocked count up
1 0 1 Clocked count down
Figure 6.11 The 74191 Down/Up’ counter.
Load'
Clock
CJ
CLR'
C'K
PRE'
Enable'
D/U'
INC
A'B'
AB
AD C B A
OV
CLR' LD' EN' D/U'
B
C
D
IN
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Digital Logic Design @Department of Computer Engineering KKU
Flip-flop Design Techniques
▪ D Flip-flop
▪ SR Flip-flop
▪ T Flip-flop
▪ JK Flip-flop
q*=D
qKqJq* +=
qRSq* +=
q*=Tq
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Digital Logic Design @Department of Computer Engineering KKU
Flip-flop Design Techniques (cont.)
From the truth table, it’s
clear that
We need to create the
appropriate flip-flop
design table to obtain a
truth table for the flip-flop inputs.
z=q1q2
q q* Input(s)
0 0
0 1
1 0
1 1
• D flip-flops
• SR flip-flops
• T flip-flops• JK flip-flops
x q1 q2 q1* q2* z
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 1 1 1
Main truth table
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Digital Logic Design @Department of Computer Engineering KKU
Design with D Flip-flop
D q*
0 0
1 1
q q* D
0 0 0
0 1 1
1 0 0
1 1 1
x q1 q2 D1=q1* D2=q2*
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 1 1
From the main truth table
q*=D
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Digital Logic Design @Department of Computer Engineering KKU
0
1
1
1
1
00
01
11
10
Xq1q2
0
1
1
1
1
00
01
11
10
Xq1q2
Design with D Flip-flop (cont.)
122 121 xqqxDxqxqD +=+=
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Implementation using D Flip-flops
back
Clock
ZD q1
q'1
D q2
q'2
X
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Design with SR Flip-flop
S R q*
0 0 q
0 1 0
1 0 1
1 1 -
q q* S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
x q1 q2 q1* q2* S1 R1 S2 R2
0 0 0 0 0 0 X 0 X
0 0 1 0 0 0 X 0 1
0 1 0 0 0 0 1 0 X
0 1 1 0 0 0 1 0 1
1 0 0 0 1 0 X 1 0
1 0 1 1 0 1 0 0 1
1 1 0 1 1 X 0 1 0
1 1 1 1 1 X 0 X 0
From the main truth table
qRSq* +=
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Digital Logic Design @Department of Computer Engineering KKU
J1
0
1
X
X
1
00
01
11
10
Xq1q2 0
X X
X
1
1
1
00
01
11
10
Xq1q2 0
1
X
1
1
00
01
11
10
Xq1q2 0
X
1 1
1
X
1
00
01
11
10
Xq1q2
K1 J2 K2
Design with SR Flip-flop (cont.)
21222
121
qqxR ; qxS
xR ; xqS
+==
==
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Digital Logic Design @Department of Computer Engineering KKU
Design with T Flip-flop
T q*
0 q
1
q q* T
0 0 0
0 1 1
1 0 1
1 1 0
x q1 q2 q1* q2* T1 T2
0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 0 0 1 1
1 0 0 0 1 0 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 0 0
From the main truth table
q*=Tq
q
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Digital Logic Design @Department of Computer Engineering KKU
0
1
1
1
1
00
01
11
10
Xq1q2
0
1
1 1
1
1
1
00
01
11
10
Xq1q2
Design with T Flip-flop (cont.)
21222 2111 qqxqxqxTqqxqxT +=+= +
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Design with JK Flip-flop
J K q*
0 0 q
0 1 0
1 0 1
1 1
q q* J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
x q1 q2 q1* q2* J1 K1 J2 K2
0 0 0 0 0 0 X 0 X
0 0 1 0 0 0 X X 1
0 1 0 0 0 X 1 0 X
0 1 1 0 0 X 1 X 1
1 0 0 0 1 0 X 1 X
1 0 1 1 0 1 X X 1
1 1 0 1 1 X 0 1 X
1 1 1 1 1 X 0 X 0
q
From the main truth table
qKqJq* +=
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Digital Logic Design @Department of Computer Engineering KKU
Design with JK Flip-flop (cont.)
122
121
qxK ;x J
xK ; xqJ
+==
==
J1
0
1
X X
X X
1
00
01
11
10
Xq1q2 0
X X
X X
1
1
1
00
01
11
10
Xq1q2 0
1
X X
X X
1
1
00
01
11
10
Xq1q2 0
X X
1 1
1
X X
1
00
01
11
10
Xq1q2
K1 J2 K2
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Digital Logic Design @Department of Computer Engineering KKU
Quick method for JK
*qJ
J0K1Jq*
=
=+=
*qK
K1K0Jq*
=
=+=
Because
Notice that when q=0
And when q=1
qKqJq* +=
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Digital Logic Design @Department of Computer Engineering KKU
Quick method for JK (cont.)
state table to maps
q1q2
q1*q2*
ZX = 0 X = 1
00 0 0 0 1 0
01 0 0 1 0 0
10 0 0 1 1 0
11 0 0 1 1 1 q1*
0
1
1
1
1
00
01
11
10
Xq1q2 0
1
1
1
1
00
01
11
10
Xq1q2
q2*
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Digital Logic Design @Department of Computer Engineering KKU
Quick method for JK (cont.)
Conventional q q* J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
First column
of J1 and K1
Second column of J1 and K1
J1
0
1
1
1
1
0
1
1
0
Xq1q2 0
1
x x
x x
1
00
01
11
10
Xq1q2 0
x x
x x
1
1
1
00
01
11
10
Xq1q2
K1q1*
0
0
1
1
J1
0
1
1
1
1
0
1
1
0
Xq1q2 0
1
x x
x x
1
00
01
11
10
Xq1q2 0
x x
x x
1
1
1
00
01
11
10
Xq1q2
K1q1*
0
0
1
1
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Digital Logic Design @Department of Computer Engineering KKU
Quick method for JK (cont.)Computation of J2 and K2
Conventional
J2
0
1
1
1
1
0
0
1
1
Xq1q2 0
1
x x
x x
1
1
00
01
11
10
Xq1q2 0
x x
1 1
1
x x
1
00
01
11
10
Xq1q2
K2q2*
0
1
1
0
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Quick method for JK (cont.)Computation of J1 and K1
Quick method0
1
1
1
1
0
1
1
0
Xq1q2
q1*
1
1
1
0 1 0 1
0
1
1
0
J1
Xq2Xq2
0
0
1
1
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Digital Logic Design @Department of Computer Engineering KKU
Example 1
For each of the following state tables and state
assignments, find the flip flop input equations and
the system output equation for an implementation
using
a. D flip flopb. JK flip flop
q q* z
X = 0 X = 1 X = 0 X = 1
A B C 1 1
B A B 1 0
C B A 1 0
q q1 q2
A 1 1
B 1 0
C 0 1
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Example 1 (cont.)
x q1 q2 z q*1 q*2
0 0 0 X X X
0 0 1 1 1 0
0 1 0 1 1 1
0 1 1 1 1 0
1 0 0 X X X
1 0 1 0 1 1
1 1 0 0 1 0
1 1 1 1 0 1
We will first produce the truth table.
q
C
B
A
C
B
A
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Z
0
X X
1
1 1
1
1
00
01
11
10
Xq1q2
0
X X
1 1
1
1 1
1
00
01
11
10
Xq1q2
0
X X
1
1
1
1
00
01
11
10
Xq1q2
D1 D2
Example 1 (cont.)
a. We can now map z, D1(q*1) and D2(q*2)
z = x’ + q1q2 D1 = x’ + q’1 + q’2 D2 = x’q’2 + q2
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Digital Logic Design @Department of Computer Engineering KKU
b. Using the quick method, we look at the shaded
part of the maps for J and the unshaded parts for K. (z is unchanged.)
0
X X
1
1 1
1
1
00
01
11
10
Xq1q2
0
X X
1
1
1
1
00
01
11
10
Xq1q2
J1 = 1 K1 = x q2 J2 = x’ K2 = x’
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Digital Logic Design @Department of Computer Engineering KKU
Example 2
For the state table and each of the state
assignments shown, design a system using D flip flops.
q q* z
X = 0 X = 1 X = 0 X = 1
A B C 1 0
B D A 0 0
C B C 1 1
D D A 1 0
q q1 q2
A 0 0
B 0 1
C 1 1
D 1 0
y q1 q2
A 0 0
B 1 1
C 1 0
D 0 1
a. b.
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Example 2 (cont.)
a. This assignment is in map order and once
again we will go directly to the maps without first producing a truth table.
0
1
1
1
1
1
00
01
11
10
Xq1q2
0
1 1
1 1
1
00
01
11
10
Xq1q2
0
1
1 1
1
1
00
01
11
10
Xq1q2
D1 D2 z
D1 = x’q’1q2 + x’q1q’2 + xq’1q’2 + xq1q2
D2 = q’1q’2 + q1q2 z = x’q’2 + q1q2
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Digital Logic Design @Department of Computer Engineering KKU
Example 2 (cont.)
b. For this part, we will first construct the truth table and then go to the maps.
x q1 q2 z q*1 q*2
0 0 0 1 1 1
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 1 1 0
1 1 1 0 0 0
q
A
D
C
B
A
D
C
B
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Example 2 (cont.)
0
1 1
1 1
1
00
01
11
10
Xq1q2
0
1
1
1
1
1
00
01
11
10
Xq1q2
0
1
1
1 1
1
00
01
11
10
Xq1q2
D1 D2 z
D1 = q’2 D1 = x’ z = x’ q’1 + q1q’2
We really did not need to map D1 and D2; we should be able to see those from the truth table.
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Digital Logic Design @Department of Computer Engineering KKU
Design of Synchronous
Counters
D C B A D* C* B* A*
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 x x x x
… … … … … … … …
1 1 1 1 X x x x
▪ Design a decimal or
decade counter
using JK flip-flops:
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, …
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D C B A D* C* B* A* TD TC TB TA
0 0 0 0 0 0 0 1 0 0
0 0 0 1 0 0 1 0 0 0
0 0 1 0 0 0 1 1 0 0
0 0 1 1 0 1 0 0 0 1
0 1 0 0 0 1 0 1 0 0
0 1 0 1 0 1 1 0 0 0
0 1 1 0 0 1 1 1 0 0
0 1 1 1 1 0 0 0 1 1
1 0 0 0 1 0 0 1 0 0
1 0 0 1 0 0 0 0 1 0
1 0 1 0 x x x x X X X X
… … … … … … … …
1 1 1 1 X x x x X X X X
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Design of Synchronous Counters (cont.)
D* C*
B* A*
D
1
X 1
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
1
1
1
1
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA
D
1 1
1 1
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
1 1
1 1
X 1
X
X X
X X
DDC
B
B
A
A
A
CCC
BA
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Design of Synchronous Counters (cont.)
D* JD
KDAK ;CBA J DD ==
From the main truth table of the D*
D
1
X 1
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
1
X X
X X
X X
X X
DDC
B
B
A
A
A
CCC
BA
D
X X
X X
X X
X X
X
X 1
X X
X X
DDC
B
B
A
A
A
CCC
BA
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Digital Logic Design @Department of Computer Engineering KKU
Design of Synchronous Counters (cont.)
C* JC
KC
BAKJ CC ==
From the main truth table of the C*
D
1
1
1
1
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
X
X
1 X
X
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA
D
X
X
X 1
X
X X
X X
X X
X X
DDC
B
B
A
A
A
CCC
BA
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Design of Synchronous Counters (cont.)
B* JB
KBAK ;A DJ BB ==
From the main truth table of the C*
D
1 1
1 1
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
1 1
X X
X X
X
X
X X
X X
DDC
B
B
A
A
A
CCC
BA
D
X X
X X
1 1
X X
X X
X X
X X
DDC
B
B
A
A
A
CCC
BA
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Digital Logic Design @Department of Computer Engineering KKU
Design of Synchronous Counters (cont.)
A* JA
KA
1K J AA ==
From the main truth table of the A*
D
1 1
1 1
X 1
X
X X
X X
DDC
B
B
A
A
A
CCC
BA D
1 1
X X
X X
1 1
X 1
X X
X X
X X
DDC
B
B
A
A
A
CCC
BA
D
X X
1 1
1 1
X X
X X
X 1
X X
X X
DDC
B
B
A
A
A
CCC
BA
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Digital Logic Design @Department of Computer Engineering KKU
Example: A Base-16 CounterD C B A D* C* B* A* remark
0 0 0 0 0 0 0 1 0→1
0 0 0 1 0 0 1 0 1→2
0 0 1 0 0 0 1 1 2→3
0 0 1 1 0 1 0 0 3→4
0 1 0 0 0 1 0 1 4→5
0 1 0 1 0 1 1 0 5→6
0 1 1 0 0 1 1 1 6→7
0 1 1 1 1 0 0 0 7→8
1 0 0 0 1 0 0 1 8→9
1 0 0 1 1 0 1 0 9→A
1 0 1 0 1 0 1 1 A→B
1 0 1 1 1 1 0 0 B→C
1 1 0 0 1 1 0 1 C→D
1 1 0 1 1 1 1 0 D→E
1 1 1 0 1 1 1 1 E→F
1 1 1 1 0 0 0 0 F→0
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Digital Logic Design @Department of Computer Engineering KKU
Example: A Base-16 Counter (cont.)
JD = KD = CBA JC = KC = BA
D
1
1 1
1 1
1
1 1
DDC
B
B
A
A
A
CCC
BA D
1
1
1
1
1
1
1
1
DDC
B
B
A
A
A
CCC
BA
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Digital Logic Design @Department of Computer Engineering KKU
Example: A Base-16 Counter (cont.)
JB = KB = A JA = KA = 1
D
1 1
1 1
1 1
1 1
DDC
B
B
A
A
A
CCC
BA D
1 1
1 1
1 1
1 1
DDC
B
B
A
A
A
CCC
BA
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Digital Logic Design @Department of Computer Engineering KKU
Example:
An Up/Down CounterX C B A C* B* A* remark
0 0 0 0 0 0 1 0→1
0 0 0 1 0 1 0 1→2
0 0 1 0 0 1 1 2→3
0 0 1 1 1 0 0 3→4
0 1 0 0 1 0 1 4→5
0 1 0 1 1 1 0 5→6
0 1 1 0 1 1 1 6→7
0 1 1 1 0 0 0 7→0
1 0 0 0 1 1 1 0→7
1 0 0 1 0 0 0 1→0
1 0 1 0 0 0 1 2→1
1 0 1 1 0 1 0 3→2
1 1 0 0 0 1 1 4→3
1 1 0 1 1 0 0 5→4
1 1 1 0 1 0 1 6→5
1 1 1 1 1 1 0 7→6
JA = KA = 1
JB = KB = xA + xA
JC = KC = xBA + xBA
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Example: 0, 3, 2, 4, 1, 5, 7, and repeat
q1 q2 q3 q1* q2* q3* remark
0 0 0 0 1 1 0→3
0 0 1 1 0 1 1→5
0 1 0 1 0 0 2→4
0 1 1 0 1 0 3→2
1 0 0 0 0 1 4→1
1 0 1 1 1 1 5→7
1 1 0 X X X 6→X
1 1 1 0 0 0 7→0
0
7 3
5 2
1 4 6
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Example: 0, 3, 2, 4, 1, 5, 7, and
repeat (cont.)
D1 = q’2q3 + q2q’3
D1 = q’1q’2q’3 + q’1q2q3 + q1q’2q3
D1 = q’2
D1
0
1 1
1 X
1
00
01
11
10
q1q2q3 0
1
1
1
X
1
00
01
11
10
0
1 1
1 1
X
1
00
01
11
10
D2 D3
q1q2q3q1q2q3
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Example: 0, 3, 2, 4, 1, 5, 7, and
repeat (cont.)
= + = + =
= +
= + = +
= =
= + + +
= +
= +
= + = +
= + = +
= =
1 2 3 2 3 1 2 3 2 3 1
2 3
2 1 2 3 1 2 3 2 2 3
3 2 3 2
1 1 2 3 2 3 1 2 1
1 2
1
3
2 1 3 1 3
3 2 3 2 3
1 2 3 2
2
3 1 3 2
2 1 3 1 3 2 1 3
3 2 3
S q q q q R q q q q S
q q
S q q q q q q R q q
S q R q
T q q q q q q q q q
T q q q q
T q q q q
J q q q q K q q
J q
q q
q q
q q q K q q
J q K q2
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Digital Logic Design @Department of Computer Engineering KKU
Design a synchronous counter that goes through the
sequence
2 6 1 7 5 and repeat
Using JK flip flops
Show a state diagram, indicating what happens if it initially is in one of the unused states(0,3,4) for each of the design.
Example 3
A B C A* B* C*
0 0 0 X X X
0 0 1 1 1 1
0 1 0 1 1 0
0 1 1 X X X
1 0 0 X X X
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1 1 0 1
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Digital Logic Design @Department of Computer Engineering KKU
The maps for the JK solution, with the J section shaded, and the equations are shown below.
0
X X
1
X 1
1
1
00
01
11
10
AB C
0
X X
1 1
X
1
1
00
01
11
10
AB C
0
X X
1
X 1
1
1
00
01
11
10
AB C
A* B* C*
JA = 1 KA = B’ + C’
JB = 1 KB = A JC = A KC = AB’
Substituting the values for the three states not
in the cycle :
0(000): JA = KA = 1, JB = 1, KB = 0,
JC = KC = 0 → 110
3(011): JA = 1, KA = 0, JB = 1, KB = 0,
JC = KC = 0 → 111
4(100): JA = KA = 1, JB = KB = 1,JC = KC = 1 → 011
Example 3 (cont.)
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Digital Logic Design @Department of Computer Engineering KKU
This is still a different behavior for the unused states. Now
state 4 goes to 3 and then, on the nect clock, it will get back into the cycle. The state diagram is shown below.
2
5 6
0
7 14 3
Example 3 (cont.)
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Digital Logic Design @Department of Computer Engineering KKU
Design of Asynchronous Counters
▪ Page 350….
▪ Figure 5.31(2-bit counter)&5.32(timing delay)
▪ Advantage:
❑Simplicity of the hardware no combinational
logic required
▪ Disadvantage:
❑Speed
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Digital Logic Design @Department of Computer Engineering KKU
Derivation of State tables and
State Diagrams
▪ Consider the problem:
▪ Another way of wording this same problem is
A Mealy system with one input x and one output z
such that z = 1 iff x has been 1 for three consecutive
clock times.
A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times.
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Digital Logic Design @Department of Computer Engineering KKU
▪ A sample input/output trace is
x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1
z 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0
q1*q2* z
q1 q2 x=0 x=1 x=0 x=1
0 0 0 0 0 1 0 0
0 1 1 0 1 1 0 0
1 0 0 0 0 1 0 0
1 1 1 0 1 1 0 1
◼ First approach:
save the previous
2 inputs.
◼ Knowing them
and the present
input → output.
◼ Just discard the older input stored in memory
and store the newer one plus the current input.55
Digital Logic Design @Department of Computer Engineering KKU
▪ Second approach: store in memory the
number of consecutive 1’s as follows:
❑A none, that is, the last input was 0
❑B one
❑C two or more
q* z
q x=0 x=1 x=0 x=1
A
B
C
A
A
A
B
C
C
0 0
0 0
0 1
0/0
no 1'sA
B C
0/0 0/0
1/0
1/1
1/0
one 1
two or more 1's
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Digital Logic Design @Department of Computer Engineering KKU
▪ The second approach requires only 3 states, whereas the first requires 4. Both, however, use 2 flip-flops.
▪ Consider: the system produces a 1 if the input has been 1 for 25 consecutive clock times.
▪ Now the first approach requires to store the last 24 inputs and a state table of 224
rows.
▪ The second approach requires 25 states which can be coded with 5 flip-flops.
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Digital Logic Design @Department of Computer Engineering KKU
Example 4
For each of the following problems show a state table or a
state diagram. (A sample input/output trace is shown for
each.)
A Meaaly system that produces a 1 output iff there
have been four or more consecutive 1 inputs or two or
more consecutive 0 input.
x 0 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 1z ? 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0
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Digital Logic Design @Department of Computer Engineering KKU
Example 4 (cont.)
q q* z
X = 0 X = 1 X = 0 X = 1
A A B 1 0
B A C 0 0
C A D 0 0
D A D 0 1
0/1
A D
B C
0/0
0/0
1/0
1/0
1/1
0/0 1/0
We start with a state for which the last input is 0. From there, we need
four consecutive 1’s to get a 1 output or another 0. Thus, on additional
0’s, we loop back to state A. On a 1, we go to B; on a second 1, we go
to C; and on a third 1, we go to D In D, additional 1’s produce a 1 output; 0’s return the system to state A.
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Digital Logic Design @Department of Computer Engineering KKU
Programmable Logic Devices
(PLD)
▪ Since sequential system is a combination of
memory and combinational logic, it can be
implemented using any of the programmable logic
devices of Chapter 4 (for the combinational logic)
and some flip-flops (for the memory).
▪ There are a variety of devices commercially
available that combine primarily a PAL and some D
flip-flops. There are also some very complex
programmable devices available.
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Digital Logic Design @Department of Computer Engineering KKU
Figure 6.13 One output of a 16R8 PLD.
OE'
Clock
D
Q
Q'
Out'AND array
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Digital Logic Design @Department of Computer Engineering KKU
Design using ASM diagrams
▪ ASM (algorithmic state machine) is the
same as sequential system.
▪ A tool is cross between a state diagram
and a flow chart is the ASM diagram.
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Digital Logic Design @Department of Computer Engineering KKU
B
A
X
Z
10
Figure 6.16a State box. Figure 6.16b Decision box. Figure 6.16c Mealy output box.
Figure 6.17 An ASM block.
name
output condition0 1 output
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Digital Logic Design @Department of Computer Engineering KKU
Figure 6.18 Moore state diagram and ASM diagram.
1one 1
A0
B0
C0
D1
two 1's
no 1's
three or more 1's
11
1 0 0
0
0
A
X
X
X
Z
X
1
1
1
1
0
0
0
0
B
C
D
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Digital Logic Design @Department of Computer Engineering KKU
Figure 6.19 Mealy state diagram and ASM diagram.
one 1
A
B C
two or more 1's
no 1's
0/0
0/0 0/0
1/0
1/0
1/1
10
A
X
X
X
1
1
B
C
Z
1
01
00
0
0
0
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Digital Logic Design @Department of Computer Engineering KKU
Hardware Design Languages (HDLs)
module full_adder (c_out, s, a, b, c);
input a, b, c;
wire a, b, c;
output c_out, s;
wire c_out, s;
wire w1, w2, w3;
xor x1 (w1, a, b);
xor x2 (s, w1, c);
nand n1 (w2, a, b);
nand n2 (w3, w1, c);
nand n3 (c_out, w3, w2);
endmodule
Verilog structural description of a full adder
Figure 6.20A full adder.
a
X2
X1
n 1
n 2
n 3
b
c
w 1
w 2
w 3
c_out
S
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Digital Logic Design @Department of Computer Engineering KKU
Behavioural Verilog
for the full adder
module full_adder (c_out, s, a, b c);
input a, b, c;
wire a, b, c;
output c_out, s;
reg c_out, s;
alwaysbegin
s = a^b^c;
c_out = (a&b) | (a&c_in) | (b&c_in);
end
endmodule
module full_adder (c_out, s, a, b c);
input a, b, c;
wire a, b, c;
output c_out, s;
reg c_out, s;
alwaysbegin
s = a^b^c;
{c_out, s} = a + b + c;
end
endmodule
(a) With logic equations
(b) With algebraic equations
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Digital Logic Design @Department of Computer Engineering KKU
module D_ff (q, ck, D, CLR);
input ck, D, CLR;
output q;
reg q;
always @ (negedge ck ro negedge CLR)begin
if (!CLR)
q <= 0;
else
q <= D;
end
endmodule
Structural model od a D flip flop.
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