Carrier and Timing Synchronization of BPSK via LDPC Code Feedback

Esteban L. Valles, Richard D. Wesel and John D. VillasenorElectrical Engineering Department

University of California, Los Angeles, CA 90095-1594evalles@ee.ucla.edu, wesel@ee.ucla.edu, villa@icsl.ucla.edu

Christopher R. JonesJet Propulsion LaboratoryPasadena, CA 91109-8099christop@jpl.nasa.gov

AbstractIn traditional receiver architectures, symbol acqui-sition and tracking are performed using phase lock techniquesthat are independent of the channel-code decoding process.In [1] feedback from the constraint-node side of a bi-partitegraph is used to estimate symbol frequency and timing offsetin a baseband pilotless transmission. In [2] soft informationfeedback from an LDPC decoder is used to recover carrier phaseinformation under the assumption of perfect symbol timing. Inthis paper we address the problem of joint carrier-phase andsymbol timing recovery. The proposed system is able to performwithin 0.3 [dB] of the code performance with perfect knowledgeof carrier phase and symbol timing.

I. INTRODUCTIONRecent advances in iteratively decoded channel codes such

as LDPC codes make it possible to operate at capacity-approaching SNRs. This places more stringent requirementson the timing and phase recovery portions of receivers, whichmust successfully acquire and track symbols and carrierinformation at these lower SNRs. Acquisition and trackinghave traditionally been performed independently of channeldecoding. However, the LDPC decoding process providesinformation that can be used by a timing recovery circuit toenable significantly improved performance relative to a systemwhere no such information is present.The idea of coupling LDPC decoding with timing recovery

has been explored in the past [3], [4]. Previous treatmentsin the literature addressing joint LDPC decoding and timingrecovery has focused on the use of output codewords producedas the iterations progress. By contrast, we exploit the infor-mation available from the metrics computed at the constraintnodes of an LDPC code during the decoding process. In addi-tion, we use a waveform model that more directly captures thedistortions induced by relative transmitter/receiver motion andother receiver-side timing errors. This model was introducedin [1] under the assumption of perfect carrier information.A significant research effort is underway in the area of joint

decoding and carrier phase estimation. As clearly explainedby Noels et al. [5] two somewhat distinct groups of jointdecoding and synchronization algorithms have evolved. Thefirst group approaches the parameter estimation problem by

The research in this paper was performed with the support of the Officeof Naval Research (Contract number N00014-06-1-0253), the NSF (Grantnumber CCR-0120778 and CCF-0541453), ST Microelectronics and the Stateof California through UC Discovery Grant COM 103-10142.

modifying iterative detection/decoding algorithms and thecorresponding Tanner graphs to include parameter estimation.A partial list of work on this approach includes [6][9]. Ofparticular interest has been the work of Colavolpe et al. [7]where phase-tracking processing nodes were introduced inthe iterative decoding graph. Dauwels et al. [9] also inves-tigated specially adapted message-passing update rules. Thesecond group of algorithms interchanges messages betweenan independent phase estimation block and an essentiallyunmodified iterative decoder. The resulting architectures areoften said to employ turbo synchronization. Noels et al. [5]have done a careful study of the mathematical interpretation ofturbo synchronization algorithms by means of the expectation-maximization (EM) algorithm. Algorithms of this type can canbe found in [10][13].In [6] the authors show that pilotless techniques are

more efficient at lower SNRs where the pilot insertion lossis considerable. In this work we use the pilotless turbo-synchronization technique described in [2] and present acarrier recovery circuit that is able to handle cases of imperfectsymbol timing information. The proposed technique has thepotentially attractive feature that little modification is requiredwith either the iterative decoder or the carrier and timingrecovery blocks. For carrier phase synchronization, the workleverages the fact that LDPC symbol estimates can wipe-off modulated symbols in a decision directed carrier recoveryloop to enhance the carrier information such that a classicresidual carrier phased-lock loop (PLL) is able to provideincreasingly accurate phase estimates over LDPC iterations.The proposed method incurs a latency penalty (by way ofincreased iterations) as carrier phase and timing information isacquired. However, complexity in terms of system descriptionand area (in the case of a real-time implementation) remainssimilar to that of state of the art residual carrier and timingrecovery techniques currently used in NASAs deep-spacenetwork.The rest of this paper is organized as follows. The next

section provides a detailed description of the transmitter andreceiver models and gives an overview of the joint parameterestimation process. In Section III, the circuit for symboltiming estimation is introduced. A digital implementation ofthe carrier synchronization circuit is illustrated in Section IV.Section V presents numerical results derived from a simulationof the BPSK scheme with a particular LDPC code. Finally,

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Section VI documents our conclusions.

II. TRANSMITTER AND RECEIVER MODELSOn the transmitter side, we consider a baseband signal com-

prised of N root raised-cosine pulses hRRC(t), transmittedat multiples of a symbol interval T and scaled di {1}:m(t) =

N1i=0

dihRRC (t iT .). Multiplication by a sinusoidalcarrier signal yields the transmitted waveform:

yTx(t) =

2Pm(t). sin (wct) , (1)

where P is the signal power.When symbol timing errors are present, the assumed time

reference for the kth sample at the receiver r[k] differs fromthe corresponding time reference at the transmitter r[k] =m(kTs + [k]). The timing error modalities considered inthis work combine constant time offsets ( [k] = D), randomwalks ( [k] = [k1]+N (0, 2d)Ts) and constant frequencyoffsets ( [k] = [k1]+ FPPM

106Ts) where Ts is the sampling

period and the frequency offset FPPM is measured in partsper million. The received waveform can be modeled as:

yRx(t) =

2Pr(t). sin (wct + c) + n(t) (2)

where

r(t) =N1i=0

dihRRC (t + (t) iT ),n(t) =

2 [Nc(t).cos(wct + c)Ns(t).sin(wct + c)] ,

c is the carrier phase and n(t) is a bandpass AWGN process.

Carrier Freq.% Sat.

Constrants

Update SymbolEstimates

Update ChannelObservations

( )Rxy t

cw

Sampling &Interpolation

cX

CarrierPhaseEstimation

c

Sampling &Interpolation

sX

cZ

sZ

LDPCDecoder

SymbolTiming

Convert toBaseband &

Filter

Convert toBaseband &

Filter

(a)

( )cosck cw =

DetectedData

Symb.Timing( ; )s cx t

Symb.Timing

( ; )c cx t

( , )Rx cy t

LDPCDecoder

NCO ACC

( )sinsk cw =[ ]e k

Quadrant

1

1

c

c

90

[ ][ ] [ ] n ky k d kA

= +

[ ]sz k

[ ]cz k [ ]cu k

[ ]su k

% Satisfied Constraints

(b)

Fig. 1. (a) Receiver block diagram. (b) Digital implementation for BPSK.

A block diagram of the decoding circuit along with the BPSKdigital implementation are shown in Fig.1. The input signal

yRx(t) is converted to baseband and low-pass filtered toremove frequencies at 2wc which yields:

xs(t) =

Pr(t)sin(c) + Nc(t)cos(c)Ns(t)sin(c)xc(t) =

Pr(t)cos(c)Nc(t)sin(c)Ns(t)cos(c)

(3)The In-phase/Quadrature (I&Q) signal components in (3)

are then sampled and matched filtered resulting in two digitalsignals:

zs[k] =PTsd[k]sin(c) + Nc[k]cos(c)Ns[k]sin(c)

zc[k] =

PTsd[k]cos(c)Nc[k]sin(c)Ns[k]cos(c)in the interval kTs t (k + 1)Ts.The symbol timing recovery process described in Section

III is now initialized. After the symbol-timing block correctstime delays, random walks and sampling frequency errors,parameter information is interchanged in an iterative fashionwith the carrier synchronization block described in SectionIV to complete the iterative parameter estimation process.

III. SYMBOL TIMING RECOVERY

In Fig. 2 we illustrate the receiver architecture whichexploits feedback from the LDPC decoder to manage symboltiming errors. The received waveform is initially sampled atintervals of Ts and stored into a buffer. The interpolator com-putes interpolants at intervals of Ti using linear interpolation,which are then used for the matched filtering process [14]. Inthis work, we use Ti = T /2 and Ts = T /4, where T is thereceiver-side assumption of the transmitter symbol period T(i.e. the symbol period that would be seen by the receiver inthe absence of any timing perturbations).The timing recovery circuit from Fig. 2 consists of two

loops. Loop 1 is first executed to iteratively recover constanttime phase and symbol-frequency offsets. The phase errorestimator provides the interpolator (after the matched filter)with a time offset, which is used to correct the constant timedelay. The symbol-frequency estimator provides a frequencycontrol word which is resampled at a rate of 1/Ts and fed tothe numerically controlled oscillator (NCO).Both the constant time delays and sampling frequency

offset estimation processes use information from the iterativechannel decoder based on the percentage of satisfied LDPCconstraints. The utility of this metric as a feedback mechanismis illustrated for the case of symbol-frequency offsets in Fig. 3,which shows the average percentage of satisfied constraints asa function of frequency estimation error for different SNRs(Eb/N0) and numbers of LDPC iterations. A similar plot,with similar tradeoffs, can be constructed for the relationshipbetween the constant time delay estimation error and satisfiedLDPC constraints.In [1] phase and symbol-frequency estimates are generated

in an iterative fashion using a window search method. Aninitial window and step size are chosen and a fixed numberof LDPC iterations are performed at each hypothesis point.For example, in order to estimate a symbol-frequency offsetof 2000 ppm (i.e. 0.2%) an initial step size of 400 ppm is

2178

0r(t)

Interpolator 1

Signal Sampling Clock(1/Ts)

x[k]Matched

Filter

y[j] z[i]

LDPC Decoder

DecodedSymbols

d[i](1/T)

ComputeFractional

Interval

[j]

[j]

NCO Resample

Overflows(1/Ti)

w[k]

SatisfiedConstraints

(1/Nc)

v[i]

q[j]

Buffer

Timing ErrorDetector

u[i]

LoopFilter

1

sel

Buffer

s[i]

c[i]Frequency Estimator

Time Delay Estimator

p[h](1/N)

Interpolator 2

Interpolator 3

Loop 1: Time Delay & Frequency Offset CorrectionLoop 2: Random Walk & Residue Error Correction

c

CarrierPhaseEstimation

Fig. 2. Generic Symbol Timing block. Signals indexed with i, j, and k are at rate 1/T , 1/Ti, and 1/Ts respectively

800 600 400 200 0 200 400 600 800

65

70

75

80

85

90

95

100

Frequency Estimation Error [ppm]

Satis

fied

Cons

train

ts [%

]

1dB, LDPC It=21dB, LDPC It=41dB, LDPC It=62dB, LDPC It=22dB, LDPC It=42dB, LDPC It=6

Fig. 3. Percentage of satisfied constraints as a function of frequencyestimation error. Curves for 2, 4, and 6 LDPC iterations are shown for Eb/N0of 1 and 2 dB.

used with three decoder iterations for each offset hypothesis.The window is then re-centered to the point with the highestnumber of satisfied constraints and the step size is reduced byhalf. The process is repeated a third time with a resolution of100 ppm. For this example, the method in [1] utilizes a total of11[points] 3[windows] 3[Iter. per point] = 99[Iterations]to correct an offset of 2000 ppm. In this work, in orderto correct the same sampling frequency offset, a fixed stepsize of 250 ppm, with 3 LDPC iterations per point, wasused. Instead of re-computing the window center and size, aninterpolation technique generates the final frequency estimatebased on the points with the highest percentage of satisfiedconstraints. This allows a reduction of the total number ofiterations (17[points] 3[Iter. per point] = 51[Iterations])without a significant performance degradation. As long asthe frequency offset is contained within the initial searchwindow, the algorithm will converge with an accuracy thatincreases with increasing SNR. The complexity of this methodgrows linearly with the width of the range of frequencyoffsets contained in the initial search window. It is possibleto track waveforms where both time delays and symbol-frequency offsets are present by means of a two-dimensionalsearch strategy. For the purposes of this paper, when a timedelay is imposed we assume it is limited to 0.5T . This iseffectively the same as assuming that some other mechanismhas provided frame synchronization.After large-scale phase and frequency errors have been

identified in loop 1, loop 2 is used to handle random walks,

correct residual time delay and sampling frequency errors,and to perform the remaining LDPC decoding. A conventionalfirst-order PLL-based circuit with a decision-directed Mueller-Muller timing error detector (M&M TED) [15] is used in loop2. After every LDPC iteration, the M&M TED is providedwith the symbols decoded by the LDPC decoder, analogousto the approach of Barry et al. [3].At this point, an updated version of the signals zc and zs

is sent to the carrier-phase recovery loop to produce a newestimate c. As shown in Fig. 1(a), this information is then fedto the LDPC decoder to continue with the iterative parameterrecovery process. From this point forward, every update fromthe carrier-phase estimation loop is followed by an updatefrom loop 2 in the symbol-timing circuit in an iterativefashion.

IV. CARRIER PHASE SYNCHRONIZATIONThe carrier recovery circuit for BPSK modulation used

in this work is the decision-directed carrier synchronization(DDCS) circuit originally proposed in [2]. This circuit con-verts the received modulated carrier to an unmodulated carrier(pure tone) before applying it to a phase-tracking loop. Thisis done by multiplying zc[k] and zs[k] by the normalizedsoft decision feedback sample y[k] = d[k] + n[k]/A, whereas before over a given iteration n[k] are modeled as i.i.d.zero mean Gaussian RVs with variance 2. The result of thismultiplication removes the modulation and produces:

us[k] = zs[k]y[k] =PTssin(c)

+[(d[k] + n[k]/A)(Nc[k]cos(c)Ns[k]sin(c))+n[k]/A

PTsd[k].sin(c)] =

PTssin(c) + vs[k],

uc[k] = zc[k]y[k] =PTscos(c)

+[(d[k] + n[k]/A)(Nc[k]sin(c)Ns[k]cos(c))+n[k]/A

PTsd[k].cos(c)] =

PTscos(c) + vc[k],

which is then input to a second order digital PLL whoseNCO produces an estimate of the carrier phase denoted byc[k]. Multiplying uc[k] and us[k] by ws[k] = sin(c[k]) andwc[k] = cos(c[k]), respectively, and then differencing theresults of these products provides the error signal:

e[k] = us[k]wc[k] uc[k]ws[k]=PTs.sin(c[k]) + vs[k]cos(c[k]) vc[k]sin(c[k])

where as before c[k] = c[k] c[k] denotes the phase errorin the loop.

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The performance of carrier-phase synchronization loopsis commonly expressed as a function of the loop SNR(LSNR). For a PLL based system, this can be expressed as:

LPLLSNR =1

2c= PLL =

PcNoBL

(4)

where Pc is the carrier power, No is the noise PSD and BLis the loop bandwidth [16].The degradation of LSNR performance in the case of BPSK

is represented by a quantity called the squaring loss, whichis a measure of the degradation of the receiver signal-to-noise(SNR) ratio and is associated with the mean-squared phaseerror of the loop. At low symbol SNR, the squaring loss ofan I&Q loop, such as the Costas loop, can be severe enoughto prevent tracking:

LCostasSNR =1

2c= C .SLC =

PtNoBL

(1 +

1

2Rd

)1

(5)

where Pt is the total transmitted power, No is the noise PSD,BL is the loop bandwidth and Rd is data SNR at the inputof the receiver. Note that (5) is independent of the iterationprocess.If the data sequence and its timing parameters were com-

pletely known, then a BPSK signal could be converted to apure tone simply by multiplying the BPSK signal by the datawaveform. One could then track the unmodulated carrier withimproved performance by use of a PLL, which from (4) wesee that it does not exhibit squaring loss. Short of completeknowledge of the data waveform and in the presence of noise,the best approximation of a pure tone could be obtained byfeeding back an estimate of the data waveform correspondingto tentative decisions on the data symbols.Although initially available data-waveform estimates (y[k])

are generally of low quality, they can be used to initiate thecarrier synchronization process by reducing the number ofdata transitions at the input. Once phase lock is achieved, theimproved phase estimates can be fed back to the data detector,yielding improved symbol estimates for feedback, and therebyachieving even better phase tracking. This iterative processeventually leads to virtual elimination of squaring loss, sothat the performance of the system approaches that of a phase-locked loop operating on an unmodulated carrier signal. Forthe proposed system we have that:

LDDCSSNR =PT

NoBL

(1 +

2

A2

)1

(6)

where A2/2 represents the decoder soft-estimate of the dataSNR.We can see from (6) that as the iteration proceeds, theestimated data SNR increases and likewise the squaring lossdecreases. By comparison, for a Costas loop, the expressionfor the squaring loss in (5) remains fixed, independent of theiteration process, for a given symbol SNR.Another important difference between these two circuits

is that unlike the Costas loop, the DDCS circuit operates

0 5 10 15 20 25 30 35 40 45 505

10

15

20

25

30

35

Loop

SNR[

dB]

Iterations

DDCS 1.00dBDDCS 1.50dBDDCS 2.00dBCS 1.00dBCS 1.50dBCS 2.00dB

Fig. 4. Loop SNR performance.

at baseband. This greatly simplifies the circuit complexitysince high-frequency processing of the received signal is notrequired. Fig. 4 compares the LSNR performance for bothloops under the assumption of perfect symbol information [2],using a rate-1/2 irregular LDPC code of length n = 1944. Anintegrator was added to the output of the traditional Costascircuit to reduce the jitter in the phase estimates. For theDDCS system channel observations are updated on everyiteration. On the other hand, the Costas loop is independentof the decoders decisions. This implies that for the Costascase, the horizontal axis of Fig. 4 in fact represents thenumber of times that each block (of size n) is processed bythe loop. For the DDCS circuit, steady state is reached after10 iterations (10 1944 = 19440 total symbols processed).The Costas loop converged to its steady state operation afteroverprocessing each block of 1944 symbols approximately 20times (for 38880 total symbol observations). The speed ofconvergence is highly dependent of the gains of the loop-filter shown in Fig. 1(b). A second order filter with transferfunction H(z) = (Kp +Kiz1)/(1z1) was used for bothcircuits with gains [Kp,Ki] = [8.85.104,8.75.104] forthe Costas loop and [Kp,Ki] = [8.92.105,8.75.105] forthe DDCS circuit.

V. NUMERICAL RESULTSWe have evaluated the performance of the all-digital BPSK

approach, assuming perfect knowledge of the carrier fre-quency and simulating the signals in (3). Joint parameter es-timation and decoding was performed using a rate-1/2 (1944,972) irregular LDPC code developed in [17] and currentlyin the IEEE 802.11n standard. After a complex rotation toresolve phase ambiguity (discussed below), the signals zc andzs are multiplied by the decoder output y to form uc and us.As described in previous sections and shown in [2], if thePLL input has a small fraction of total modulated symbols ina block successfully removed, then it can begin to producea reasonable phase estimate, even at relatively low SNRs.We have found that the estimation/decoding process can besuccessfully started by assigning y to the signal zc or zswith the highest energy (Subsequent iterations derive y fromthe decoder). After this assignment, the PLL in the carriersynchronization loop operates once across all symbols in a

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codeword. LDPC decoder log-likelihood ratio inputs are thenproduced by combining the updated PLL phase estimates withzc and zs:Q[k] = 2

2llr

(zs[k]wc[k] + zc[k]ws[k])

= 22

llr

(PTsd[k]cos(c)Nc[k]sin(c)Ns[k]cos(c)

)

where 2llr = PT 2s /(2Es/No).In order to remove residual timing errors, loop 2 from the

symbol timing circuit in Fig.2 is updated after a new carrier-phase estimate has been generated.We conclude this section by noting that phase ambiguity

(for offsets greater than /2 can be resolved by firstmeasuring the average power across a single codeblock ofthe signals zc and zs. If the sine component (zs) has averagepower greater than the cosine component (zc), then thesetwo components are swapped. This procedure may leave(or induce) a remaining error of radians. To resolve thisambiguity we run a single PLL pass followed by several(up to 4) LDPC iterations. The orientation that produces themaximum number of satisfied odd-degree check equations isselected and the decoding procedure is reinitialized 1. Similartechniques are proposed in [10], [11].Results in Fig.5 for a carrier phase offset = = /4, a

symbol-frequency offset of2000ppm, a time delay of 0.5Tand a random walk of d/T = 0.5% shows a degradationsmaller than 0.3 dB from the code performance where carrierphase and symbol timing are known perfectly.

0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8104

103

102

101

100

Eb/No(a)

FER

0.8 0.9 1 1.1 1.2 1.3 1.4 1.50

0.1

0.2

0.3

0.4

FER

GA

P [d

B]

Eb/No(b)

Genie

[Carr.TD.Fr.Rw]

[Carr.Rw]

[Carr.Freq.]

[Carr.TD.]

Fig. 5. (a) FER 50 Iterations(solid) / FER 20 Iterations(dashed) performance.Legend format [Carr.] indicates the presence of a = /4 carrier phase off-set, (Freq.)Symbol-frequency offset, (TD)Time delay, (Rw.)Randomwalk. (b) Shows the SNR gap with respect to the genie-aided performancefor the same set of curves.

VI. CONCLUSIONWe have demonstrated a means for improving the sym-

bol timing and carrier-phase estimation for iterative decoded1Even degree checks remain satisfied under a rotation of all inputs by .

BPSK using information derived from an LDPC decoder.For carrier synchronization, the signal modulation is removedprior to the carrier tracking operation. The motivation fordoing this is to overcome the penalty in noisy reference lossattributed to the large squaring loss at low SNRs that ischaracteristic of the traditional BPSK carrier sync loops suchas the Costas-type loop. The scheme described in this papermakes use of soft-decision information and does not requireestimating the decoder error probability. A pilotless symboltiming recovery architecture for tracking time delay, frequencyoffsets and random walks using LDPC feedback was alsopresented. The complexity of this window search methodsiginificantly reduces the number of iterations needed in [1].Performance within 0.3 dB of the genie-aided performancecan be achieved for large time delays, frequency timing offsetsand any carrier phase offset.

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