Atomic Layer Deposition in
Semiconductor Manufacturing
Juan Pablo Trelles
Design and Technology Solutions, Intel Corporation
Washington State University, Vancouver, WA
November 7, 2011
1
Outline
1. Overview of Semiconductor Manufacturing
– Semiconductor industry and work @ Intel
2. Introduction to Atomic Layer Deposition
– Chemistry, process
3. Industrial ALD Processes
– How to make ALD feasible in industry
– Role of Computational Modeling & Simulation
2
1. Overview of Semiconductor
Manufacturing
3
About Intel
• Semiconductor Manufacturing Silicon, Software, Solutions
– Deliver the “Computing Continuum”
• +90 000 employees worldwide
4
• R & D facilities in Hillsboro, OR
• 2 Fabs in OR + 1 new (D1X) in 2012
> 2 Billion $
http://download.intel.com/newsroom/kits/22nm/pdfs/Global-Intel-Manufacturing_FactSheet.pdf
D1C
D1D
D1X
(latest)
(new)
Integrated Circuits
Integrated circuit ~ electric - logical unit
• Circuit design: logic equations transistors
• Layout: circuit schematics layers to be fabricated
5
C = A & B
• Chip ~ 3.5 Billion transistors (contrast: world population 7.0 Billion)
Core i7
(4 cores)
logic circuit layout
http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm
core
shared L3 cache
controller
Semiconductor Manufacturing
6http://www.intel.com/pressroom/kits/chipmaking/
sand melted Si monocrystal
ingot
ingot slicing wafer
ion
implantationapply high-k
dielectric
apply
photoresist
exposure exposure
(transis. level)
wash-off
photoresist
etching
remove
photoresistready
transistorelectroplatingpolishing
metal layers
sort test
slicing &
selection
single die
3 main types of processes:
– Deposition of material (CVD, PVD, ALD, EP)
– Removal of material (wet etch, dry etch, CMP)
– Modification of material (litho, implant, annealing)
Moore’s Law
7
http://www.intel.com/pressroom/kits/events/moores_law_40th
Gordon Moore, Co-founder,
Intel Corporation
• Compared to Intel’s first microprocessor, latest microprocessors …
• Run +4000X faster
• Each transistor uses +5000X less energy
• Price per transistor dropped by +50 000X
• “The number of transistors on a chip doubles about every two years”
– Driven by High Volume Manufacturing + Economics
– Drives Semiconductor Research roadmap
206 2101971 chip / trans.#
2011 chip / trans.#
Technology Development @ Intel
8
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
transistor
chip cross
section
chip top
view
interconnects
transistors
http://en.wikipedia.org/wiki/File:
Red_White_Blood_cells.jpg
red blood cell
~ 300 transistors
• A New Technology introduced every 2 years (Tic – Toc)
Technology Development @ Intel (cont.)
9
ALD technology enabler ALD intrinsic in process development
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
• New Technology often involve revolutionary innovations …
2013 2015
14 nm 10 nm
? ??
2. Introduction to Atomic Layer
Deposition
10
Atomic Layer Deposition (ALD)
11
Thin Film deposition process characterized by:
1. Complementary and Self-limiting surface reactions
2. Monolayer thickness control
3. ALD processes often involve cyclic exposures and purges of reactants
Tanaka and Takagi, ECT Trans, 2011
~ 1 atom thickness
Example: GeO2 over crystalline Ge for MOSFETs
Examples & Uses of ALD
12
R. Gordon, Atomic Layer Deposition (ALD): An Enabler
for Nanoscience and Nanotechnology, Harvard University
Applications:
• Lubrication of moving parts
• Optical coatings (reflective, anti‐reflective, absorbers)
• Corrosion protection
• Increased hardness of the mechanical layer
• Tuning of mechanical properties (i.e., stiffness)
• Charge dissipation
• Hydrophobic surface or uniform nucleation layers
• Protective layers for biocompatible coating of MEMS
• Controlled gap filling, closing on nano‐scale pores
• Hermetic coatings
• Growth of sacrificial layers for small gaps
Industries:
• Semiconductors
• Micro-Electro-Mechanical Systems (MEMS)
• Nano-Electro-Mechanical Systems (NEMS)
• Displays and OLED Lighting Technologies
• Flexible electronics
• Textiles
A. Londergan (Qualcomm), New Opportunities for ALD in MEMS,
NEMS, Displays and OLED Lighting Technologies, Workshop, Atomic
Layer Deposition, Cambridge, MA, 2011
lining & filling
nanopores
nanotube
coating
photonic
crystals
coating of
nano-particles
Gas Chemistry Kinetics
• Elementary reaction:
13
BAkR Rdt
Dd
dt
Cd
dt
Bd
dt
Ad
][][][][
• Example: Hydrogen Bromide synthesis
)(2)()( 22 gHBrgBrgHk
Br
Br
H
H
Br
H
H
Br
+
Reaction rate:([ ] = molar concentration)
DCBAk
DCBA
k
molecules
of mole 1 ithtogether w
molecules
of mole 1
molecules
of mole 1 withcollides""
molecules
of mole 1 y probabilit withproduces
Surface Chemistry Kinetics
14
• Similar to Gas kinetics, BUT surface as reactant
• Ex: Silicon deposition from Silane
)(2)()()()( 24 gHsSibSisSigSiH
• Film growth occurs by repetitive insertion of bulk species; types:
a) two-dimensional
b) island
c) random
1. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
(g): gas
(s): surface
(b): bulk
Si Si Si Si SiSi
Si
H H
HH
Si
…
H
HH
H
+surface
bulk
)()()()()(
)()()( )()(
2
1
bAgCsBsAgB
bBgCsAsBgA
k
k
precursors surface termination bi-products film
ALD Chemistry
15
inject A insert B
inject B insert A
time
B(b) in A(b) inbi-prod out
bulk
AB film
bi-prod out
+ D(g), dilutant always present
• “Complementary Self-Limiting Surface Reactions”
• “Canonical” ideal ALD of A-B film
(g): gas, (s): surface, (b): bulk
Ideal 2-step ALD chemistry is rarely
(if ever) found
productsproduct-bi gaseouson terminatisurface teintermediaprecursors
223
224
)()(2)(2)()(2
)()(2)( )()(
bTigHClsNHsTiClgNH
bNgHClsTiClsNHgTiCl
Example: ALD of TiN
16
• TiN deposition from TiCl4 and NH3
N deposition
Ti deposition
N deposition Ti deposition
H. Kim, J. Vac. Sci. Technol. B
21„(6), Nov/Dec 2003
Elements in ALD
17
R. Gordon, Introduction to the Chemistry of ALD, Atomic Layer Deposition, Cambridge, MA, 2011 based on data in R. Puurunen,
J. Appl. Phys. 97, 121301 (2005)
Combination of
elements in ALD films
Elements used in
ALD films
~ most elements BUT often: high T,
undesired bi-prods, expensive,
…
ALD Process
181. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
Typical type showerhead reactor
wafer
exhaustFlow pathB. Devulapalli, Deposition: One Layer at a
Time, Report, Fluent (2003)
“Cyclic exposure and removal of reactants over the substrate”
• Example 2-reactans, 4-stages cycle:
1. Flow reactant A over substrate for time t1
2. Evacuate reactant A for time t2
3. Flow reactant B over substrate, time t3
4. Evacuate reactant B, time t4
A(s)
B(s)
Molecular Dynamics Simulation of ALD
19
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
HfO2 from HfCl4 + H2O on oxidised Si substrate
Initial SiO2 surface
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
20
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Reaction with HfCl4
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
21
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Rearrange of HfCl4 –terminated surface
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
22
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Reaction with H2O
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
23
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Rearrangement of H2O–terminated surface
One full cycle is completed repeat
3. Industrial ALD Processes
24
Chemistry Process Film
25
(Input)
(Output)
Ideal Chemistry ≠ Ideal Process- stage duration = complete surface termination- no mixing, desorption, gas-phase reactions, etc
A(g)injection
B(g)injection
A(g)purge
B(g)purge
time
Q
gas flow
t1 t2 t3 t4
recipe
(4 stages)
Real
AxBy film
t1 t2 t3 t4time
deposition
rate
Ideal
y x
B(b).
A(b).
ALD @ Intel
26
• Since High-k Metal Gate ALD technology enabler
• ALD for High-Volume Manufacturing (HVM)o cost (precursors, equipment, throughput)
o control, reliability, yield, …
1st gen high-k metal gate
2nd gen high-k metal gate
3-D tri-gate transistors
Intel Technology Journal, ISSN 1535-864X
DOI 10.1535/itj.1202.01
M. Bohr, Silicon Technology for 32 nm and
Beyond System-on-Chip Products, IDF 2009
How to Increase Process Throughput?
27
• Process conditions:
• Pressure limited to avoid gas phase reactions, particles
• Temperature limited by substrate, may have complex effect
• Reactivity:
• Catalysts hard to find, could lead to undesired reactions
• Plasma-enhancement complex, may lead to non-conformal growth
• Equipment:
• More substrates advance reactor design
• Faster recipe optimization
1. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
All above used in HVM; Equipment most advantage
exhaust
Qin
wafer stack
Qout
Example: ALD Reactor for HVM
• Multi-substrate batch reactor: 1 inlet (injector), 1 outlet (exhaust), 4 wafers
28
injector
Qin
Flow effects limit ideal ALD
dissimilar flow
resistance
non-uniform injection
recirculation
stagnation
Patterned Surfaces & ALD Chemistry
• ALD in semiconductor technology: (geometric) Multi-Scale
29
• Patterned topography increases substrate areao Process from “diffusion limited” to “reaction limited”
• Film evolution at the feature-scale:
Intel Press Release, Intel First to
Demonstrate Working 45nm Chips, 2006
~ 10 cm
~ 1 cm ~ 1 um
wafer die pattern feature
~ 10s nm
Profiles of obtained film after each ALD cycle using detailed
10-step chemistry
ALD film
Deposition Process Example
Conditions:
• Ideal A-B chemistry
• k1 = k2
• rQin const.
• 100% B(s) initial surf. term.
• D(g) pressure loading
• P ~ Torr (Kn << 1)
30
B(b) depositionB(s) consumptionA(g) transport +
A(g)
Qin
A(g) 1
2
3
4
5
6
7
Precursor Transport
31
A(g)
2 73 5 64
stagnant precursor residual deposition
non-uniform injection different deposition
Stagnation & Recirculation
32
Fluid Flow effects limit applicability of “estimates” in recipe formulation
1 2
recirculation inside injector:non-uniform injection, mixing
1A(g)
stagnant bi-products:reduce available Pv
1
2
C(g)
C(g)
dragging of stagnant gas: mixing, non-ALD growth
2B(g)
A(g)
During research (i.e., no industrial) ALD, these peaks are > 5X apart below problems not found
ALD Recipe
33
CaseTime
Total Cycle
Time
Purge/Total
Growth
rate
Max
A(s)
I 50% T 1/2 59% 65%
II 50% T 2/3 63% 67%
III 75% T 2/3 93% 99%
IV 100% T 2/3 100% 100% complete
~ optimal
non-ALD
non-ALD
ALD
non-ALD
A(s) fractional coverage • inj. time growth rate• purge time ALD• purge time > 2/3 cycle• “optimal” recipe limited by flow effects
• optimal:+25% shorter cycle-7% growth rate
Summary
• Semiconductor Manufacturing
– Industry roadmap driven by Moore’s Law
– Economics of High Volume Manufacturing (HVM)
– Latest node @ Intel: 22 nm, 3D transistors, > 1 Billion transistors / chip
• Atomic Layer Deposition (ALD)
– Atomic-layer control of Thin Film deposition processes
– Complementary & self-terminating surface reactions
• ALD for HVM challenges: Throughput– Fluid Flow effects: recirculation, stagnation, dissimilar transport, etc.
– Increasing process throughput limits “ideal ALD”
– Most cycle time spent in “purges” (i.e., no chemistry) … room for improvement?
34
Notes
• Information about Semiconductor Manufacturing and Intel
– www.intel.com About Intel Silicon Innovations
– http://www.intel.com/content/www/us/en/silicon-innovations/silicon-innovations-
technology.html
• Review papers on ALD
– H. Kim, H.-B.-R. Lee, W.-J. Maeng, Applications of atomic layer deposition to
nanofabrication and emerging nanodevices, Thin Solid Films 517 (2009) 2563–2580
– O. Sneh, R. B. Clark-Phelps, A. R. Londergan, J. Winkler, T. E. Seidel, Thin film atomic
layer deposition equipment for semiconductor processing, Thin Solid Films 402 (2002)
248–261
• Intel is doubling number of internships for 2012
– More information and online application:
– http://www.intel.com/jobs/usa/students/internships/
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