Hot Chips 2007ASICs to ASSPs for Working Engineers
Building the OMAP 3430
David Witt
Texas Instruments
1G
AnalogCellular
Voice
AMPS, TACS
2G
DigitalCellular
Voice
Pager
10kbps data
GSM, TDMA
CDMAOne
3G
Wide-BandDigitalCellular
Video
M-pixel cam.
3D
300kbps
14Mbps
UMTS,HSDPA
CDMA 1XEVDO
2.5G/
2.75G
Voice
Photos
Web
~100kbpsdata
GPRS/EDGE
CDMA 2000 1X
4G
Wide-BandNetwork
Ubiquitousdata
FlexibleSpectrum use
Enhancedapps.
100Mbps –1Gbps
OFDM
Today
BOILER PLATE – Framing the Problem -
DigitalCellular
3.9G/
OFDM
Wide-BandDigitalCellular
Video
High-endgaming
100 Mbps,10msec
Flexiblebandwidth
All IP Network
Super 3G/LTE
OFDM (MIMO)
WiBro/WiMAX
Ch. BW Data Rate
2G 1X 1X
3G 25X 100X
4G 100X 1000X
~50X
~8X
Modern CMOS10 m
1 m
100 nm
10 nm
1 nm1970 1980 1990 2000 2010 2020
35 Yearsof Scaling History
Every generationFeature size shrinks by 70%Transistor density doublesWafer cost increases by 20%Chip cost comes down by 40%
BOILER PLATE – Process Migration
90 nm in 2004
Generations occur regularlyOn average every 2.9 yearsover the past 35 yearsRecently every 2 years
65 nm in 2006
Presumed Limitto Scaling?
Deep UV Litho
Beginning ofSubmicron CMOS
1995: ~20M 2G handsets
2005: ~45M 3G handsets
10 years, 5 lithography nodes
~32X transistor density
~ close to 50X complexity
45 nm in 2008
Memory Iddq vs. Power Management
1
10
100
1000
10000
180nm 130nm 90nm 65nm 45nm
Without PM
With PM
Idd
q
no
rm.
0
100
200
300
400
500
600
700
1993 1995 1997 1999 2001 2003 2005 2007
MCU
MIPS Phone Performance Requirement
Productavailable
Technology Node
Technology: memory Iddq
1
10
100
1000
10000
180nm 130nm 90nm 65nm 45nm
Idd
q
no
rm.
Without PM
Talk Time: Pwr_Active = CV2F + Leakage
- C: Decrease/node,offset by complexity
- F: Increases/node
- Leakage: Increases/node, temp.
Standby Time: Pwr_Idle = Leakage
- Leakage: Increases/node, temp
BOILER PLATE – Advanced Process and Leakage – and a Phone
BOILER PLATE – We are not just digital guys anymore
Multiple
SRAMsDSP
Digital
Base
Band
JTAG/P1500/Bist => DfT Multiple DPLLs
ADCTouch Screen
Auto Frequency + Pwr Ctrl DACs
BatteryDisplay
DRAM
Flash keypad
DC-DC Reg.
(eSMPS)
Video
DAC+
Buffer
USB 2.0
OTG
USB2.0 TV
PM
20V Battery
Charger
Fuel Gauge
White LED Dr.Audio CODEC
Class DMany eLDOs
Tx: I&Q DACs
3V I/O
SD-Mem
+ SIM
Cards
SmartReflex
eLDOs
SIP
ARM
SmartReflex SmartReflex
eLDOs
Temp Sensor
Dig Rf
Serial i/f
RF
Chip
Rx: I&Q ADCs
Memory i/f User i/f Battery i/f
MIPI
PHY
eLDOs
ADCs BB AmpDRPxx
BandGap
RF
i/f
OMAP 3430 – or something similar –
Security Firewall
32-bit
shared
linkcrossbar
USB
(OCP -1.0)
USB
HS
SSI
sDMA CAMLCD
IVA-2
Target
2D/3D
Target
L3 Subsystem
IVA-2
2D/3D
engine
ARM-MPU
GPMCOCMC
ROM
OCMC
RAM
SMS
SDRC
32/1
64/3
32/1
32/2
32/4
32/1
32/1
32/1
32/1
64/8
32/1
32/1
32/1
64/5
64/9
64/1
L4-Core
Peripheral
Interconnect
32/1
L4-Per
Peripheral
Interconnect
32/2
DAP
32/1
D2D
32/1
L4-EMU
Peripheral
Interconnect
32/4
L4-WU
Peripheral
Interconnect
TI async
bridge
TI async
bridge
TI async
bridge
TI async
bridge
(OCP -1.0)
(OCP -1.0)
(OCP -1.0) (OCP -1.0)
(OCP -1.0)
TI
isolation
TI
isolation
TI
isolation
Sonics
isolation
Sonics
isolation
Sonics
async
bridge
Targets
Targets Targets
Targets
RT
Walk thru the past in building ASIC “complex things”
� What killed us in the past??
– Predicting performance – and trends in applications
– Verification – many IPs / many teams
– Hookup errors – 100 IPs 10K to 100K signals
– Arch /spec – what is it you really wanted
– Standards for power/security
– Timing closure – guidelines/predictability
– Process – advanced/models/stability
– Analog/ESD and the integration of same
OMAP/application modeling – ASIC 101..
� Level set architecture before “aircraft carrier gets going”
� System C based models
– Processors
– Accelerators
– Caches
– On chip interconnect
� Enough insight to predict direction
� About 1.5 year MAX – prediction to tape
� We must understand and close in this time or die..
� We think things are IP – or SOC – not both ..
What was new in the OMAP 3430 and why??
� Cortex A8 – CPU– ARM v7 ISA
– 2 issue very high clock/low power
– NEON dsp/ float extensions..
– First to deploy..
� Programmable DSP accelerators..– Audio/video/imaging
– Flexibility/high performance
� New 3G graphics core– Open GLS2.0
� Camera high speed interface– With sensor/lens preprocessing
� Latest and greatest displays
� Software upgrades from 2430
� 65nm 7LM LP TI process– Advanced process
– Advanced power management
– Only way to fit in all “stuff” and still be ableto ship high volume..
OMAP 3430 ES1
Sept 2006
Our ASIC – OMAP/Modems - Manage Power
� See first slides
– Model
� Use case scenario
� Spreadsheet/and early model
– Variables on chip
� Voltage domains – 4 to 10 to ??
� On chip voltage – 3
– Interfaces – Bring up/down
� Important to find a way to manage
– Power off/good – and State Machine
– Standardize /automate – or bug farms
– Defined standards – handling power and control
� Nobody can roll your own -
Power Management – 90nm=50x – today at 65nm=10Kx
One Voltage Domain
SRAM Retention
5 Power Domains
#1: MCU Core
#2: DSP Core
#3: Graphic Accelerator
#4: Core + Periphery
#5: Always On logic
90 nm CMOS Technology
~90M transistors
OMAP 2420 circa 2004
OMAP/Modem ASICs - Security
� Another standardization/requirement
– GSM standard for my flash/modem authenticity and encryption
– Digital contents Rights management standards
– Secure transaction etc etc etc..
� Our ASICs
– Designs must reflect a method of standardizing
� Software/firmware/common platform
� Hardware accelerators/on chip firewalls/propagated secure mode
� We must insure – no hackers in phones /apps – this is real money ..
� Technique
– Define well thought out mechanism and just evolve it
– Do not break system/software migration- this is where TI $$$
Clocks/Reset/DFT
� This gets hard as designs get complex
� For TI ASIC– Many PLLs on chip 3 to 7 to ??
– Standardize clock control structure/control� IP/top level constraints on CTS to close
– One way to do reset – asynchr. Rest/synch set –
� DFT– Always adapting to new standards
– Achieve wireless <200 to 300 DPM and low cost test
– Design must be defect density limited – driven by volume
ASIP verification – IP and SOC – managing the bug farm…
Module/Block
Constraint random testing
Reusable test environment
Reusable stimulus
Exhaustive black/grey box
Subsystem
Directed and Random testing
Mimic chip level constraints
Reuse module level
environment
Chip
C/ASM based directed testing
Reuse from module
Synthesizable test bench
Hardware
Same environment as chip level
Application threads
Operating System boot up
HVL test bench / scoreboard / checker / assertions HDL test bench
Functional Coverage driven Functional Scenario driven Application driven
Regression Manager / Verification Dashboard – DV / Defect tracking
Verification Process – checkpoints / audit / reviews
Verification Metrics – coverage, bugs, regression, formal, cycles, efficiency tracking
SOC and IP Release/Compiles – How we coordinate designs in flight
CP2 PG
Compile 0
Compile 1
Compile 2
Compile 3
SOCdevelopment
Netlist freeze (new synthesis
will restart COMPILE3
REL0.1
Main tasks:
Top level verification
STA, Trial layout
Main tasks:
Final layout,
ECO at netlist level,
STA, GLS
Main tasks:
DFT implementation,
synthesis (EDT, scan
insertion), top level
verification setup, power
routing, package freeze,
STA setup
All modules
connected
(func + test)All modules
connected
(func only)
Data base created,
(setup, tools)
Main tasks:
Functional module
connectivity. Preliminary
synthesis.
REL0.5 REL0.8 REL1.0
IP Release
CML0.1 CML 1.0CML0.5 CML0.8
SoftMacr
o
HardMacro
Automation Tools – Avoid mistakes spec to tape
� Automated
– Spec to SOC hookup and simple test read/write/reg
– OCP centric IP and top level interconnect
– Power / reset/control management
– Configuration management/regression/progress
– Legacy IP blocks
– Standard tool flow RTL creation/track front end
– Standard tool flow backend/floorplan/STA/closure
– IP delivery and checklists/regression/
OMAP2430C
substrate
Solder resist
Mold cap : 105.0um
Modem46.0μ
23.0μ
UFR : 30.0μSolder resist : 11.0μ
61.0μ
Clearance : 62.0μ
DAF
Mold thickness : 268um
ACTUAL PACKAGE X-SECTION
OMAP/Modem ASIC – it is not just a digital problem..
OMAP 3430 ES1 First Silicon – a
picture/snapshot
� Tape Aug 2006
� First Silicon Oct 2006 – ES1
� At typical process
� Cortex A8 >700MHz
� Booted all major O/S off first silicon
� Full 3d/video/O/S – 3GSM @ 1GHz
� Coming to a phone in 2008
� A successful apps part
� A successful flow
Lessons learned OMAP 3430…
� What worked– Almost everything
– Digital design becoming predictable – just big verif tasks.
� What do we need to focus on– ESD – still a bit of a black art – better models/rules
especially analog /complex/high speed I/O
– Analog/digital integration – “boundary” models
– Routing/utilization/area prediction – new tools
– Packaging – mixing analog/PM/RF/memory
– Modeling – especially analog/PM/RF/memory
– Yet another process – 45nm/32nm..
Thank you
And thanks to WW OMAP 3430 team -