Analytical Modeling of Triple -Gate MOSFET Structures
Prof. Benjamin Iñiguez, Department of Electronic, Electrical and Automatic
Control EngineeringUniversitat Rovira i Virgili
Tarragona, Catalonia, [email protected]
Outline
• Introduction– COMON project activities– Multi-Gate MOSFETs
• Analytical Electrostatic Modeling of Triple-Gate MOS Structures
• Complete Triple-Gate MOSFET modelsdeveloped in the framework of COMON
• Conclusions
EU COMON Project – Who are we?
COMON: COmpact MOdeling Network
“Marie-Curie”Industry-Academia Partneship andPathways project (IAPP FP7, ref. pro. 218255)
Duration:4 years, started fromDecember 1 2008.
Coordinator:Prof. B. Iñiguez(URV Tarragona)[email protected] More information available on our website:
http://www.compactmodelling.eu
Melexis Ukraine
Dolphin Integration Grenoble
RFMD UK
AIM-software
Austria Microsystems
AdMOSInfineon Munich
Industrial partnersAcademic partners
URV Tarragona
UNIK Kjeller
EPFL Lausanne
TUC Chania
UdS Strasbourg
UCL Louvain-la-Neuve
ITE Warsaw
TUI IlmenauFH Giessen
Associate partners
GoalsTo address the full development chain of Compact Modeling, to
develop complete compact models of Multi-Gate MOSFETs(Foundry: Infineon, now Intel), HV MOSFETs (Foundry: Austriamicrosystems) and III-V HEMTs (RFMD (UK)).
Development of complete compact models of these types of advanced semiconductor devices.
Development of suitable parameter extraction techniques for the new compact models.
Implementation of the compact models and parameter extraction algorithms in automatic circuit design tools.
Demonstration of the implemented compact models by means of their utilization in the design of test circuits.
Validation and benchmarking: compact model evaluation for analog, digital and RF circuit design: convergence, CPU time, statistic circuit simulation.
As an IAPP project the ultimate COMON goal is the know -howtransfer from the academia to the industry
Activities funded by COMONSecondments of young researchers between academia
and industry Universities sending students to the participating companies
for several months Also, several companies sending employees to universities for
trainings Secondments are the most instrumental tool for the transfer of
knowledge between academia and industryRecruitments of postdoctoral researchers from outside
the COMON networkMOS-AK WorkshopsTraining Courses on Compact Modeling
1st Course, held in Tarragona (Spain) on June 30-July 1 2010 2nd Course, to be held Tarragona (Spain) on June 28-29
2012
6
Why several gates ?
Excellent electrostatic coupling: Short Channel Effects(SCEs) reduction leakage currentsreduction
Two conduction channels Double-gate transistor
good ION
‘Planar double-gate’ architecture
Frontgate
front channelback channel
Silicon Substrate
tSiBackgate
But self-alignment of the gatesrequired to maintain Double-gateadvantages
idea of vertical gates: FinFET type transistors
Gate misalignment
Frontgate
front channelback channel
Silicon Substrate
tSiBackgate
Multi-Gate MOSFETs• The non-classical multi-gate devices such as Double-Gate (DG)
MOSFETs, FinFETs or Gate-All-Around (GAA) MOSFETs show an even stronger control of short channel effects, and increase of on-currents taking advantage of volume inversion/accumulation.
DG MOSFET GAA MOSFET
FinFET
Tranversal cross-section for Triple-gate (b), Pi-gate FETs (c), and Omega-gateFETs (d).
Modeling Approaches
1) A purely design-oriented model developed by UCL/URV for symmetric DGMOSFETs. It is based on a 1D electrostatic analysis with semi-empirical equations with fitting parameters for short-channel effects. It can work for FinFETs and Tri-Gate MOSFETs if they are narrow enough.
2) A predictive design-oriented model developed by UdS/EPFL with the recent collaboration from URV. It was originally a quasi-2D model for DG MOSFET that became recently a quasi-3D model for Tri-Gate MOS structures. It uses very few fitting parameters and is explicit.
3) A fully 2D/3D predictive technology-oriented model, based on isomorphic expressions, developed by UniK in cooperation with URV. It is a predictive technology-oriented semi-analytical model.
1D ModelsThe first step to develop a compact model is to consider a well
behaved device, with good electrostatic control by the vertical field (from the gate) and where the derivative of the lateral field in the direction of the channel length can be neglected compared to thederivative of the vertical field in the direction perpendicular to the channel.
• This is the gradual channel approximation, and simplifies the electrostatic analysis. This leads to neglect the short-channel effects
By integrating the Poisson’s equation between the centre (y=0) and the top surface of the film (y=-tsi/2) we get an analytical expression of the vertical field at the interface, but it cannot be integrated to give an analytical expression of the potential if the doping is considered.Approximations are needed, but there is an analytical solution in the case of undoped devices
Core (1D) undoped DG MOSFET Model
• An analytical solution is possible in the case of undoped DG MOSFET or cylindrical Surrounding-Gate MOSFETs
• For undoped DG MOSFETs, Poisson’s equation:
• The resulting charge control model can be written as:
( ) ( )kT
Vxq
iSi
enq
dx
Vxd
dx
xd−
⋅⋅=−
=)(
2
2
2
2 )()(ψ
εψψ
( )
++
+=−−−
0
0
0ox
0GS Q
QQlog
q
kT
Q
Qlog
q
kT
C
QVV V
From this charge control model,we get the expression of the current:
( )
++
+
−+−=
0
0222
2
2log8
42
QQC
q
kT
C
QQQQ
q
kT
L
WI
s
dSi
ox
dsdsDS
µ
SiCq
kTQ 40 =
1D models: FinFET and Tri-Gate FET
( )
++
+=−−−
0
0
0ox
0GS Q
QQlog
q
kT
Q
Qlog
q
kT
C
QVV V
In general, in symmetric Multi-Gate MOSFETs
Charge associated to top, lateral and total charge calculated with ATLAS 3-D simulations and with the unified charge control model (FinFET with Wfin=10 nm, Hfin=50 nm)
Anyway, a more physical and scalable model is needed, taking also into account the back-bias effects
12
Tri-Gate Modeling Assumptions Undoped channels(mandatory for TG/Pi/Omega-gate FETs due to processconsiderations) ‘Well-behaved’ devices No corner effects (undopedchannels) Constant surface potential(φS1)Parabolic approximation at the body/overetched BOX boundary and at the overetched BOX/BOX boundary No quantum effects (W and H > 10 nm) Negligible carrier’s concentrations up to threshold
Transversal cross-section of an ΩFET transistor, with the notations used in this work.
Simplified boundary conditions Electrostatics described by the Laplace equation(∆φ≈0)
13
Obtaining the potential (1)…
∑∞+
=
−−+−
+=
1n
2
OV
2
OV1S3S
21S2S
2n
1SOV
)Wtπn
(sh
)W
)yt(πn(sh)φφ()
Wyπn
(sh)φφ(
)W
xπnsin(P
φ)y,x(ψ
∑∞+
=
−−+=
1n
n
1S2S1SSi
)W
xπnsin()
WHπn
(sh
W)yH(πn
(sh
W
F
)φφ(φ)y,x(ψ
Transversal cross-section of a ΩFET transistor, with the notations used in this work.
In the overetched region:
with: EN2 t2WW −= the overetched regionwidth.
Solution: development in Fourier’s series with the coefficient calculated with respect to the boundary conditions (here, surface potentials φS1,2,3):
In the channel:
14
Obtaining the potential (2)…
3n
)2
πn(
)πnsin(πn))πncos(1(2P
−−=
Transversal cross-section of a ΩFET transistor, with the notations used in this work.
with:
Coefficients coming from the parabolic approximation
)t2W()2πn
(
)Wtπn
sin())Wπnπnt2)πncos(Wπn)πncos(πnt2(
)Wtπn
cos()W2)πncos(W2)πnsin(Wπn)πnsin(πnt2(W
F
EN3
ENENEN
ENEN
n
−
−++−
++−−
=
Coefficients coming from the Ω-shape approximation
and:
15
Obtaining the front-gate threshold voltage
Bφ)B1(φVV 2S1S1FB1G −++=
)C)GE)(F
D1((φ))FGE)(
F
D1(DC(φVV 2S1S2FB2G −+++−++−−+=
Spliting the back-interface regimes (accumulation, depletion, and inversion)
Finally, after applying Gauss’ law, we obtain the two master equations:
ST2FB2G1FB2DEP,1TH
2INV,2G2G2ACC,2G
ST1FB2INV,1TH
ST2FB2INV,2G2G
ST1FB2ACC,1TH
ST2FB2ACC,2G2G
φ)DC)FGE(
FD1
1
B1()VV)(
DC)FGE(FD1
1
B(VV
:)VVV(depletedgateback)c
φVV
:)φVVV(invertedgateback)b
φ)B1(VV
))φ)FGE)(F
D1(DC(VVV(daccumulategateback)a
+−−+++++−
+−−+++−=
<<−+=
+=>−++=
−++−−+=<−
16
Front-gate threshold voltage …
Model of front-gate threshold voltage V TH1 vs. back-gate bias V G2 for Triple-gate FETs
Plateaus when the back-interface is accumulated/inverted, lineardecrease when the back-interface is depleted. Narrow devices: larger ‘depleted back-interface’ region and smalleramplitude of threshold voltage.
0.45
0.5
0.55
0.6
0.65
0.7
-40 -30 -20 -10 0 10 20
Back-gate bias, V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
, VT
H1 [
V] H = 30 nm, t OX1 = 2 nm, t OX2 = 100 nm
εOX1 = εOX2 = 3.9
W = 10 µm, 100 nm,and 50 nm
VG2 = VFB2 + φST
VTH1 = VFB1 + φST
VG2 = VG2,INV2
VG2 = VG2,ACC2
(@ W = 50 nm)accumulation plateau
invertionplateau
17
2.3 Obtaining the back-gate threshold voltage
Bφ)B1(φVV 2S1S1FB1G −++=
)C)GE)(F
D1((φ))FGE)(
F
D1(DC(φVV 2S1S2FB2G −+++−++−−+=
Similarly, it yields:
With the two master equations:
ST1FB1G1FB1DEP,2TH
1INV,1G1G1ACC,1G
ST2FB1INV,2TH
ST1FB1INV,1G1G
ST2FB1ACC,2TH
ST1FB1ACC,1G1G
φ)B1
)1CF
GE)(D1(
1()VV)(B1
1C)F
GE)(D1(
(VV
:)VVV(depletedgatefront)c
φVV
:)φVVV(invertedgatefront)b
φ)C)F
GE)(D1((VV
))φBVVV(daccumulategatefront)a
+
−−++++−
+
−−++−=
<<−+=
+=>−
−+++=
−=<−
18
Back -gate threshold voltage …
Model of back-gate threshold voltage V TH2 vs. front-gate bias V G1 for Triple-gate FETs
Plateaus when the back-interface is accumulated/inverted, linear decrease when the back-interface in depleted. Narrow devices: SMALLER ‘depleted back-interface’ regionand LARGER amplitude of threshold voltage.
-5
-3
-1
1
3
5
7
9
11
13
15
-1 -0.5 0 0.5 1
Front-gate bias, V G1 [V]
Bac
k-ga
te th
resh
old
volta
ge, V
TH
2 [V
] H = 30 nm, t OX1 = 2 nm,
tOX2 = 100 nm, εOX1 = εOX2 = 3.9
W = 10 µm, 100 nm,and 50 nm
VG1 = VFB1 + φST
VTH2 = VFB2 + φST
VG1 = VG1,INV1
VG1 = VG1,ACC1
(@ W = 50 nm)accumulation plateau
invertionplateau
19
Validation – Numerical Simulations
-1000
-800
-600
-400
-200
0
200
-15 -10 -5 0 5 10 15
Back-gate bias V G2 [V]
Thr
esho
ld v
olta
ge V
TH [m
V]
W = 500 nm
W = 100 nm
W = 30 nm
Triple-gateΠFETΩFET
numerical simulations
100
120
140
160
180
200
220
240
260
280
300
-15 -10 -5 0Back-gate bias V G2 [V]
Thr
esho
ld v
olta
ge V
TH [m
V]
numerical simulations
Triple-gateΠFETΩFET
W = 500 nm
W = 100 nm
W = 30 nm
Good agreement model/simulations for TGFETs, Pi-gate FETs, and ΩFETs. Pi-gate FET threshold voltage lesssensitive to back-gate bias than TGFET. ΩFET threshold voltage less sensitive to back-gate bias than Pi-gate FETs. Narrow devices threshold voltage lesssensitive to back-gate bias than widedevices.
Zoom of the previous figure in the back-interface accumulation/depletionzones:
Acceptable agreement and correct modelling of the ‘front-to back-interfaces coupling’coefficients
Model vs. numerical simulations for TGFETs,Pi-gateFETs, ΩFETs, and for channel width
W=30, 100, and 500 nm.
Model vs. numerical simulations for TGFETs,Pi-gateFETs, ΩFETs, and for channel width
W=30, 100, and 500 nm.
20
Validation – Experimental meas.
Good agreement model/measurementsfor experimental ΩFETs (H = 26 nm, W from 2 µm down to 50 nm). Good modelling for both NMOS and PMOS devices.
Good agreement model/measurements for experimental wide devices (ΩFETsin the planar FDSOI configuration) for different channel thicknesses(26, 13, and 7 nm).
Model vs. measurements for ΩFETs, and for channel width W from 2 µm down to 50 nm.
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
-15 -10 -5 0 5 10 15
Back-gate bias, V G2 [V]
Thr
esho
ld v
olta
ge, V
TH [V
]
PMOSΩFET
NMOS ΩFET
grounded back-gate
invariantpoints
W = 2000, 500, 250, 100, and 50 nm
W = 2000, 500, 250, 100, and 50 nm
NMOS: back-interface inversion at VG2 = 0VPMOS: back-interface depletion at VG2 = 0V
Front-gate threshold V TH1
Back-gate threshold V TH2
measurements
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-15 -10 -5 0 5 10 15
Back-gate bias, V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
, VT
H1
[V]
measurementsplanar FDSOI devices
tSi = 26, 13, and 7 nm
W = 2 µmVDS = 50 mV
Model vs. measurements for wide ΩFETs (W = 2 µm), and for channel thicknesses (t Si or H) of 26, 13, and 7 nm.
21
Why is that so important to take into account the b ack-gate?
Experimental determination of the invariant point position with the VTH1(VG2) curves for several Fin widthsW:
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
-15 -10 -5 0 5
Back-gate bias V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
VT
H1
[V]
eOX1=1.95 nm, eOX2 = 100 nm
H = 26 nm, e OV = 30 nm
W = 2000, 500, 250,100 and 50 nm
VG2 = VFB2 + φST
VG1 = VFB1 + φST
back-gate invertedat VG2 = 0V
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
-15 -10 -5 0 5
Back-gate bias V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
VT
H1
[V]
eOX1=1.95 nm, eOX2 = 100 nm
H = 26 nm, e OV = 30 nm
W = 2000, 500, 250,100 and 50 nm
VG2 = VFB2 + φST
VG1 = VFB1 + φST
back-gate invertedat VG2 = 0V
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
Comparison front-gate threshold voltage V TH1 vs. back-gate bias V G2 with model (lines) and experimental
measurements (squares)
Under ‘normal’ condition, with a grounded back-gate (VG2 ≈ 0 V):
• Direction and amplitude of the VTH(W) curves driven by the position of the invariant point• No amplitude at the invariant point. Not true elsewhere.• Back-interface in accumulation, in depletion or in inversion?
Determination of the back-gate regime at VG2= 0 V
Determination of the correct VTH1(W) evolution
22
3D potential, TG and PiFETs (1)
eOV
eOX2– eOV
0
BOX
y
H
W0
VG1
VG2x
Si channel
overetch
φS2
φS1
φS1φS1
φS3
HfO2 TiN
SiO2
Si
SiO2
Poly
eOX1
eOV
eOX2– eOV
0
BOX
y
H
W0
VG1
VG2x
Si channel
overetch
φS2
φS1
φS1φS1
φS3
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
eOX1
0z
)z,y,x(ψ
y
)z,y,x(ψ
x
)z,y,x(ψ2
2
2
2
2
2
≈∂
∂+∂
∂+∂
∂
)z,y,x(ψ)z,y,x(ψ)z,y,x(ψ)z,y,x(ψ)z,y,x(ψ )SD(Drain/Source)LG(gatesLateral)BG(gateBack)TG(gateTop +++= −−−
+++−= ∑ ∑
∞+
=
∞+
=))eH(π))
L
n()
W
m(cosh()yπ))
L
n()
W
m(cosh()
L
zπnsin()
W
xπmsin()n(F)m(F)VV()z,y,x(ψ OV
2
G
22
G
2
G1m 1n PP1FB1GTG
+++
++++−
+++
+−++
−= ∑ ∑∞+
=
∞+
=
)Wπ))eH(2
1n2()
L
m(sinh(
)xπ))eH(2
1n2()
L
m(sinh())xW(π)
)eH(2
1n2()
L
m(sinh(
))eH(2
)yeH(π)1n2(sin()
L
zπmsin()n(F)m(F)VV()z,y,x(ψ
2
OV
2
G
2
OV
2
G
2
OV
2
G
OV
OV
G1m 0n nP1FB1GLG
+++
++++−
+++
+−++
=∑ ∑∞+
=
∞+
=
)Lπ))eH(2
1n2()
W
m(sinh(
)zπ)))eH(2
1n2()
W
m(sinh(V))zL(π))
)eH(2
1n2()
W
m(sinh(V
))eH(2
)yeH(π)1n2(sin()
W
xπmsin()n(F)m(F)z,y,x(ψ
G2
OV
2
2
OV
2DG
2
OV
2S
OV
OV
1m 0n nPSD
++−++= ∑ ∑
∞+
=
∞+
=))eH(π))
L
n()
W
m(sinh())yeH(π))
L
n()
W
m(sinh()
L
zπnsin()
W
xπmsin()n(F)m(Fφ)z,y,x(ψ OV
2
G
2OV
2
G
2
G1m 1n PP3SBG
with: )))eH(π))
L
n()
W
m(tanh(π)
L
n()
W
m()
2
πnsin()
2
πmsin()n(F)m(F
)ee(ε
ε1()VV(φ OV
2
G
22
G
2
1m 1n PPOV2OXBOX
Si2FB2G3S
+++
−+−= ∑ ∑
∞+
=
∞+
=
W being the fin width, H the fin height, LG the gate length, eBOVB
the overetch depth, εBBOXB
the BOX permittivity, εBSiB
the silicon permittivity, VBFB1 (resp. VFB2)
B
the front-gate (resp. back-gate) flat band voltage. The series coefficient Fp, Fn, and Fc are defined in the Appendix.
3D Laplace’s equation to solve:
Boundary conditions: Influence of the 6 terminals (3 sides of the
top-gate, back-gate, source and drain) considered separately.
Dirichlet (with constant or parababolicboundary conditions) or Neumann.
3D potential:Transversal cross-section
TGFET/PiFET, with notations.
23
3D potential, TG and PiFETs (2)- Constant potential boundary condition :
πn
))πncos(1(2)n(Fc
−=
- Parabolic potential boundary condition
3P
)2
πn(
)πnsin(πn))πncos(1(2)n(F
−−=
- Neumann boundary condition :
))2
π)1n2(cos(1(
π)1n2(
4)n(Fn
+−+
=
0
0.1
0.2
0.3
0.4
0.5
0.6
0 5 10 15 20
Lateral axis, y [nm]
Ele
ctro
stat
ic p
oten
tial [
V]
lateral sides of the front-gate
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 10 20 30 40
Longitudinal axis, z [nm]E
lect
rost
atic
pot
entia
l [V
]
VG1 = 0, 0.3, 0.5 V
Source
Drain
With the boundary coefficients:
BOX
source
drain
channelgate
x
y
zBOX
source
drain
channelgate
x
y
z
Validation of the model:
TGFET (closed symbols) and PiFET (open symbols)
TGFET (closed symbols) and PiFET (open symbols)
Model Flow Chart
24
1. Calculation of minimum of potential’s position
2. Calculation of minimum of potential
3. Calculation of subthreshold current
4. Derivation of subthreshold slope
For undoped channels and deep subthreshold operation, theposition of the most leaky path is determined mostly by the thedevice geometry (and gate biases boundary conditions)
Most leaky path: approximation saying that the current flowingwhere the gate control is the weakest gives a good reproduction ofthe global device’s behavior.
Calculation of the minimum potentialCalculation of the minimum potential Position of the ‘most leaky path’:
At mid-channel (y=W/2) for obvious symmetry considerations
At the body/BOX interface (x = tOV): generally true, not necessarily for
L<(W,H) but is a correct approximation
Along the Source/Drain axis:
Low VDS: ZC = LG/2
High VDS: minimum of potential moving closer to the source
Finally: φMIN = φ(tOV,W/2,ZC)
Formula from [Pei´02]:
)Vφ
φln(
π2
L
2
LZ
DSMS
MSDGC +−
−+=
2/1
22D H
5.0
W
1L
−
+=with:
Simpler and acceptable approximation
[Pei’02] G. Pei et al., IEEE TED, 2002.
0
5
10
15
20
25
30
35
40
45
50
20 40 60 80 100
Gate length, L G [nm]
Min
imum
of p
oten
tial [
nm]
VDS = 1.2 V
W = 20 nm, H = 20 nm
W = 20 nm, H = 100 nm
W = 100 nm, H = 20 nm
LG/2
Position of the minimum of potential along the S/D axis– comparison between the results given by the
numerical simulations (closed symbols) and theanalytical formula (open symbols)
Calculation of the Calculation of the subthresholdsubthreshold currentcurrent
∫ ∫+
−
−−=Ht
t
2/W
2/W
V/)Z,y,x(φV/V
G
tiDS
OV
OV
TCMINtDS dxdye)e1(L
VqnµI
Using the most leaky path approach, current expressed as:
Assuming Drift-Diffusion transport, drain current written as:
∫∫ ∫
∫
+
−
−
=G
OV
OV
T
DSTF
L
0 Ht
t
2/W
2/W
V)z,y,x(φ
V
0 FVφ
iDS
dxdye
dz
φdenµqI
This work: approximation that the exponential of the potential can be described by a parabola in the width direction and is constantin the height direction.
Approximation amounting to say that a majority of carriers are located close to φMIN, i.e. in the vicinity of (x=W/2, y=tOV)
Calculation of the Calculation of the subthresholdsubthreshold currentcurrent
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
-0.5 0 0.5 1 1.5
Front-gate bias V G1 [V]
Dra
in c
urre
nt I
D [A
] VDS = 50 mV
VDS = 1.2 V
LG = 90 nm
LG = 50 nm
W = 50 nmH = 26 nmtOV = 30 nmtOX1 (EOT) = 1.95 nmtOX2 = 100 nm
Finally, after integration:
3
ee2WH)e1(
L
VqnµI
t1GtCOV
tDS
V/VV/)Z,t,2/W(φV/V
G
TiDS
+−=
n.b.: φ(W/2,tOV,ZC) also a function of VG1
Subthreshold analytical (symbols) and experimental (solid lines) drain currents I D vs. front-gate bias V G1
for gate lengths L G of 90 nm (squares) and 50 nm (diamonds).Gate width W = 50 nm, H = 26 nm.
Formula allowing to
take into account
the drain and short
channels effect in the
subthreshold regime
Good precision obtained
compared to experimental
measurements [Jahan’05]
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
Subthreshold slope , DIBL
60
65
70
75
80
85
90
95
100
105
110
40 50 60 70 80
Gate width, W [nm]
Sub
thre
shol
d sl
ope,
SS
[mV
/dec
]
LG = 90, 70, 50, and 40 nm
LG,EFF = LG + 10 nm
0
50
100
150
200
250
40 50 60 70 80
Gate width, W [nm]
DIB
L [m
V/V
] LG = 90, 70, 50, and 40 nm
LG,EFF = LG + 10 nm
VDS = 0.1, and 1.2 V
SS vs. gate width W and gate length L G.Model (lines) and experimental
measurements (symbols)
DIBL vs. gate width W and gate length L G.Model (lines) and experimental
measurements (symbols)
Calculation of the potentialminimum and derivation of thesubthreshold slope and DIBL.
Correct agreementmodel/experimental.
Subthreshold characteristicsimproved with narrower devices.
Device Scaling
Structure Features Pi-gateFET (core structure) tOV ≠ 0
TGFET tOV ≈ 0 Planar FDSOI tOV ≈ 0, W>>H
DGFET/FinFET tOV ≈ 0, W<<H Gate All Around tOV ≈ 0, φS3 = VG1 – VFB1
SS vs. gate gate length L G for GAA (open squares), PIFET (circles), TGFETs (triangles), DGFET (diamonds )
and planar FDSOI (squares). Model (lines) and simulations (symbols)
PiFET structure adaptable toTGFETs, DGFETs, planarFDSOI devices, and GAA transistors.
Expressions extendible to a large number of MuGFETs.
Variations of the core structure
50
60
70
80
90
100
110
120
130
140
150
160
170
20 30 40 50 60 70 80 90 100
Gate length, L G [nm]
Sub
thre
shol
d sl
ope,
SS
[mV
/dec
]
W = 30 nmH = 30 nmtOV = 60 nm
VD = 100 mV
Semi-Empirical Design -Oriented Model forMulti-Gate MOSFETs
Model developed as a collaboration between UCL (Belgium), URV (Spain) and CINVESTAV (Mexico).
Model dedicated to the simulation of analog and mixed signal circuits using DG MOSFETs, than can also be applied to FinFET as well as trigatesstructures with a narrow width fin, by appropriately fitting theparameters.
The model equations are based on analytical expressions of the potentials , that allow continuity in all operation regions for undopedand doped silicon layers, up to NA=2⋅1018cm-3.
Several effects are taken into account in the model, like geometrical and process related aspects (oxide thickness, width fin, high fin, polysiliconand midgap metal gates), effects of doping profile, mobility effects due to the vertical and longitudinal fields, and short-channel effects due to velocity saturation, channel-length modulation, roll-off and DIBL and temperature effects, by means of semi-empirical equations.
Semi-Empirical Design OrientedDG MOSFET model
Simulated and modeled transfer characteristics for 3 mm and 100nm channel lengths at VD=50 mV: (a) I-V curves and (b) semilog I-V curves.
Predictive Design Oriented Multi-Gate MOSFET Model
The UdS and EPFL teams developed a strongly physically-based and explicit compact model for lightly doped FinFETs, which has been extended to doped devices.
It is both a predictive and a design-oriented model valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters.
The model is based on a core charge control model derived from the 1D Poisson’s equation, with extensions coming from the remaining 2D/3D Poisson’s equation.
The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential.
Predictive Design Oriented Multi-Gate MOSFET Model
A physics-based 2D/3D approach is followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, using hyperbolic functions.
The cross section and back bias modeling scheme developed by URV, seen before, can be incorporated into this model
Velocity saturation, channel length modulation and carrier mobility degradation are also included.
The quasi-static model is then developed and accurately accounts for small-geometry effects as well.
Predictive Design Oriented Multi-Gate MOSFET Model
10-15
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
Co
ura
nt
de
dra
in,
I D (
A)
1.00.80.60.40.20.0
Tension de grille, VGS
(V)
60
50
40
30
20
10
0
x10-6
WSi
= 3 nm
HSi
= 50 nm
tox
= 1.5 nm
VDS
= 1 V
L = 25 nm
L = 40 nm
L = 100 nm
80
70
60
50
40
30
20
10
0
Co
ura
nt
de
dra
in,
I D (
µA
)
1.00.80.60.40.20.0
Tension de drain, VDS
(V)
L = 25 nm WSi
= 3 nm HSi
= 50 nm tox
= 1.5 nm
VGS
= 0.6, 0.7 ... 1 V
Validity of the extended model:
Gate length (L): down to 25 nmSilicon width (WSi): down to 3 nmSilicon height (HSi): down to 50 nmChannel doping (Na): intrinsic to 1017 cm-3
nMOS and pMOS
2D/3D Technology -Oriented Multi-Gate MOSFET Modeling
Objectives:
• Establish unified analytical models for nanoscale MugFETs (multigateMOSFETs) including FinFET and GAA devices The model was developedby UniK and URV
Procedure :
• Decompose Poisson’s equation into a Laplace equation and aresidual Poisson’s equation (superposition principle)
Capacitive inter-electrode effects- From 2D/3D Laplace equation determine potential distributionassociated with capacitive inter-electrode coupling.
- Use this to calculate subthreshold electrostatics, drain current andcapacitances
Near and above threshold- Apply residual Poisson’s equation, boundary conditions, and modelingexpressions to determine self-consistent device properties
Schematic representation of 2D cut-plane of DG FinFET and trigateFinFET respectively
Schematic representation of 2D cut-plane of quad- and cylindrical GAA devices respectively
2D/3D Technology -Oriented Multi-Gate MOSFET Modeling
The final model is based on the use of isomorphic modeling expressions for the potential distribution in (x,y) cross sections perpendicular to the source-drain z axis.
In subthreshold, this allows the complete potential distribution in the device body to be obtained based on the Laplace equation.
Short-channel effects are included by introducing auxiliary boundary conditions, such as the device center potential and the electrical field at the source center, derived analytically from the conformal mapping analysis.
A similar procedure, again using isomorphic modeling expressions, can also be applied to strong inversion by invoking Poisson’s equation.
Starting from a rectangular gate structure, the present modeling can be generalized to include FinFETs, trigate, square gate, DG, and even circular gate devices, laying the groundwork for a unified, compact
modeling framework for a wide range of multigate MOSFETs.
2D/3D Technology -Oriented Multi-Gate MOSFET Modeling
( ) ( )2 2
1
2 2ˆ ˆ, , 0,0, 1 1' '
i in
ii
x yx y z z
a bφ φ α
=
= − −
∑
( )zyx ,,ϕ
We first consider a MugFET with a rectangular (x,y) cross-section of silicon widths a and b, for which we write the potential distribution as a ‘power expansion’ of the following isomorphic form,
Here a’ = a + 2t’ox, b’ = b + 2t’ox and t’ox = toxεsi/εox is an equivalent silicon layer that represents the electrostatic effect of the true gate insulator
is the body potential relative to the gate interface.
(0,0,z)
y
xb
t’ox
a
a’
Silicon body
b’
Insulator
FinFET modeling
Modeled potential compared to numerical simulations along the height (y) direction for rec-gate devices with κ = 4 and 5, Vds= 0 V, Vgs = – 0.1V.
Modeled potential compared to numerical simulations along the height direction for a trigate device. Aspect ratio of original rec-gate device: 5:1. Vds = 0 V, Vgs = – 0.1V
Drain current and capacitance results
Conclusions
• Analytical solution of the 2D Laplace’s equation under threshold in the case of TGFETs, PiFETs, and OmegaFETs.
• Definition of a threshold voltage model forTGFETs/PiFETs/OmegaFETs, for all type of dimensions(excluding the quantum regime), for NMOS/PMOS, in all regimesof the back-gate (including the two threshold voltages in the‘back-interface inversion’ regime).
• Validation of the model with numerical simulations andexperimental measurements.
• Analytical solution of the 3D Laplace’s equation under threshold in the case of TGFETs, and PiFETs.
• Analytical model for short channel characteristics (SS, DIBL).• Expression for the device scalability of MuGFETs.
ConclusionsUnder the framework of the “COMON” EU Project,
compact models for Multi-Gate MOSFETs, HV MOSFETs and HEMTs have been developed.
By the end of “COMON” (Nov 2012) several models will be completed and ready for standardization:
Three Multi-Gate MOSFET models:
1) Purely design-oriented model
2) Predictive and design-oriented model
3) Predictive technology-oriented model
Thank you for your attention!
43
Invariant point
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
-50 0 50 100
vertical axis y [nm]
Ele
ctro
stat
ic p
oten
tial [
V]
body BOX
VG2 = VFB2 + ΨST
x = 0 nm (at mid-channel)
gate
gate oxide
VG1 = ΨS1 = ΨS2 = VFB1 + ΨST
Model of the potential at mid-channel (x=W/2)for V G2 = VFB2 + φST and VG1=VTH1=VFB1+φST
Invariant point predicted by the modelexperimentally observed Invariant point occuring for VG1 = VFB1 + φST and VG2 = VFB2 + φST
Interesting solution to alleviate the thresholdvoltage variations due to the process variability of W and H.
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
-15 -10 -5 0 5
Back-gate bias V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
VT
H1
[V]
eOX1=1.95 nm, e OX2 = 100 nm
H = 26 nm, e OV = 30 nm
W = 2000, 500, 250,100 and 50 nm
VG2 = VFB2 + φST
VG1 = VFB1 + φST
back-gate invertedat VG2 = 0V
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
-15 -10 -5 0 5
Back-gate bias V G2 [V]
Fro
nt-g
ate
thre
shol
d vo
ltage
VT
H1
[V]
eOX1=1.95 nm, e OX2 = 100 nm
H = 26 nm, e OV = 30 nm
W = 2000, 500, 250,100 and 50 nm
VG2 = VFB2 + φST
VG1 = VFB1 + φST
back-gate invertedat VG2 = 0V
HfO2 TiN
SiO2
Si
SiO2
Poly
HfO2 TiN
SiO2
Si
SiO2
Poly
Invariant point
Compensation of the back-gate induced potential drop Flat potential in the channel Potential insensitive to channel width and height W and H