Analog Building Blocks for P326 Gigatracker Front-End

ElectronicsSorin Martoiu, Univ./INFN Torino

Outline• Front-End Cell Building Blocks• CFD analysis• “CMOS” implementation

– Passive Filter– Scaling

• Dynamic Offset cancellation• Coincidence discriminator vs. zero-crossing discriminator w/

leading-edge hysteresis • Preamplifier• Single-ended to differential block• Overall performance• Additional blocks• Conclusion & Discussion

Front-End Cell Building Blocks

• PA Preamplifier• SEDB Single-ended to differential buffer• CFCF CFD filter• ZCS Zero-crossing discriminator• DD Digital driver

PA

SEDB CFDF ZCD DD

Chip Floorplan Proposal

Cell0

Cell1

CellN

Digital noise

Readout

CFD analysis

• Ideally zero time-walk• No delay-line in CMOS• LP filter instead

• σt = σnoise/(dV/dt) time-walk ~ offset/(dV/dt)

Delay

Hdelay(s) = HLP(s)

Hdiscr(s)

ZC discriminator

f

Bipolar signal

CFD analysis

• Increasing filter order performance approaches ideal delay line CFD

1 2 3 4 5

-0.3

-0.2

-0.1

0.1

0.2

1 2 3 4 5Filter order

1

1.1

1.2

1.3

1.4

1.5

epolSa.u.

“CMOS” Differential Implementation

Filter Scaling

• kT/C noise floor => high C for low noise• high peak current from input nodes• non-uniform filter – C scales up from in to out nodes, w/

RC = constant

Non-uniform scaling Uniform scaling

1,0 1,2 1,4 1,6 1,8 2,00,0

20,0µ

40,0µ

60,0µ

80,0µ

100,0µ

90,0µ

100,0µ

110,0µ

120,0µ

130,0µ

140,0µ

150,0µ

Curr

ent (A

)

K

RM

S N

ois

e (V)

1 2 3 4 510,0µ

20,0µ

30,0µ

40,0µ

50,0µ

60,0µ

70,0µ

80,0µ

90,0µ

100,0µ

80,0µ

100,0µ

120,0µ

140,0µ

160,0µ

180,0µ

200,0µ

220,0µ

Curr

ent (A

)

kc

RM

S N

ois

e (V)

Dynamic Offset Compensation

• Offset cancellation• Low-pass feedback => high-pass overall transfer

=> reduce low-frequency noise (1/f noise)

I+I

I-I

Dynamic Offset Compensation

Coincidence discriminator

• Noise produces inherent noise switching at output of ZCD

• Need parallel leading-edge discriminator to mask noise switching

• Noise switching is not eliminated

Delay

ZC discriminator

f

ZCD w/ hysteresis

• ZCD “arms” when the bipolar signal crosses a certain threshold

• Switching noise is eliminated• Additional fast block w/o offset compensation =>

may introduce some time walk

Front-End Cell Building Blocks

• PA Preamplifier• SEDB Single-ended to differential buffer• CFCF CFD filter• ZCS Zero-crossing discriminator• DD Digital driver

PA

SEDB CFDF ZCD DD

Preamplifier

• Peaking time 5ns• Gain 40mV/fC• Output noise < 1mV

@Cd=200 fF (150e- ENC)• Non-linearity < 1.5%

0,0 500,0n 1,0µ 1,5µ 2,0µ 2,5µ 3,0µ 3,5µ 4,0µ 4,5µ0,0

50,0m

100,0m

150,0m

200,0m

250,0m

300,0m

350,0m

400,0m

450,0m "vampl" Linear Fit of preamplin_vampl

Vout p

eak

(V)

Detector curent peak (A)

SED Buffer

• High drive current ~ 100uA• GBW > 500MHz• Good linearity• Good CMRR• Class AB differential opamp with CMFB and CMFF

SED Buffer

CFDF + ZCD Layout

Status

• Full channel simulations:– jitter: 100ps rms (1fC signal)– time-walk: 200ps max

Power Consumption

Block IDD (uA) P@Vdd=1.2

(uW)

PA 70 84

SEDB 250 300

ZCD 110 132

DD 70 84

Total 500 uA 600 uW

Potential problems

• Disturbances at sensitive nodes• Parasitics

– decrease bandwidth– induce non-linearity

• Input and/or output skews – affect measurement

PA

SEDB CFDF ZCD DD

Timewalk0,25

0,05

0,075

0,1

0,125

0,15

0,175

0,2

0,225

Amplitude1000 20 40 60 80

Plot 0landau distr landau distr 2

100

0

20

40

60

80

Amplitude1000 20 40 60 80

Plot 0Timewalk curve

0,25

0,05

0,075

0,1

0,125

0,15

0,175

0,2

0,225

Time error (ps)1000 20 40 60 80

Plot 0Time error distr Timewalk curve