Alvise Bagolinia, Maurizio Boscardin a, Gian-Franco Dalla Bettab, Gabriele Giacominia, Francesca Mattedia, Marco Povolib, Nicola Zorzia
a Fondazione Bruno Kessler (FBK-CMM) Italyb INFN and University of Trento, Italy
Production of 3D silicon pixel sensors at FBK for the ATLAS IBL
3D silicon pixel sensor productionThe layout has been developed in the in the framework of the ATLAS 3D Sensor Collaboration
• FE-I4 (8x)
• FE-I3 (9x)
• CMS (3x)
• test structures
3D_DDTC with passing-through columns technology was used for the first production oriented to the ATLAS insertable B-Layer
dead area of 200 mm
Ohmic Side
Junction side
50 µm
125 µm
FE-I4 sensor 80 x 336 pixels
Layout details of a FE_I4 sensor
• Column depth equal to the wafer thickness, etched from both sides
• Full double side process• Surface isolation with p-spray
on both sides• No support wafer• Columns (~12 µm diam.) are
“empty”, doped by thermal diffusion and passivated by SiO2
• Edge protection in order to improve the mechanical yield
t
p+ col.
n+ col.
p-spray
edge protection
p-sub
3D-DTC with passing through columns
• Optimization of DRIE recipe for holes with higher aspect ratio in order to improve the uniformity of the etch rate throughout the process.
• Optimization of edge protection in order to • increase the mechanical yield after DRIE etching • reduce the wafer bowing and consequently the leakage
current
Main technological aspects
Optimize DRIE recipe for holes with higher aspect ratio
Etch stop for DRIE etching
≈ 12 µm
≈ 10 µm
≈ 234 µm≈ 11 µm
≈ 5 µm
208 µm
Optimize edge protectionMechanical fragility of wafers manly due to a cracks on the wafer edge caused by D-RIE etch step:
Need a special edge protection during DRIE etching (electrostatic clamping) to prevent the creation of cracks that could cause the breakage during the processing.
Need a special care during processing
Mechanical yield with the optimized edge protection:
initial wafers
broken wafers
mechanical yield (%)
3D ATLAS 10 25 5 80%3D ATLAS 11 25 3 88%3D ATLAS 12 23 6 74%3D ATLAS 13 20 8 60%
3D_ATLAS10
Optimize edge protection: wafer bowing
Old edge protection wafers warp up to 120 µmOptimized edge protection wafers warp < 30 µm
Edge protection effects on the wafer bowing.
A high bowing induces High leakage current Misalignment among columns Bonding problem
Wafer bowing: leakage current The wafer bowing strongly influences the leakage current.
With the optimized edge protection it is reduced of one order of magnitude.
Leakage current on planar test diodes (4mm2)
Old edge protection Optimized edge protection
Wafer bowing: Column alignment
old edge protection misalignment of a
several μm
left side center right side
optimized edge protection layer
Misalignment < 5μm
Temporary metal for electrical characterization
• The temporary metal shorts 336 pixels together in a strip • Allows to perform electrical tests on the FE-I4 pixel sensors before
bump-bonding• The IV characteristics of 80 strips form a FE-I4 pixel sensor
336 pixels ( 2 electrodes per pixel)
80 strip
Temporary Metal: IV characteristicsThe IV characteristics of 80
strips of two sensors The IV characteristics of FE-I4 pixel sensor as a sum of 80 IV strips curves
VBD and Ileak of the FE-I4 strips
Good uniformity from batch to batch related to the 80 strips of each detector
Numbers of production4 production batches
Selected wafers at least 3 FE-I4 sensors qualified
Selection criteria before bump-bonding:•Vdepl ≤ 15V and•Vop ≥ Vdepl +10V•I (Vop) < 2mA per tile•Vbd > 25V •[I (Vop) / I(Vop – 5V)] < 2
Batch Tested Wafers
Selected Wafers
Total Sensors
Number of Good Sensors
Yield on Selected Wafers (%)
3D ATLAS 10 20 12 96 58 60%3D ATLAS 11 11 4 32 14 44%3D ATLAS 12 16 13 104 63 61%3D ATLAS 13 11 4 32 15 47%
Litho n+ on junction side
Problem with resist adhesion
Low final yield
Problem Investigation on 3D_Atlas11
ConclusionFBK has developed and optimized the technology used for the production
of Si-3D pixel sensors for the ATLAS IBL with a relatively good yield.
Outlook
Upgrade to 6 inchadvantages• Production capability = double the wafers
area• DRIE upgrade with a thin ceramic edge
protection = increasing of the mechanical yield
disadvantage• We have to learn how to process a thin
wafers