ALU for MIPSrequirements ?
support the arithmetic/logic operations: add, addi addiu, sub, subu, and, or, andi, ori, xor, xori, slt, slti, sltu, sltiu
design a multiplier
design a divider
*
*
Q outputs sampled value for rest of cycle.
Q
Where?
CLK
Change
Rst
D
Q
D
Q
D
Q
R
G
Y
Q outputs sampled value for rest of cycle.
D
Q
CLK
ff ff_R(R, next_R, CLK);
ff ff_Y(Y, next_Y, CLK);
ff ff_G(G, next_G, CLK);
wire next_R, next_Y, next_G;
output R, Y, G;
Next State Combinational Logic
wire next_R, next_Y, next_G;
next_G
next_R
next_Y
R
G
Y
Rst
Change
ff ff_R(R, next_R, CLK);
ff ff_Y(Y, next_Y, CLK);
ff ff_G(G, next_G, CLK);
R
G
Y
ALU for MIPS ISA
*
*
If we set Binvert = Carryin =1
then we can perform a - b
*
*
*
design the most significant bit ALU
most significant bit need to do more work (detect overflow and MSB can be used for slt )
how to detect an overflow
overflow = carryin{MSB} xor carryout{MSB]
overflow = 1 ; means overflow
set-on-less-than
slt $1, $2, $3; if $2 < $3 then $1 = 1, else $1 = 0
*
Overflow
*
ALU for MIPS
Critical path of 32-bit ripple carry adder is 32 x carry propagation delay
How to solve this problem
design trick : use more hardware
design trick : look ahead, peek
carry look adder (CLA)
1 1 1 generate
*
two 4-bit numbers: a3a2a1a0, b3b2b1b0
p0 = a0 + b0; g0 = a0b0
c1 = g0 + p0c0
c2 = g1 + p1c1
c3 = g2 + p2c2
c4 = g3 + p3c3
larger CLA adders can be constructed by cascading 4-bit CLA adders
other adders: carry select adder, carry skip adder
*
glue simple components together
work on the things you know how to do. The unknown will become obvious as you make progress
Successive Refinement
multiplier design
divider design
binary : 0 place 0
*
64 bits
32 bits x 32 bits; using 64-bit multiplicand reg. 64 bit ALU, 64 bit product reg. 32 bit multiplier
ADD
or multiplicand
Control provides
four control
1.a if multiplier0 = 1, add
multiplicand to product
4. 32nd repetition ? if yes done
if no go to 1.
*
0 initial 0101 0000 0010 0000 0000
1 1.a 0101 0000 0010 0000 0010
2 0101 0000 0100 0000 0010
3 0010 0000 0100 0000 0010
2 2 0010 0000 1000 0000 0010
3 0001 0000 1000 0000 0010
3 1.a 0001 0000 1000 0000 1010
2 0001 0001 0000 0000 1010
3 0000 0001 0000 0000 1010
4 2 0000 0010 0000 0000 1010
3 0000 0010 0000 0000 1010
0010 x 0101 = 0000 1010
*
1/2 bits in multiplicand always 0
use 64-bit adder is wasted (for 32 bit x 32 bit)
0’s inserted into multiplicand as shifted left, least significant bits of the product does not change once formed
3 steps per bit
*
32 bits
32-bit multiplicand reg. 32-bit ALU, 64-bit product reg. 32-bit multiplier reg
ADD
or multiplicand
1a. if multiplier0 = 1 add
multiplicand to the left
the result in the left half of
product register;
4. 32nd repetition ? if yes done
if no, go to 1.
*
0 initial 0011 0010 0000 0000
1 1.a 0011 0010 0010 0000
2 0011 0010 0001 0000
3 0001 0010 0001 0000
2 1.a 0001 0010 0011 0000
2 0001 0010 0001 1000
3 0000 0010 0001 1000
3 2 0000 0010 0000 1100
3 0000 0010 0000 1100
4 2 0000 0010 0000 0110
3 0000 0010 0000 0110
*
Observations
product reg. wastes space that exactly matches the size of multiplier
3 steps per bit
*
multiplicand
Multiply Algorithm Version 3
1. test product0 (multiplier is in the right half of product register)
1a. if product0 = 1
half of product and place the
result in the left half of product
register
3. 32nd repetition ? if yes, done
if no, go to 1.
*
iter. step multiplicand product
2 1110 0111 0101
2 1110 1010 1010
4 1.a 1110 1 0011 0101
2 1110 1001 1010
14 x 11 = 154
*
Observations
2 steps per bit because of multiplier and product in one register, shift right 1 bit once (rather than twice in version 1 and version 2)
MIPS registers Hi and Li correspond to left and right half of product
MIPS has instruction multu
How about signed numbers in multiplication ?
method 1: keep the sign of both numbers and use the magnitude for multiplication, after 32 repetitions, then change the product to appropriate sign.
method 2: Booth’s algorithm
*
normal approach Booth’s approach
0010 0010
0110 0110
Booth’s approach : replace a string of 1s in multiplier by two actions
*
011111111111111111110
(previous bit)
1 0 beginning of a run of 1s sub. mult’d from
left half of product
1 1 middle of a run no arithmetic oper.
0 1 end of a run add mul’d to left
half of product
*
product shift right 1110 0001 0011 1
2 shift right 1110 0000 1001 1
3 shift right 1110 0000 0100 1
4 add 1110 1110 0100 1
shift right 1110 1111 0010 0
-2 x 7=-14 in signed binary 1110 x 0111 = 1111 0010
previous
bit
To begin with we put multiplier at the right half of
the product register
Divide Hardware Version 1
64-bit divisor reg., 64-bit ALU, 32-bit quotient reg. 64-bit remainder register
divisor
*
start: place dividend in remainder
1. sub. divisor from the remainder and place the result in remainder
2. test remainder
2a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1
2b. if remainder <0, restore the original value by adding divisor to remainder, and place the sum in remainder. shift
quotient to left and setting new least significant bit 0
3. shift divisor right 1 bit
*
0 initial 0000 0010 0000 0000 0111
1 1 0000 0010 0000 1110 0111
2b 0000 0010 0000 0000 0111
3 0000 0001 0000 0000 0111
2 1 0000 0001 0000 1111 0111
2b 0000 0001 0000 0000 0111
3 0000 0000 1000 0000 0111
3 1 0000 0000 1000 1111 1111
2b 0000 0000 1000 0000 0111
3 0000 0000 0100 0000 0111
4 1 0000 0000 0100 0000 0011
2a 0001 0000 0100 0000 0011
3 0001 0000 0010 0000 0011
5 1 0001 0000 0010 0000 0001
2a 0011 0000 0010 0000 0001
3 0011 0000 0001 0000 0001
*
1/2 of divisor is wasted
1/2 of 64-bit ALU is wasted
Possible improvement
instead of shifting divisor to right, shifting remainder to left ?
*
Divide Hardware Version 2
32-bit divisor reg. 32-bit ALU, 32-bit quotient reg., 64-bit remainder reg.
divisor
1. shift remainder left 1 bit
2. sub. divisor from the left half of remainder and place the result in the left half of remainder
3. test remainder
3a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1
3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift quotient to left and setting new least significant bit 0
4. n repetitions ? if yes, done,
if no, go to 1.
*
0 initial 0000 0011 0000 1111
1 1 0000 0011 0001 1110
2 0000 0011 1110 1110
3b 0000 0011 0001 1110
2 1 0000 0011 0011 1100
2 0000 0011 0000 1100
3a 0001 0011 0000 1100
3 1 0001 0011 0001 1000
2 0001 0011 1110 1000
3b 0010 0011 0001 1000
4 1 0010 0011 0011 0000
2 0010 0011 0000 0000
3a 0101 0011 0000 0000
*
Further improvement (version 3)
eliminating quotient register by combining with remainder register as shifted left
therefore loop contains only two steps, because the shift of remainder is shifting the remainder in the left half and the quotient in the right half at the same time
consequence of combining the two registers together is the remainder shifted one time unnecessary at the last iteration
*
32-bit divisor register, 32-bit ALU, 64-bit remainder register, 0-bit quotient register (quotient bit shifts into remainder register, as remainder register shifts left)
divisor
1. shift remainder left 1 bit
2. sub. divisor from the remainder and place the result in remainder
3. test remainder
3a. if remainder >= 0, shift remainder to left setting the new rightmost bit to 1
3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift remainder to left and setting new least significant bit 0
4. n repetitions ? if yes, done,
if no, go to 2.
*
iter. step divisor remainder
1 0101 0001 1100
3b 0101 0011 1000
3b 0101 0111 0000
3a 0101 0100 0001
3b 0101 1000 0010
quotient
Observations
same hardware as multiply, need a 32-bit ALU to add and subtract and a 64-bit register to shift left and right
divide algorithm version 3 is called restoring division algorithm for unsigned numbers
Signed numbers divide
simplest method
remember signs of dividend and divisor, make positive, and finally complement quotient and remainder as necessary
dividend and remainder must have the same sign
quotient is negative if dividend sign and divisor sign disagree
SRT (named after three persons) method
an efficient algorithm
unsigned 0 <-------------> 2N-1
BCD 0 <-----------------------> 10N/4 - 1
rationals, such as 2/3; irrationals such as 2;
transcendentals, such as , .
6.12 x 10 23
hidden integer bit: 1.M
a FP number N = (-1)S 2(E-127) (1.M)
0 = 0 00000000 00000000000000000000000
-1.5 = 1 01111111 10000000000000000000000
S E M
-0.75 =-0.11b=-1.1 x 2-1 E=126 1 01111110 10000.......0
-5.0 = -101.0b=-1.01 x 22 E=129
7 = 111b = 1.11 x 22 E=129
*
(1.0) 2 -126
(1.11111111111111111111111)binary 2127 = (2 - 2-23) 2127
*
255 0 infinite
other topics in FP numbers
1. extra bits for rounding
2. guard bit, sticky bit
3. algorithms for FP numbers
*
Number is: (-1)s (1.M) x 2E-1023
*
b. Sig(X) = Sig(X) >> Diff
Sig = Sig(X) + Sig(Y)
3. Normalize the sum
1. shift Sig right/left until leading bit is 1; decrementing or incrementing Exp.
2. Check for overflow in Exp
3. Round
*
1. 0110 x 23
0. 1100 x 23
Add the aligned components
10. 0010 x 23
4-bit significand; extra bit needed for accuracy
1. Align binary point:
1. 0001 x 23
- 0. 01111 x 23
0. 10011 x 23
1.0011 x 22 = 4.75
*
Want arithmetic to be fully precise
IEEE 754 keeps two extra digits on the right during intermediate calculations (guard digit, round digit)
Alignment step can cause data to be discarded (shifted out on right)
2.56 x 100 + 2.34 x 102
2.3400 x 102
+ 0.0256 x 102
2.3656 x 102
±