A 40-Gb/s Decision Circuit A 40-Gb/s Decision Circuit in 90-nm CMOSin 90-nm CMOS
T. Chalvatzis1, K. H. K. Yau1, P. Schvan2,
M.-T. Yang3 and S. P. Voinigescu1
1Department of Electrical and Computer Engineering,
University of Toronto, Toronto, Canada2Nortel Networks, Ottawa, Canada
3TSMC, Hsin-Chu, Taiwan
T. Chalvatzis, University of Toronto - ESSCIRC 2006 2
OutlineOutline
• Motivation• Decision Circuit Design• Measurement Results• Summary
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MotivationMotivation
• Low-power, high-speed blocks in CMOS for mm-wave A/D Conversion [Chalvatzis, et al., RFIC2006]
• Low-power blocks for 40-Gb/s wireline and fiber-optic transceivers in CMOS
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Decision Circuit Block DiagramDecision Circuit Block Diagram
• Two latches in Master-Slave configuration
• Data and clock amplifiers as TIAs
• Output driver buffers to 50Ω
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Conventional LatchConventional Latch
• Conventional CML latch requires 3 vertically stacked transistors
• Standard 1.2V supply in 90nm
• VDS too low for 40 Gb/s speed
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Previous WorkPrevious WorkTo operate from lower power supply (<1.2V)
Transformer coupling for clock-to-data path [Kehrer, et al., CSICS2004]
-> Not broadband due to transformer
Remove current sources [Kanda, et al., ISSCC2005]
-> Not sufficient for 40Gb/s operation
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Proposed LatchProposed Latch
• Bias at peak-fT current density
IBIAS=Ipeak-fT/2=0.15mA/μm
• High-VT devices on clock path
• Low-VT devices on data path
• For IBIAS=4.5mA and RL=40Ω:
ΔV=9mAx40Ω=360mV
• Total power consumption:
10.8 mW/latch
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Retiming DFF – SchematicRetiming DFF – Schematic
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Retiming DFF – SchematicRetiming DFF – Schematic
• Clock must fully switch M1/M2
• VDS,M7/8 swings as
low as VT (M1/M2)
• Use high-VT for M1/M2
• VDS,M7/8=VDD-ΔVswing=VT=0.34V
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TIA Design MethodologyTIA Design Methodology
• Bias at min noise current density 0.15 mA/μm [Dickson, et al., JSSC Aug 2006]
• p-MOS active load to increase gain at
low VDD
• Feedback inductor LF resonates out the
capacitance at the TIA node
• LF=500pH designed with two top metals
for minimum footprint to obtain high SRF
T
RZ FO
1
Fdsds
m
Rgg
gT
121
1
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TIA scaling to 65-nmTIA scaling to 65-nmCMOS TIA BW3dB=28GHz @ 3mA
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Fabrication and measurement Fabrication and measurement results of decision circuitresults of decision circuit
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P=130mW @ VDD=1.2V
Area=600x800μm2
Circuit fabricated in two different foundries
TIA DFF DRIVER
CLOCKTREE
Decision Circuit – Die PhotoDecision Circuit – Die Photo
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Retiming DFF – Test SetupRetiming DFF – Test Setup
• 40-Gb/s signal generated from 4x10Gb/s streams• Solid lines Data signals• Dashed lines Clock signals
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Measurements at 30Gb/sMeasurements at 30Gb/s
FCLK=30GHz, Data Rate=30Gb/s, Trise=7ps
JitterRMS,input=1.7ps JitterRMS,output=0.5ps
Single-ended input with other input terminated to 50Ω
Jitter from setup not de-embedded
Input (top) Output (Bottom)
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Measurements at 30Gb/s vs VMeasurements at 30Gb/s vs VDDDD, T, T
JitterRMS,input=1.7ps JitterRMS,input=1.4ps
JitterRMS,output=0.7ps JitterRMS,output=1.0ps
Input (top) Output (Bottom)
VDD=1V, T=25oC VDD=1.2V, T=100oC
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Measurements at 37Gb/s and 40Gb/sMeasurements at 37Gb/s and 40Gb/s
JitterRMS,input=1.292ps JitterRMS,input=1.403ps
JitterRMS,output=1.149ps JitterRMS,output=1.396ps
Input (top) Output (Bottom)
37Gb/s @ 1.2V 40Gb/s @ 1.5V
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Measurements at 40Gb/s and 1.5VMeasurements at 40Gb/s and 1.5V
• Error-free 508-bit pattern• Input (top), output (bottom)
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Comparison of high-speed latchesComparison of high-speed latches
Ref Technology Rate (Gb/s)
Supply (V)
PLATCH (mW)
PDEC,CIRC (mW)
[3] 245-GHz InP HEMT 80 5.7 N/A 1200
[4] 250-GHz InP HBT 50 1.5 20 125
[8] 150-GHz SiGe BiCMOS 43 2.5 23 288
This work
120-GHz CMOS37
401.2
1.510.8
20130
240
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ConclusionConclusion
• 90-nm CMOS latch and retimer demonstrated at 37 Gb/s from 1.2 V and 40 Gb/s from 1.5 V supply
• p-MOS device for low-noise TIA on data and clock path
• Peak-fT bias and combination of low and high-VT devices
in latch allows for 40-Gb/s retiming
• 1.2-V operation at 40 Gb/s possible if clock path TIA replaced with a CML inverter chain with inductive peaking and source follower
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AcknowledgementsAcknowledgements
• Nortel Networks for funding support• STMicroelectronics and TSMC for chip
fabrication• ECTI, OIT and CFI for equipment• NIT for lab access• CMC for CAD tools
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Backup SlidesBackup Slides
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ffTT of LVT and HVT transistors of LVT and HVT transistors
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Measurements at 30Gb/s (min. input)Measurements at 30Gb/s (min. input)
• Input (top) – Output (bottom)
• 30Gb/s @ 1.2V and 60mV input (13-dB attenuation)
• Retiming with
JitterRMS,input=1.9ps
JitterRMS,output=1.7ps
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Measurements at 7.5Gb/s (Fclk/4)Measurements at 7.5Gb/s (Fclk/4)
• Input (bottom) – Output (top).
• 7.5Gb/s @ 1.2V• Retiming with• JitterRMS,input=4.2ps• JitterRMS,output=2.6ps