7.10 e 7.11
• Contadores com reset
• Contadores BCD, em anel e Johnson
Figure 7.26 A modulo-6 counter with synchronous reset
Enable
Q 0 Q 1
Q 2
D 0 D 1
D 2
Load
Clock
1
0
0
0
Clock
0 1 2 3 4 5 0 1
Clock
Count
Q 0
Q 1
Q 2
(a) Circuit
(b) Timing diagram
Figure 7.27 A modulo-6 counter with asynchronous reset
T Q
Q Clock
T Q
Q
T Q
Q
1 Q 0 Q 1 Q 2
(a) Circuit
Clock
Q 0
Q 1
Q 2
Count
(b) Timing diagram
0 1 2 3 4 5 0 1 2
Figure 7.28 A two-digit BCD counter
EnableQ0Q1Q2
D0D1D2
LoadClock
1000
Clock
Q30 D3
EnableQ0Q1Q2
D0D1D2
LoadClock
000
Q30 D3
BCD0
BCD1
Clear
Figure 7.29 Ring counter
D Q
Q
Clock
D Q
Q
D Q
Q
Start
Q 0 Q 1 Q n 1 ”
Clock
Q 0
Start
Two-bit up-counter
w 0 En
y 0
w 1
y 1 y 2 y 3
1
Q 1 Q 2 Q 3
2-to-4 decoder
Q 1 Q 0
(a) An n -bit ring counter
Clock
Clear
(b) A four-bit ring counter
D Q
Q
Clock
D Q
Q
D Q
Q
Start
Q 0 Q 1 Q n 1 ”
Clock
Q 0
Start
Two-bit up-counter
w 0 En
y 0
w 1
y 1 y 2 y 3
1
Q 1 Q 2 Q 3
2-to-4 decoder
Q 1 Q 0
(a) An n -bit ring counter
Clock
Clear
(b) A four-bit ring counter
yo y1 y2 y3
wow1 En
QoQ1Clk
Clear
Figure 7.30 Johnson counter
D Q
Q
Clock
D Q
Q
D Q
Q
Q 0 Q 1 Q n 1 –
Reset
Recommended
