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Area Efficient Full Subtractor Based
G. Hemanth Kumar1B.E
Department of ECE, SNS College
ABSTRACT A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much more smaller. Keyword: Full Subtractor, cmos, static 125nm, tanner, multisim, Xilinx, half subtractor I. INTRODUCTION a logic gate is a physical device implementing a Boolean expression that is, it performs a logicaldesign operation on one or more binary inputs and produces a single binary output. In digital circuit theory, combinational circuits which is also called as time independent logic is a type of digitis implemented by Boolean circuits in which the output is the pure function of the input. has reduced propagation delay and it has faster addition logicfull subtractor is a combinational logical designperforms subtraction of two binary bits, one is said to be minuend and other is subtrahend, borprevious adjacent lower is minuend bit. This circuit has three inputs and two outputs‘a’, ‘b’ and ‘c’, denote the minuend, subtrahend, and previous borrow, respectively. The outputsDifference and Borrow represent the differenceoutputs borrow, respectively. Subtractor and adders
International Journal of Trend in Scientific Research and Development (IJTSRD)
International Open Access Journal | www.ijtsrd.com
ISSN No: 2456 - 6470 | Volume - 2 | Issue – 6 | Sep
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Area Efficient Full Subtractor Based on Static CMOS Technology
Hemanth Kumar1, K. Gopi1, P. Gowtham1, G. Naveen BalajiB.E Student, 2Assistant Professor
SNS College of Technology, Coimbatore, Tamil Nadu
A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently
btractor which is and observing the
distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which
isting full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits
static CMOS, 25nm, tanner, multisim, Xilinx, half subtractor
physical device implementing a that is, it performs a logical
operation on one or more binary inputs and In digital circuit
theory, combinational circuits which is also called as time independent logic is a type of digital logic which
Boolean circuits in which the tput is the pure function of the input. has reduced
propagation delay and it has faster addition logic. A combinational logical design that
performs subtraction of two binary bits, one is said to be minuend and other is subtrahend, borrow of the previous adjacent lower is minuend bit. This
has three inputs and two outputs. The inputs the minuend, subtrahend, and
The outputs, represent the difference and
Subtractor and adders
are used in almost all integrated adders and subtractors are used for education purpose but in order check a ouput of the full subtractor a student has to connect multiple gatesrequired gate are integrated into a single chip .It will be easy to analyze the circuit very fastly and accurately. The Full subtractor constructed in this research paper is constructed in 125nm static CMOS technology. II. EXISTING SYSTEMA full Subtractor is a logic circuit build with two half subtractor. A half subtractor combinational logic area in which it performs basic binary subtraction. A half subtractor is a two bit logical circuit .A half subtractor is made multiple gates which performs very basic operations according to the connections made in the CMOS (Complementary Metal Oxide Semiconductor).Full subtractor is also a two bit logical three inputs and two output where ‘a’,considered to be inputs of the full subtractor whereas ‘difference’ and ‘borrow’ are the outputs of the the logical circuit. Gates used in the full subtractor are ‘xor’ gate, ‘and’ gate, ‘not’ gate. Generally gate are the building of the the combinational circuits .Gates are built using several numbers of transistor. law which states every six months number of the transistors used in a particular integrated circuit will be increased due to the technology enhancemenXOR gate is a combinational logic‘1’ output when the number of ‘1’XOR gate implements an exclusive or, that is, a ‘1’output results if one, and only one, ogate is ‘1’. If both inputs are ‘0’
Research and Development (IJTSRD)
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Oct 2018 Page: 1371
Static 125nm
Naveen Balaji2
Tamil Nadu, India
are used in almost all integrated circuits. as for now adders and subtractors are used for education purpose but in order check a ouput of the full subtractor a student has to connect multiple gates . If all the required gate are integrated into a single chip .It will be easy to analyze the circuit very fastly and accurately. The Full subtractor constructed in this research paper is constructed in 125nm static CMOS
EXISTING SYSTEM: ull Subtractor is a logic circuit build with two half
subtractor is a logic design in the combinational logic area in which it performs basic binary subtraction. A half subtractor is a two bit logical circuit .A half subtractor is made up of multiple gates which performs very basic operations according to the connections made in the CMOS (Complementary Metal Oxide Semiconductor).Full subtractor is also a two bit logical circuit. It consist of three inputs and two output where ‘a’, ’b’ and ‘c’ are considered to be inputs of the full subtractor whereas ‘difference’ and ‘borrow’ are the outputs of the the
Gates used in the full subtractor are ‘xor’ gate, ‘and’ gate, ‘not’ gate. Generally gate are the building blocks
he the combinational circuits .Gates are built using transistor. We know that Moore’s
law which states every six months number of the transistors used in a particular integrated circuit will be increased due to the technology enhancement. The XOR gate is a combinational logic gate that gives a ‘1’ output when the number of ‘1’ inputs is odd. An
gate implements an exclusive or, that is, a ‘1’ output results if one, and only one, of the inputs to the gate is ‘1’. If both inputs are ‘0’ or both are ‘1’, a ‘0’
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output results. In ‘and’ gate ,only multiplication operation can be done if the both input are same the output will be the same as the input and if the inputs are different then the output will ‘0’. In ‘not’ contains only one input and the output is the output of the input if the input is ‘1’ then the output will be ‘0’ vice versa.
Fig-1.1: Block diagram of Half Subtractor:
In fig 1.1 we can analyze that a half subtractor consist of two inputs ‘a’ and ‘b’ and output ‘difference’‘borrow
Fig-1.2: Logic diagram of Half Subtractor:
In fig 1.2 Gates like ‘xor’, ‘not’, and which are used to process the inputs and give the output. Each gate has a difference type of process algorithm based the connection given to the CMOSThe Boolean expression of the half subtractor is as follows
Difference = ab’ + ba’ Borrow = a. b
Fig-1.3: Truth Table of Half Subtractor:
In fig 1.3 is a truth table of the half subtractor which portrays the output of that logical circuit.
b
aHalf
Subtractor
U7NOT
U8
AND2
U9
XOR2
ab
a b Difference Borrow
0
0
0
01
1
1
1
0 0
0 0
1 1
1 0
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In ‘and’ gate ,only multiplication operation can be done if the both input are same the output will be the same as the input and if the inputs
. In ‘not’ gate, input and the output is the output of
the input if the input is ‘1’ then the output will be ‘0’
Subtractor:
In fig 1.1 we can analyze that a half subtractor consist of two inputs ‘a’ and ‘b’ and output ‘difference’ and
Logic diagram of Half Subtractor:
‘not’, and ‘and’ Gates which are used to process the inputs and give the output. Each gate has a difference type of process
connection given to the CMOS. The Boolean expression of the half subtractor is as
Truth Table of Half Subtractor:
In fig 1.3 is a truth table of the half subtractor which circuit. A half
subtractor is a basic arithmetic processor which perform only subtraction its only function is to deduce a single bit binary from the input III. FULL SUBTRACTORHalf subtractor logical design has a major which we do not have the space to providefor the subtraction in half subtractorSubtractor logic, we can actually make a Borroinput in the circuitry and could subtract it with other two inputs A and B. So, in the case ofCircuit we have three inputs, A which is minuend, B which is subtrahend and Borrow In. On the other handwe get two f output, Difference andsubtractor is basic combinatinal logic circuit which performs a single arithmetic function It consist of three input naming ‘a’, ‘b’, ‘c’ which takes the input and process the algorithm using multiple gates such as ‘xor’, ‘Comparison between currently existing full subtractand newly area efficient full subtractor
Fig2.1: Block diagram of Full Subtractor:
In fig 2.1 we can analyze that a fullof two inputs ‘a’, ‘b’, and ‘c whereas ‘difference’ and ‘borrow
Fig2.2: Logic Diagram of
When the inputs are given through the respective labels gates present the circuits will process the data and perform the arithmetic operation subtraction and produce the output difference and borrow
Difference
Borrow
Difference
Borrow
Borrow
ba
c
Full Subtractor
U1
XOR3
U2
AND2U4
AND2U5
AND2
U6NOT
abc
International Journal of Trend in Scientific Research and Development (IJTSRD) ISSN: 2456-6470
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subtractor is a basic arithmetic processor which perform only subtraction its only function is to deduce a single bit binary from the input
FULL SUBTRACTOR: logical design has a major flaw in
which we do not have the space to provide input bit ubtractor. In case of full
, we can actually make a Borrow in input in the circuitry and could subtract it with other two inputs A and B. So, in the case of Full Subtractor
we have three inputs, A which is minuend, B and Borrow In. On the other hand
Difference and Borrow. A full subtractor is basic combinatinal logic circuit which performs a single arithmetic function i.e. subtraction. It consist of three input naming ‘a’, ‘b’, ‘c’ which takes the input and process the algorithm using multiple gates such as ‘xor’, ‘and’ and ‘not’.
urrently existing full subtractor and newly area efficient full subtractor.
Block diagram of Full Subtractor:
at a full subtractor consist , and ‘c whereas output
Logic Diagram of Full Subtractor:
When the inputs are given through the respective labels gates present the circuits will process the data and perform the arithmetic operation subtraction and
difference and borrow
Difference
Borrow Subtractor
U1
XOR3
U3
OR3
Difference
Borrow
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Fig2.3: CMOS Design of Full Subtractor:
The above full subtractor is designed using static cmos algorithm under 125nm which is quite efficient and the results are same as the currently existing one
Fig2.4: Truth Table of Full Subtra
The above truth table is solved using the universal Boolean expression
Difference=((a&(~b)&(~c) )| ((~a)&b&(~c))|
~b)&c)| (a&b&c))
Borrow = ( (~(a) & b ) | ( b & c) | ( c & (~a) )) The above table used to serve the universal expression of a logic gate function. A logic gate truth table shows each possible input combination to the gate or circuit with the final output depending upon the combination of these inputs.
Difference Borrowa b c
0
0
1
10
0
1
1
0
0
1
10
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
1
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Full Subtractor:
The above full subtractor is designed using static cmos algorithm under 125nm which is quite efficient and the results are same as the currently existing one
Truth Table of Full Subtractor:
The above truth table is solved using the universal
((~a)&b&(~c))| ((~a)&((a&b&c))
Borrow = ( (~(a) & b ) | ( b & c) | ( c & (~a) ))
universal boolean A logic gate truth
table shows each possible input combination to the output depending upon
IV. RESULTS: B.1 OUTPUT:
Waveform of Logic design of
Waveform of CMOS design of
CONCLUSION: It has been observed from the simulation results that performance of adder architectures varies with various CMOS design. The output of these two Full Subtractors are same. The current of Carry Look Ahead adder is 125nm.If the fabrication size reduced to less than 100nm, performance varies and can be (CMOS) technology. From this research t
Borrow
0
1
1
1
0
0
0
1
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Waveform of Logic design of Full Subtractor:
Waveform of CMOS design of Full Subtractor:
It has been observed from the simulation results that ectures varies with various
The output of these two designs of are same. The current fabrication size
adder is 125nm.If the reduced to less than 100nm, the adder
varies and can be absorbed using static . From this research the (CMOS)
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can be achieved by operating point within 0.9v.research is very useful and more advantageous infuture microprocessor industries. REFERENCES 1. N. Weste and K. Eshraghian, --Principles of VLSI
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