1
K-Maps, Multi-level Circuits, K-Maps, Multi-level Circuits, Time ResponseTime ResponseToday:
• Reminder: Test #1, Thu 7-9pm• First Hour: K-map example, espressoK-map example, espresso
– Section 2.3 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Multi-Level Logic, All-NAND/NOR Circuits, Time Response
• Section 3.1 of Katz’s Textbook
– In-class Activity #2
2
Recap: K-mapsRecap: K-maps• A graphical way to express a truth table
• Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables
ABCD 00 01 11 10
00
01
11
10
A donut-like representation
!
1 1
1
3
Recap: K-mapsRecap: K-maps• A graphical way to express a truth table
• Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables
ABCD 00 01 11 10
00
01
11
10
1 1
1
The “Boolean Lasso”
expresses the uniting theorem
Remember: diagonally-adjacent
terms cannot be united
4
Recap: K-mapsRecap: K-maps• A graphical way to express a truth table
• Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables
ABCD 00 01 11 10
00
01
11
10
1 1
1
The bigger the lasso, the
smaller the result
DCA
DCBA
5
K-map Method SummaryK-map Method Summary
• Step 1 — Group 1s starting with the largest cube, then next largest, etc.
• Step 2 — If 1 is covered by only one cube, that cube is an essential covering
• Step 3 — Use largest covering for 1s not covered by essential coverings
• Step 4 — Include singletons
• Step 5 — Translate to Boolean formStep 5 — Translate to Boolean form
6
Example Example
• A circuit that compares two 2-bit numbers
Comparator
AB
CD
AB < CD
AB = CD
AB > CD
4 input bits 3 output bits
7
Truth TableTruth TableA B C D = < >0 0 0 0 0 1 1 0 1 10 1 0 0 0 1 1 0 1 11 0 0 0 0 1 1 0 1 11 1 0 0 0 1 1 0 1 1
AB is one two-bit number and CD is the other
AB is held constant and AB is held constant and compared with the 4 compared with the 4 possible values of CDpossible values of CD
Notice the three outcomes ( = < > ) are mutually exclusive
1 0 00 1 00 1 00 1 00 0 11 0 00 1 00 1 00 0 10 0 11 0 00 1 00 0 10 0 10 0 11 0 0
8
Fill in the K-mapsFill in the K-mapsAB
CD 00 01 11 1000 1 0 0 001 0 1 0 011 0 0 1 010 0 0 0 1
ABCD 00 01 11 10
00 0 0 0 001 1 0 0 011 1 1 0 110 1 1 0 0
ABCD 00 01 11 10
00 0 1 1 101 0 0 1 111 0 0 0 010 0 0 1 0
=
< >
9
The “=“ Function:SOPThe “=“ Function:SOPAB
CD 00 01 11 1000 1 0 0 001 0 1 0 011 0 0 1 010 0 0 0 1
=
No simpler SOP form!
Makes sense: XOR-gates!
No simpler SOP form!
Makes sense: XOR-gates!
““=“=“ = A’B’C’D’ + A’BC’D + ABCD + AB’CD’
10
The “=“ Function: POSThe “=“ Function: POS
ABCD 00 01 11 10
00 1 0 0 001 0 1 0 011 0 0 1 010 0 0 0 1
=
““=“=“ = (A C' + A' C + B D' + B' D)'
= (A' + C)(A + C')(B' + D)(B + D')
11
The “<“ Function: SOPThe “<“ Function: SOP
ABCD 00 01 11 10
00 0 0 0 001 1 0 0 011 1 1 0 110 1 1 0 0
<
““<“<“ = A’C + B’ C D + A' B‘D
12
The “<“ Function: POSThe “<“ Function: POS
ABCD 00 01 11 10
00 0 0 0 001 1 0 0 011 1 1 0 110 1 1 0 0
<
““<“<“ = (A C' + B C' + C' D' + A B +A D')'
= (A' + C)(B' + C)(C + D)(A' + B')(A' + D)
13
The “>” Function: SOPThe “>” Function: SOP
ABCD 00 01 11 10
00 0 1 1 101 0 0 1 111 0 0 0 010 0 0 1 0
““>“>“ = AC’ + ABD’ + BC' D'
>
14
The “>” Function: POSThe “>” Function: POS
ABCD 00 01 11 10
00 0 1 1 101 0 0 1 111 0 0 0 010 0 0 1 0
>
““>”>” = (A' C + A' D + C D + A' B' +B' C)'
= (A + C')(A + D')(C' + D')(A + B)(B + C')
15
Simplifying Larger Functions
• Use Logic Minimization software.
• Example: espresso – Public domain software
– Easy to use, but not a toy!
– Used for real designs.
• Often the cost of a circuit depends on the number of
– The number of terms
– Number of literals.
• espressoespresso tries to achieve fewer different termsfewer different terms.
16
espresso Exampleespresso Example
a2 a1 a0 b2 b1 b0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 x x x
1 1 0 x x x
1 1 1 x x x
Minimize the following 3-input, 3-output function:
3 easy Steps:
1. Translate the given function into the espresso file format.
2. Run espresso
3. The espresso output file has the simplified function!
17
Input to espresso.i 3
.o 3
.p 8
000 001
001 010
010 011
011 100
100 000
101 ---
110 ---
111 ---
.e
- # input variables
- # output variables
- # table rows (optional)
- inputs, outputs, ...
- dash denotes don’t care
- marks the end (optional)
a2 a1 a0 b2 b1 b0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 x x x
1 1 0 x x x
1 1 1 x x x
18
espresso Output Output .i 3
.o 3
.p 40-0 001-11 100-01 010-10 010.e
• This looks familiar but is new.
• Output Boolean expressionsOutput Boolean expressions
– For each column, look for the rows that are 1, the AND terms
– Then OR the AND terms
– e.g., AND term 0-0 is a2a0
b2 = a1 a0
b1 = a1' a0 + a1 a0'
b0 = a2' a0'
b2 = a1 a0
b1 = a1' a0 + a1 a0'
b0 = a2' a0'
These dashes denote absent
variables
19
ComparisonComparison• mintermminterm expression
b2 = a2' a1 a0
b1 = a2' a1' a0 + a2' a1 a0'
b0 = a2' a1' a0' + a2' a1 a0'
b2 = a2' a1 a0
b1 = a2' a1' a0 + a2' a1 a0'
b0 = a2' a1' a0' + a2' a1 a0'
• espressoespresso expression
b2 = a1 a0
b1 = a1' a0 + a1 a0'
b0 = a2' a0'
b2 = a1 a0
b1 = a1' a0 + a1 a0'
b0 = a2' a0'
• 4 different terms, used 4 times. 8 literals.
• 1 2-input OR and 4 2-input ANDs
• Simpler
• 4 different terms, used 5 times. 12 literals.
• 2 2-input ORs;• 4 3-input ANDs
We’ll learn to use espresso during the next studio!
20
Do Activity #1 NowDo Activity #1 Now• Reference:
–Section 2.3 of Katz’s Textbook
–More K-maps
–Translating to/from espresso format
21
Multilevel LogicMultilevel Logic
• Boolean networks can have space-time tradeoffs.
• Smaller slower. Bigger faster.
• If you factor out common expressions, you may get a form with fewer gates, but with more than 2 levels of gates multilevelmultilevel
• Boolean networks can have space-time tradeoffs.
• Smaller slower. Bigger faster.
• If you factor out common expressions, you may get a form with fewer gates, but with more than 2 levels of gates multilevelmultilevel
22
Multilevel Circuits Multilevel Circuits Reduced sum of products form: X = A D F + A E F + B D F + B E F + C D F + C E F + G
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires)
1
2
3
4
5
6
7
A
A
B
B
C
C D
D
D
E
E
E
F
F
F
F
F
F
G
x
1
2 3 4
A B C
D E
F G
x
Factored form: X = (A + B + C) (D + E) F + G
1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
23
NAND-NAND networksNAND-NAND networks
• SOP expressions have ANDs and ORs.
• You can convert it to use all NANDs (or all NORs).
• Necessary facts:
– DeMorgan's theorem
– Many logic chips have outputs that are active lowactive low
– Active low outputs are indicated by the presence of a bubblebubble
24
Conversion of FormsConversion of Forms
NOR NANDDeMorgan's Law: (A + B)' = A' • B'; (A • B)' = A' + B'
NOR is the same as AND with complemented inputs NAND is the same as OR with complemented inputs
OR ANDWritten differently: A + B = (A' • B')'; (A • B) = (A' + B')'
OR is the same as NAND with complemented inputs AND is the same as NOR with complemented inputs
25
Equivalent FormsEquivalent Forms
A A B B ºOR OR OR
A A B B ºNand Nand NAND
A A B B ºAND AND AND
A A B B ºNOR NOR NOR
26
Conversion Between FormsConversion Between Forms
• It is possible to convert from networks with ANDs and ORs to networks with NANDs and NORs by introducing the appropriate inversions (bubblesbubbles)
• To preserve logic levels, bubblesbubbles must be introduced in pairs
27
(1) A B
C D
(3) A B
C D
NAND
NAND
NAND
A B
C D
AND
AND
OR
(2)
A B
C D
NAND
NAND
NAND
(4)
AND/OR to NAND/NANDAND/OR to NAND/NAND
28
AND/OR to NAND/NANDAND/OR to NAND/NAND
• Used bubble-pushingbubble-pushing to simultaneously add or remove 2 bubbles to an output and associated input.
• Can also just use Boolean algebra:
• Can also convert to NOR/NOR form.
f = A B + C D (AND-OR)
= ( (A B)' (C D)' )' (NAND-NAND)
revisitedrevisited
29
Time Response TermsTime Response TermsTerms:Terms:
gate delaygate delay — time for change at input to cause a change at output- minimum delay vs. typical/nominal delay vs. maximum delay.- careful designers design for the worst case!
propagation delaypropagation delay — same as gate delay
rise timerise time — time for output to transition from low to high voltage
fall timefall time — time for output to transition from high to low voltage
30
Time Response in Time Response in Combinational NetworksCombinational Networks
• emphasis on timing behavior of circuits
• waveforms used to visualize what is happening
• use simulation to create these waveforms
• momentary changes of signals at the outputs: hazardshazards
– can be useful — pulse shaping circuits
– can be a problem — glitches: glitches: incorrect circuit operation
31
Time Response ExampleTime Response ExamplePulse Shaping CircuitPulse Shaping CircuitPulse Shaping CircuitPulse Shaping Circuit
What is the value of F if
A = 0?
What is the value of F if
A = 0?
What is the value of F if
A = 1?
What is the value of F if
A = 1?
3 gate delays
D remains high forthree gate delays after
A changes from low to highF is not always 0!
What happens when A changes from 0 to 1 and back again?
What happens when A changes from 0 to 1 and back again?
32
Do Activity #2 NowDo Activity #2 NowDue: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:• Bring Randy Katz Textbook
• Required Reading:– Sec 4.1 of Katz
• This reading is necessary for getting points in the Studio Activity!