1
Introduction
ELG 6158 Digital Systems ArchitectureMiodrag Bolic
Pipelining• Basic pipeline performance and effects of hazards
on performance• Pipelined version of the MIPS processor• Pipeline hazards
– Structural hazards– Data hazards – Control hazards– Drawing pipeline diagrams to identify hazards and stalls
add $5, $7, $1add $6, $3, $5, sw $6, 200($0)
• Show what parts of the datapath are active and what are the values of control signals and buses for various instruction
Pipelined datapath
Memory HierarchyConcepts of memory hierarchies
– Memory close to the processor is faster, smaller, and more expensive– Take advantage of locality
• Basics of caches– How to access a cache, hit or miss– Determining the size of the byte offset, index, and tags– Determining total number of bits in the cache– Drawing diagrams of different types of caches
• Improving cache performance– Increasing the size of the cache– Increasing the block size– Increasing associativity– Adding a second level cache
Memory Hierarchies
• Virtual Memory– Benefits of virtual memory– Address tranlation processes:
virtual address -> physical address– Page tables– Translation lookaside buffers– Handling page faults
Vector processors• Vector processor architecture• Basic vector processing program• Execution time with and without
chaining for the given architecture
Superscalar processor
• Data dependencies in the program• Superscalar architecture• Understanding terminology: dispatch buffer,
reorder buffer• Execution of programs on superscalar
processors• Show the pipeline activity for the given program
on the given processor
VLIW processor
• VLIW architecture• The role of the compiler • Concept of loop
unrolling and software pipelining
• The example of scheduling of the instructions to the functional units
Dynamic Interconnection Networks
• Properties– Network latency – Hardware complexity– Blocking/Nonblocking
• Switches– Permutations and legitimate states
• Multistage Interconnection networks– Omega network:
» topology, » number of switches, stages and permutations, » routing protocol
• Crossbar
Static Interconnection Networks
• Network properties– Node degree d– Diameter D– Bisection width
• Complete• Star• Tree• Linear array• Ring• Mesh• Torus• Hypercube
– routing protocol
• k-ary n-cubes
• To prepare for dynamic and static interconnection networks use
– slides, – assignment and – text book Chapter 2 and
chapter 3 only text that goes with tables 3.1 and 3.2.
Shared Memory Systems
• Cache coherence policies– Snooping protocols– Directory protocols
12
System-on-chip architectures
32-BitNiosProcessor
ROM(with Monitor)
Address (32)
Read
Write
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
Avalon B
us
Nios Processor Tri-StateBridge
SDRAMController
Tri-StateBridge
Compact Flash PIOs
Button PIO7-SegmentLED PIOLCD PIOLED PIO
General Purpose Timer
Periodic Timer
UART
Reconfig PIO
13
14
15
16
17