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Improving Design Quality by Managing Process Variability
ISQED ’09
San Jose, CA
Terry Ma
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CONFIDENTIAL INFORMATIONThe following material is being disclosed to you pursuant to a non-disclosure agreement between you or your employer and Synopsys. Information disclosed in this presentation may be used only as permitted under such an agreement.
LEGAL NOTICEInformation contained in this presentation reflects Synopsys plans as of the date of this presentation. Such plans are subject to completion and are subject to change. Products may be offered and purchased only pursuant to an authorized quote and purchase order. Synopsys is not obligated to develop the software with the features and functionality discussed in the materials.
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Design-Centric Yield Management
• Summary
Outline
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Moore’s Scaling
Source: IMEC
90nm
65nm
45nm
32nm
22nm
<15nm
Stress engineering implemented at 65nm enables continued scaling
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What exactly does stress do?
Stress Band Structure
Mobility
Vt
Leakage
Lattice distortion
Gate
SiGe
Si
NMOS
NiSiSi3N4
35nm
NiSi
Si3N4 stress cap
PMOSSiGe
SiGe
NiSi
1.2nm
Unlike humans, transistors perform better under stress!
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If you are a designer….
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Unfortunately, stress is everywhere…
Each object (diffusion, poly, contact, well edge, …) contributes to stress!
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If you look inside a standard cell…
As much as 25% variation in current across a standard cell
0.95 0.8
0.95 0.86 0.980.95 0.86 1.03
0.8 0.74
0.740.78 0.8
0.74 0.78 0.95
P
N
0
5
10
15
20
25
1 2 3 4 5 6 7 8
Idlin
de
gra
da
tio
n
0
5
10
15
20
25
30
1 2 3 4 5 6 7 8Transistor
Idlin
de
gra
da
tio
n
P-Channel
N-Channel
Transistor Position
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Cell context can become a problem too….
Proximity Effect Typical Ambit
Lithography ~ 1um
Mechanical Stress ~ 2-3 um
Well Proximity ~ 1-2 um
Adjacent cells
Cell under analysis
Ambit size
3.7x1.4 2.6x1.0 1.8x0.7 1.3x0.55.3x2.0 0.91x0.35Gate size (um2)32nm0.18mm 0.13mm 90nm 65nm 45nmTechnology
Minimum gate width for 45nm node is ~0.5 um
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Design Manufacturing
Co
st
Slip!Slip!
Time
Systems
Oops!Oops!
The price to pay….
Design Tapeout Production
Co
st/C
han
ge
1X
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Design-Centric Yield Management
• Summary
Outline
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Sources of Layout Proximity Variation
Cap layer
SiGe S/D
Gate Spacer
STI
X
Y
Z
Litho Proximity Mechanical Stress/Strain Well Proximity
Effect Physical Variation Electrical Variation
Lithographic Proximity
Shape of poly gate, diffusion region Transistor L, W
Mechanical Stress
Mechanical strain, defect diffusion
Mobility, Vth
Well Proximity Channel Doping Vth, Body effect
Electrical Variation Circuit Variation
Modeling of electrical variation (caused by physical variation) to account for proximity effects is crucial for design
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Lithographic Proximity Variation• Sub-wavelength lithography physical shape variation
Physical shape variation Electrical variation
• CD Variation• Corner Rounding
• Drive Current• Leakage• Capacitance• Delay
Transistor Drain Current
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Stress-Induced Ion Variation @ 45nm
Layout A
W=100nm
P2P=120nm
#1 #3 #5
Layout C
#1 #2 #3 #4 #5
1 2 3 4 50%
5%
10%
15%
20%
25%
PMOS Ion Sensitivity
ABC
Transistor Number
Ion
Var
iati
on
, %
~25% Ion variation even for simple layouts!
(Transistors in Layout A are used for Ion reference)
Layout B
#1 #2 #3 #4 #5
W=100nm
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• Implant atoms bounce off of photoresist
• Extra dopant in channel region changes Vth, body effect
Well Proximity Effect
• Depends strongly on well / isolation layouts
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DL
SA
P2P
SDP
WA
H
SDP
jogs
DB
DT
DB
Complex Layout Effects
• Jogs (L, H, U, Z, … shapes)• SA (length of diffusion)• DL (longitudinal diffusion spacing)• DT (transverse diffusion spacing)• SDP (active-to-dummy poly)• P2P (poly space)• WA (DSL and WPE)• DB (distance to boundary)
• Poly spacing variation still exists, despite effort to follow restrictive design rules (RDR) – poly-on-grid
• Active diffusion jogs and corner rounding remain pervasive
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Added Design Challenges
250nm
180nm
130nm
90nm
65nm
350nm
45nm
32nm22nm
Timing Closure!
PowerVerification
Signal Integrity
Power!Verification!
Yield Power!!Verification!!
Clocks
Power!!!Verification!!!
Yield!Power!!!
Verification!!!!Yield!!
Variability
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Yield Management for Design
• Summary
Outline
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How to bridge process and design?
Process
Design
Transistor
Si STI STI
Length of Diffusion
Lszz
sxx
syy
W
Layout
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Designer’s Care-about
• Everything starts with Spice
Annotated Spice Netlist
Accurate Cell LibraryCharacterization
SpiceSimulations
Critical Path Analysis
Sign-off
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From Physics to Compact Model
)( itype G
typexx
totalxx G
i
Compact ModelCompact Model
Physical ModelingPhysical Modeling
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From Layout to Spice Instance Parameters
Layout
Litho
Stress
WPE
Others
Geo
met
ry P
roce
ssin
g
Phy
sics
-bas
ed C
ompa
ct M
odel
s
(m/m
ref, D
Vth
, D
L, D
W,
…)
Back-annotated
Spice Instance
Parameters(MULU0, DELVT0, L, W, …)
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Design-Centric Yield Management
• Summary
Outline
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Litho Contour
totalz
totaly
totalx zzyyxx
kkk 0/
Stresssxx
syy
szz
Instance Params Determination
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.8 1.0
Vds/Vdd
Ids
/ I
ds
at
Vdd
0.6Vdd
0.4Vdd
0.2Vdd
Vgs
Simulated with MULU0 and DELVTO
Measured data
Seismos LX: Stress to Electrical
Weq
Leq
Seismos CX: Contour to Electrical
Layout
Si Calibrated Stress Model
Visualization
Annotated SPICE Netlist
HSPICE, HSIM, NanoSim
Design-Centric Process Variability Tools
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Library/Cell Design Flow Drop-in
Schematic
Layout
PhysicalVerification
Device & RC Extraction
Annotated Netlist
Spice Simulation
Instance Parameters: meff, Vth, Leff,
Weff
Seismos
Stress Model
Tech File
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Model-Based Approach Accuracy
0.8 0.9 1 1.1 1.2 1.30.8
0.9
1
1.1
1.2
1.3Small W
Silicon Idlin Variation
Mod
eled
Idlin
Var
iatio
n
0.8 0.9 1 1.1 1.2 1.30.8
0.9
1
1.1
1.2
1.3 Large W
Silicon Idlin Variation
Mod
eled
Idlin
Var
iatio
n
Desirable45o target
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Handling tricky layout…
Compressive STIstress pushesSide of Diffusion edge
Leads to Tensile longitudinalStress at bottom edge
In a complex layout, physics-based approach can handle very well the changes
in stress behavior at diffusion corner
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Visualizing Mobility Variation Across a Cell
strongweak
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Doing What-if Analysis
• Integrated with IC-Workbench• Layout editing, with instant in-place mobility analysis
Original
nmos
pmos
• weaken nmos• enhance pmos
Shrink Diff
• enhance nmos• weaken pmos
dummy
dummy
Add Dummy
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Device and Timing Characteristics
• Back-annotated netlist is used for Spice simulations
% Change ( dense v. sparse)
Params NMOS PMOS
Ion 6.0% 16.2%
Ioff 7.0% 16.9%
Delay -5.5% (fall) -13.9% (rise)
SiGe + STI
3-stage ring oscillator
Dense Sparse
(sparse) (dense)
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Analyzing Cell Context Effects
• Context dependent timing variation can be evaluated to determine • Sensitivity• Distribution• Derating factor, …
Context Dependent Delay Variation
BU
FX
4
BU
FX
4
BU
F
BU
F
NA
ND
2
NA
ND
2
BU
F
BU
FX
2
NA
ND
2
Fill
er4
Fill
er4
NA
ND
2
Fill
er2
Fill
er2
NA
ND
2
(a) (b) (c) (d) (e)
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• Context analysis reveals timing variations, and best and worst case neighbors
Example: 40nm 24x Inverter
6.45
E-12
6.47
E-12
6.48
E-12
6.50
E-12
6.51
E-12
6.53
E-12
6.55
E-12
6.56
E-12
0
5
10
15
20
25
- ( )tdelay fall s
Fre
qu
ency
02468
101214161820
- ( )tdelay rise s
Fre
qu
ency
100 Random Contexts – 2 Timing Arcs
worstworstbest best
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Layout VariationTypical Ion variation
range
Typical Vth
variation range
Length of diffusion (LOD) (SiGe or STI) ~30% ~50mV
Spacing to adjacent diffusion ~5% ~15mV
Active diffusion corners ~5% ~15mV
Poly spacing ~15% ~30mV
Poly corner rounding ~5% ~20mV
Well boundary (WPE)/ Dual stress liner (DSL) ~15% ~90mV
Contact to gate distance ~3% ~10mV
Proximity Variation Summary
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Design-Centric Yield Exploration
• Summary
Outline
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Statistics and DataMining
Data Visualization / Correlation
Yield Management System
Measurement and Inspection
Wafer History
Equip. History
FAB
ATPG Tests
DFT Diagnosis Fail Classification
Arrays Tests
Parametric Test Results
Functional Test Results
TEST
DRC / CAA
Parasitics
STA
LCC / CMP
EDA
Physical Design Data
Characterization Results
Test Engineer
Program Fix
Layout Engineer
Design Fix
Process Engineer
Process Fix
FA Engineer
Faster FA
New Paradigm in Yield Management
Stress
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Low Yield Lot
Cell Fail By Test
Failing Cell Map
Spatial Trends
Failing Cells and Nets
Failing NetsOn Layout
Physical FA50% Accurate
2-3 Days
2-3 Weeks
Yield Explorer Automated Flow
Multi-Tool Manual Flow
Low Yield Lot
Physical FA>90% Accurate
• Single Data Bank for yield relevant data from Design, Fab and Test
• An order of magnitude faster systematic failure localization
Design-Centric Yield Management
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• Introduction
• Sources of Process Variability
• Modeling Process Variability
• Design-Centric Process Variability Analysis
• Design-Centric Yield Exploration
• Summary
Outline
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• Stress engineering added to boost transistor performance at 65nm and below increases process variability
• Interactions between design features and physical processes result in systematic defects that can degrade design quality and yield in manufacturing
• Design modification made after tapeout and in manufacturing cannot fix everything and is costly
• For 45nm and below, design quality and yield can be improved by properly managing process variability
Summary
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Predictable Success