1
COMP541
Memories II:DRAMs
Montek Singh
Oct 20, 2014
Topics Last class:
Read-Only Memories (ROMs)Static Random-Access Memory (SRAM)
Today:Dynamic Random-Access Memory (DRAM)
2
Dynamic RAM (DRAM) Very “lightweight” bit-level memory
a single capacitor holds charge (= value)no charge = ‘0’
a single transistor acts as gateWrite: connect switch & add charge to store a ‘1’…… then disconnect switchRead: read by connecting switch
3
DRAM Bit Cell Very lightweight
contrast with SRAMDRAM cell consists of one transistor and one
capacitor!SRAM cell has at least 6 transistors
4
wordline
bitline bitlinewordline
bitline
DRAM bit cell: SRAM bit cell:
Hydraulic Analogy: Writing
5
StorageFull (1)
Empty (0)Pump fills tank to 1
value
Pump drains tank to 0 value
Hydraulic Analogy: Reading
6
Tank had a 1 value – raises
water level
Outside water begins at
intermediate level (black wavy line)
Tank had a 0 value – lowers
water level
DRAM Characteristics Destructive Read
When cell is read, charge is (partially) removedMust be restored after each read!
RefreshAlso, there’s steady leakage
and no transistor to constantly automatically replenishCharge must be restored periodically
7
DRAM Logical Diagram
8
Core memory storageControl circuitry
DRAM Read Signaling Since DRAM is often on a separate chip
number of pins available can be a limitation lower pin count by using same pins for row and
column addresses
9
Delay until data
available
DRAM Write Signaling
10
DRAM Refresh Many strategies
refresh circuits on chiphere a simple row counter: reads and writes back
11
Refresh Timing Say, need to refresh every 64ms Distributed refresh
Spread refresh out evenly over 64msSay on a DRAM with 8192 rows (213),
refresh window for each row = 64ms/8192=7.8 usAssume: time to refresh each row is 30nsTotal time spent in refresh = 30ns * 8192 = 0.25ms
but spread out
Burst refreshSame 0.25ms, but all at onceMay not be good in a computer system
an unlucky instruction will have to wait long…
Refresh takes low % of total time0.25 ms / 64 ms = less than 4% 12
Bidirectional Lines Another optimization for reducing pins:
Many chips have one set of data pinssame pins used as data input for write operationssame pins used as data output for read operationsotherwise float them (i.e., tri-state)
Makes sense because don’t need both read/write data at once
13
Synchronous DRAM (SDRAM) Has a clock Common type in PCs late-90s
Typical DRAMs still synchronous Multiple banks Pipelined
Start read in one bank after anotherCome back and read the resulting values one after
another
14
Modes of DRAM operation DRAMs optimized to read & write entire blocks
or at least a few consecutive locations
Several different modesnormal/basic modeNibble or Burst ModeFast Page ModeExtended Data Out (EDO) Mode
15
Basic Mode of Operation
Slowest mode Uses only single row and column address Row access is slow (60-70ns) compared to column access (5-
10ns) Leads to three techniques for DRAM speed improvement
Getting more bits out of DRAM on one access given timing constraints
Pipelining the various operations to minimize total time Segmenting the data in such a way that some operations are
eliminated for a given set of accesses 16
Row ColumnAddress
RAS
CAS
DataData
17
Nibble (or Burst) Mode
Several consecutive columns are accessed Only first column address is explicitly specified Rest are internally generated using a counter
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS
RA CAD1 D2 D3 D4
18
Fast Page Mode
Accesses arbitrary columns within same row Static column mode is similar
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS
RA CA1 CA2 CA3 CA4D1 D2 D3 D4
19
EDO Mode
Arbitrary column addresses Pipelined EDO = Extended Data Out Has other modes like “burst EDO”, which allows
reading of a fixed number of bytes starting with each specified column address
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS CAS CAS CAS
RA CA1 CA2 CA3 CA4 CA5 CA6 CA7D1 D2 D3 D4 D5 D6
DDR DRAM Double Data Rate (DDR) SDRAM
Transfers data on both edges of the clockCurrently popularYou get two memory accesses per clock cycle!
20
RAMBUS DRAM (RDRAM) Another attempt to alleviate pin limits Many (16-32) banks per chip Made to be read/written in packets Up to 1200MHz bus speeds
XDR – 8 bits per clock, 16-bit wide bus, 6.4GBBut DDR doing very well also
Quite expensivealmost disappeared from consumer PCsstill present in servers and specialized chips
21
DRAM Controllers Very common to have a separate chip/module
that controls memoryHandles banksHandles refresh
Multiplexes column and row addressesRAS and CAS timing
Called “Northbridge” on PC chip set
22
Conclusions RAMs with different characteristics
For different purposes Static RAM
Simple to use, small, expensiveFast, used for cache
Dynamic RAMComplex to interface, largest, cheapNeeds periodic refresh
23
Links Ram Guides (not very technical)
http://arstechnica.com/paedia/storage.html Your Nexys 3 / Nexys 4 board manual
24
Recommended