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Family Highlights Spartan (5.0 Volt) family introduced in Jan. 98
— Fabricated on advanced 0.5µ process technology
SpartanXL (3.3 Volt) family introduced in Nov. 98— Fabricated on advanced 0.35µ process technology— Power management features— Higher performance over Spartan (5.0 Volt)— Entire family of 5 devices under $7.50
Both families offer:— SRAM technology (re-programmable)— Leverage industry standard XC4000 architecture— Lowest cost FPGA families with memory (SelectRAM)— Extensive core support— Broadest density/package/temperature/speed offering
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Spartan Series Roadmap
1998 1999 2000
Spartan
$395
per 5K gates
Pric
e
SpartanXL
$249
per 5K gates
Spartan-II
up to100K gates
0.5 3LMHigher Density + More Features
Without CompromisesPricing competitive with ASICsHigh PerformanceOn-chip SelectRAMTM
PCI LogiCORE + AllianceCORE
3.3 Volt
5 Volt
*Prices are for >100K units, slowest speed, lowest cost package
0.25 5LM
SpartanNext Generation
up to200K gates
1.8 Volt0.18
Higher SpeedLower Power
Power Down Mode
0.35 5LM
2.5 Volt
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Spartan/XL Product Matrix5 Volt XCS05 XCS10 XCS20 XCS30 XCS40
3.3 Volt XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL
System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K
Logic Cells 238 466 950 1368 1862
Max Logic Gates 3,000 5,000 10,000 13,000 20,000
Flip-Flops 360 616 1120 1536 2016
Max RAM bits 3,200 6,272 12,800 18,432 25,088
Max I/O 77 112 160 192 224
Packages PC84 PC84
VQ100 VQ100 VQ100 VQ100
TQ144 TQ144 TQ144
CS144 CS144
PQ208 PQ208 PQ208
PQ240 PQ240
BG256 BG256
CS280 CS280CS packages available only in SpartanXL family
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Chip Scale Packages for SpartanXL
XCS10XL and XCS20XL in CS144
XCS30XL and XCS40XL in CS280
0.8 mm pitch solder ball spacing
Higher in I/O count and smaller than any competitive offering in the industry
Reduces board space
Adds 19 more I/Os to the XCS40XL
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XC4000 Spartan SpartanXL
M0 MODE: M0: Master Serial, Master Serial, Slave Serial Slave Serial
M1 Don’t Connect M1: Express
M2 Don’t Connect Powerdown
Mode Pins
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XCS20XL in PQ208 Adds 8 VCCs vs. XCS20
3V XCS20XL adds 8 VCC pins that are not available in the 5V XCS20— Pads weren’t available on XCS20 die— Extra VCC pins are more important at higher speed and
lower VCC— Bonded out to same locations as in XCS30/XL— P18, P33, P71, P86, P121, P140, P173, P192— Currently NCs on 5V XCS20
Don’t connect these to GND or other signals now that they are VCC!
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Spartan Speed Grades Spartan speed grades increment from an arbitrary number
(“-3”, “-4”)— No correspondence to a physical delay
Former system of using LUT delay no longer applicable at ~1ns
LUT alone doesnot reflect overallclock speed or routing speed
New
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Perf
orm
ance
5200 4000E Spartan, 5V SpartanXL, 3V
E-1
E-2
Spartan -4
Spartan -3
-4
-3
SpartanXL-5
SpartanXL-4PCI
Speed Grades
Higher speed grade = higher performance
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Device BUFGP BUFGS BUFGLS BUFGE
Spartan 4 4 0 0
SpartanXL 0 0 8 0
XC4000X 0 0 8 8
General recommendation: Design with BUFG
Software chooses appropriate specific buffer
BUFGP/BUFGS will convert to BUFGLS automatically for SpartanXL target
Global Clock Buffers
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CLB Latch
CLB flip-flops can be used as latches
LD, etc. components in SpartanXL library
Simplifies use of HDL synthesis
Similar to XC4000X
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Interconnect
Carry only propagates upward— Significantly higher speed
– Similar to XC4000X— Standard long line can be used to continue at the
bottom of the next column
All other device routing is identical to 5V Spartan family
Carry Chain: Up Down
Spartan X X
SpartanXL X
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5V Compatibility
Can be driven by any 5V device and can drive 5V TTL (default)
Any 5 V
device
SpartanXLFPGA
Advanced 0.353.3V Core3.3V I/O
5V3.3V
5V
3.3V
Meets TTLLevels
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Optional 3.3V Clamp for PCI
Programmable global 3.3V clamp for 3V PCI
Sacrifices 5V compatibility
BITGEN option— Default is “5V Tolerant I/Os”
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Output Drive
Programmable 12 mA or 24 mA output drive— Pin-by-pin option— Default is 12 mA— 24 mA option supports 5V PCI V/I requirements— Similar to XC4000XLA
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IOB Output Mux
Output 2:1 mux or 2-input LUT in IOB supported in silicon and software— OMUX2, OAND2, etc. in SpartanXL library
Can use BUFGLS to drive one of the inputs for a fast path through the device
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Fast Capture Latch
IOB fast capture latch supported in silicon and software— SpartanXL library includes ILFFX, etc.
Note that there are no “fast” clock buffers— BUFGLS would be used to drive fast capture latch
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0
10
20
30
40
50
60
10KE
XCS30XL6KA
10KA
Spartan 6K
10K
2.5V 3.3V
5.0VSpartanXL K Factor = 11
Lowest K Factor
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Power Down Pin /PWRDWN pin activates low-power standby mode
— Occupies the M2 pin on the corresponding XC4000E device— Active Low— Timing is asynchronous
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All inputs (including M0, M1, DONE, CCLK and TDO) except /PWRDWN are disconnected from their sources — The internal nodes are pulled to GND
All pull-up and pull-down resistors on all I/Os (except /PWRDWN) are disabled
The GSR net is active throughout Power Down
The GTS net is active throughout Power Down
What Power Down Does
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Clear the “5 V tolerant I/Os” option
Disable the internal pull-up resistor for /PWRDWN
Avoid contention
Avoid internal oscillators
Run at 3.3V and 25C— Will be specified over operating conditions once
characterization is complete
To Achieve ICCO=100 A During Power Down...
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Boundary Scan
PowerDown pin taken out of scan chain— BSDL files are different than 5V Spartan
Added IDCODE Instruction— Becomes default instruction
Simplified configuration via boundary scan
Similar to XC4000XLA
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Bitstream
Different format than 5V Spartan bitstream— 1 more bit/frame, 1 more frame— Express mode is completely different
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Express Mode
M1 pin enables Express Mode configuration— True parallel configuration
– Similar to XC4000XLA— Default pull-up prevents Express mode— Use “BITGEN -g ExpressMode:Enable
-g CRC:Disable”
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New Features in SpartanXL Family
Higher speed (-4/-5) 8 flexible global low-skew buffers (BUFGLS) CLB latches and Input Fast Capture Latch Output multiplexer or lookup table 3.3V supply for low power with 5V tolerance
— 3V input clamp for 3V PCI, 24 mA output drive for 5V PCI Power-down pin Improved boundary scan Express parallel configuration mode Chip Scale packages