z/VM V6.4 Enterprise Systems …Chapter in this document Corresponding chapter(s) in IBM Enterprise Systems Ar chitectur e/390Principles of Operation, SA22-7201-08 Chapter 6, “Interr

z/VM

Enterprise Systems Architecture/Extended ConfigurationPrinciples of OperationVersion 6 Release 4

SC24-6192-01

IBM

Note:Before you use this information and the product it supports, read the information in “Notices” on page B-1.

This edition applies to version 6, release 4, modification 0 of IBM z/VM (product number 5741-A07) and to allsubsequent releases and modifications until otherwise indicated in new editions.

This edition replaces SC24-6192-00.

© Copyright IBM Corporation 1991, 2017.US Government Users Restricted Rights – Use, duplication or disclosure restricted by GSA ADP Schedule Contractwith IBM Corp.

Contents

Figures . . . . . . . . . . . . . . . v

Tables . . . . . . . . . . . . . . . vii

About This Document . . . . . . . . ixIntended Audience . . . . . . . . . . . . ixConventions . . . . . . . . . . . . . . ixWhere to Find More Information . . . . . . . x

Links to Other Documents and Websites . . . . xHow to Send Your Comments to IBM . . . . . . x

Summary of Changes . . . . . . . . xiiiSC24-6192-01, z/VM Version 6 Release 4 (August2017) . . . . . . . . . . . . . . . . xiii

Chapter 1. Introduction . . . . . . . 1-1Highlights of ESA/XC . . . . . . . . . . 1-1

The ESA/390 Base . . . . . . . . . . . 1-2System Program . . . . . . . . . . . . 1-2Compatibility . . . . . . . . . . . . . 1-2

Compatibility among ESA/XC Implementations 1-2Compatibility among ESA/XC, ESA/390,ESA/370, 370-XA and System/370 . . . . . 1-3Relationship to z/Architecture . . . . . . . 1-3

Chapter 2. Organization . . . . . . . 2-1Main Storage . . . . . . . . . . . . . 2-1Central Processing Unit . . . . . . . . . . 2-1

Access Registers . . . . . . . . . . . 2-1Host Access List . . . . . . . . . . . . 2-2Host Program . . . . . . . . . . . . . 2-2

Chapter 3. Storage . . . . . . . . . 3-1Storage Addressing . . . . . . . . . . . 3-1Absolute-Storage Address Spaces . . . . . . . 3-1

Private and Shareable Address Spaces . . . . 3-2Identification of Address Spaces . . . . . . 3-2

Address Types and Formats . . . . . . . . 3-2Address Types . . . . . . . . . . . . 3-2

Protection. . . . . . . . . . . . . . . 3-3Key-Controlled Protection . . . . . . . . 3-4Host Access-List-Controlled Protection . . . . 3-4Host Page Protection . . . . . . . . . . 3-5Low-Address Protection . . . . . . . . . 3-5Suppression on Protection . . . . . . . . 3-5

Prefixing . . . . . . . . . . . . . . . 3-6Dynamic Address Translation . . . . . . . . 3-6Translation Control . . . . . . . . . . . 3-6

Translation Modes . . . . . . . . . . . 3-6Address Summary . . . . . . . . . . . . 3-6

Addresses Translated . . . . . . . . . . 3-6Handling of Addresses . . . . . . . . . 3-7

Assigned Storage Locations . . . . . . . . . 3-8

Chapter 4. Control . . . . . . . . . 4-1Program-Status Word . . . . . . . . . . . 4-1

Program-Status-Word Format . . . . . . . 4-1Control Registers . . . . . . . . . . . . 4-1Tracing . . . . . . . . . . . . . . . 4-1Program-Event Recording . . . . . . . . . 4-1Timing. . . . . . . . . . . . . . . . 4-2

Time-of-Day Clock . . . . . . . . . . . 4-2Externally Initiated Functions . . . . . . . . 4-2

Resets . . . . . . . . . . . . . . . 4-2

Chapter 5. Program Execution . . . . 5-1Authorization Mechanisms . . . . . . . . . 5-1

Extraction-Authority Control . . . . . . . 5-1Access-Register Mechanisms . . . . . . . 5-1

PC-Number Translation . . . . . . . . . . 5-1Home Address Space . . . . . . . . . . . 5-1Access-Register Introduction . . . . . . . . 5-2

Summary . . . . . . . . . . . . . . 5-2Access-Register Functions . . . . . . . . 5-2

Host Access-Register Translation . . . . . . . 5-6Host-Access-Register-Translation Control . . . 5-6Access Registers . . . . . . . . . . . 5-6Host-Access-Register-Translation Structures . . 5-7Host-Access-Register-Translation Process . . . 5-8

Linkage Stack . . . . . . . . . . . . . 5-9Sequence of Storage References . . . . . . . 5-9

Chapter 6. Interruptions . . . . . . . 6-1Interruption Action . . . . . . . . . . . 6-1

Exceptions Associated with the PSW. . . . . 6-1Program Interruption . . . . . . . . . . . 6-1

Program-Interruption Conditions . . . . . . 6-1Multiple Program-Interruption Conditions . . . 6-3

Chapter 7. Instructions . . . . . . . 7-1ESA/390 Instructions Not Provided . . . . . . 7-1Modified ESA/390 Instructions . . . . . . . 7-1

DIAGNOSE . . . . . . . . . . . . . 7-1INSERT ADDRESS SPACE CONTROL . . . . 7-1INSERT STORAGE KEY EXTENDED . . . . 7-2INVALIDATE PAGE TABLE ENTRY . . . . . 7-2LOAD ADDRESS EXTENDED . . . . . . . 7-2LOAD PSW . . . . . . . . . . . . . 7-2LOAD USING REAL ADDRESS . . . . . . 7-2PURGE ALB . . . . . . . . . . . . . 7-2PURGE TLB . . . . . . . . . . . . . 7-2RESET REFERENCE BIT EXTENDED . . . . 7-3RESUME PROGRAM . . . . . . . . . . 7-3SET ADDRESS SPACE CONTROL and SETADDRESS SPACE CONTROL FAST . . . . . 7-3SET STORAGE KEY EXTENDED . . . . . . 7-4SET SYSTEM MASK . . . . . . . . . . 7-4SIGNAL PROCESSOR . . . . . . . . . 7-4STORE THEN OR SYSTEM MASK . . . . . 7-4

© Copyright IBM Corp. 1991, 2017 iii

STORE USING REAL ADDRESS . . . . . . 7-4TEST ACCESS . . . . . . . . . . . . 7-4TEST BLOCK . . . . . . . . . . . . 7-5TEST PROTECTION . . . . . . . . . . 7-5TRACE . . . . . . . . . . . . . . 7-6TRAP . . . . . . . . . . . . . . . 7-6

Chapter 8. Machine-Check Handling 8-1Handling of Machine Checks . . . . . . . . 8-1

Validation. . . . . . . . . . . . . . 8-1Machine-Check Extended Interruption Information 8-1

Failing-Storage Address and ASIT . . . . . 8-1

Chapter 9. Input/Output . . . . . . . 9-1Handling of Addresses for I/O . . . . . . . 9-1

Appendix. Comparison betweenESA/390 and ESA/XC . . . . . . . . A-1New Facilities in ESA/XC . . . . . . . . . A-1

DAT-Off Access-Register Addressing . . . . A-1Multiple Absolute-Storage Address Spaces . . A-1Address-Space Sharing . . . . . . . . . A-1

Comparison of Facilities. . . . . . . . . . A-1Summary of Changes . . . . . . . . . . A-2

Changes in Instructions Provided . . . . . A-2Comparison of PSW Formats . . . . . . . A-2Changes in Control-Register Assignments . . . A-2

Changes in Assigned Storage Locations . . . A-3Changes in Exceptions . . . . . . . . . A-3Changes to Insert Address Space Control . . . A-3Changes to Resume Program . . . . . . . A-3Changes to Set Address Space Control (SASC)and SASC Fast . . . . . . . . . . . . A-3Changes to Set System Mask . . . . . . . A-4Changes to Test Access . . . . . . . . . A-4Changes to Trap . . . . . . . . . . . A-4

Notices . . . . . . . . . . . . . . B-1Programming Interface Information . . . . . . B-2Trademarks . . . . . . . . . . . . . . B-2Terms and Conditions for Product Documentation B-2IBM Online Privacy Statement . . . . . . . . B-3

Glossary . . . . . . . . . . . . . C-1

Bibliography . . . . . . . . . . . . D-1Where to Get z/VM Information . . . . . . . D-1z/VM Base Library . . . . . . . . . . . D-1z/VM Facilities and Features . . . . . . . . D-2Prerequisite Products. . . . . . . . . . . D-3Other Publications . . . . . . . . . . . D-3

Index . . . . . . . . . . . . . . . X-1

iv z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Figures

3-1. Handling of Addresses (Part 1 of 2) 3-73-2. Handling of Addresses (Part 2 of 2) 3-84-1. PSW Format . . . . . . . . . . . 4-15-1. Use of Access Registers. . . . . . . . 5-36-1. Priority of Access Exceptions . . . . . . 6-4

7-1. Priority of Execution: SET ADDRESS SPACECONTROL and SET ADDRESS SPACECONTROL FAST . . . . . . . . . . 7-3

7-2. Priority of Execution: TEST ACCESS 7-5

© Copyright IBM Corp. 1991, 2017 v

vi z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Tables

3-1. Translation Modes . . . . . . . . . 3-6A-1. Availability of ESA/390 Facilities in

ESA/XC . . . . . . . . . . . . A-1A-2. ESA/390 Instructions Not Provided in

ESA/XC . . . . . . . . . . . . A-2

A-3. ESA/390 Control-Register Fields NotAssigned in ESA/XC . . . . . . . . A-2

A-4. Changes in Assigned Storage Locations A-3A-5. ESA/390 Exceptions Not Recognized A-3

© Copyright IBM Corp. 1991, 2017 vii

viii z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

About This Document

This document provides a detailed description of the IBM® Enterprise Systems Architecture/ExtendedConfiguration (ESA/XC) virtual-machine architecture, as provided by z/VM®. It describes the way anESA/XC virtual machine operates as it appears to an assembler language programmer. Because ESA/XCis based on and is closely related to Enterprise Systems Architecture/390® (ESA/390), this documentdefines ESA/XC by indicating the ways in which it is the same as, or different from, ESA/390.

The following elements of the ESA/XC architecture are covered in this document:v Overall organizationv The structure of storage and address spacesv Control facilitiesv Program executionv Interruptionsv The operation of instructionsv Input/output facilities

Intended AudienceThis document is intended for programmers who write or debug programs that run in ESA/XC virtualmachines.

You should have a basic familiarity with the ESA/390 architecture, or alternatively, the EnterpriseSystems Architecture/370 (ESA/370) or System/370 Extended Architecture (370-XA) upon whichESA/390 is based. These architectures are described in:v IBM Enterprise Systems Architecture/390 Principles of Operation, SA22-7201v IBM Enterprise Systems Architecture/370 Principles of Operation, SA22-7200v IBM System/370 Extended Architecture Principles of Operation, SA22-7085

You should also know IBM basic assembler language and have experience with z/VM programmingconcepts and techniques.

ConventionsThis document is intended to be used in conjunction with the definition of ESA/390 provided in IBMEnterprise Systems Architecture/390 Principles of Operation. Where possible, information is presented in thisdocument using the same style and general organization as IBM Enterprise Systems Architecture/390Principles of Operation. To assist in locating corresponding information in the two documents, thefollowing table shows the relationship of the chapters of this document to the chapters in IBM EnterpriseSystems Architecture/390 Principles of Operation.

Chapter in this document Corresponding chapter(s) in IBM Enterprise Systems Architecture/390Principles of Operation, SA22-7201-08

Chapter 1, “Introduction,” on page 1-1 Chapter 1, Introduction

Chapter 2, “Organization,” on page2-1

Chapter 2, Organization

Chapter 3, “Storage,” on page 3-1 Chapter 3, Storage

Chapter 4, “Control,” on page 4-1 Chapter 4, Control

Chapter 5, “Program Execution,” onpage 5-1

Chapter 5, Program Execution

© Copyright IBM Corp. 1991, 2017 ix

Chapter in this document Corresponding chapter(s) in IBM Enterprise Systems Architecture/390Principles of Operation, SA22-7201-08

Chapter 6, “Interruptions,” on page6-1

Chapter 6, Interruptions

Chapter 7, “Instructions,” on page 7-1 Chapter 7, General Instructions Chapter 8, Decimal Instructions Chapter 9,Floating-Point Overview and Support Instructions Chapter 10, ControlInstructions Chapter 18, Hexadecimal-Floating-Point Instructions Chapter 19,Binary-Floating-Point Instructions

Chapter 8, “Machine-CheckHandling,” on page 8-1

Chapter 11, Machine-Check Handling

Chapter 9, “Input/Output,” on page9-1

Chapter 13, I/O Overview Chapter 14, I/O Instructions Chapter 15, BasicI/O Functions Chapter 16, I/O Interruptions Chapter 17, I/O SupportFunctions

Note: There is no material in this document corresponding to Chapter 12, “Operator Facilities” of IBM EnterpriseSystems Architecture/390 Principles of Operation.

Where to Find More InformationBesides the document IBM Enterprise Systems Architecture/390 Principles of Operation, the followingdocuments in the z/VM library may be useful in understanding ESA/XC:v z/VM: CP Programming Servicesv z/VM: CMS Application Development Guidev z/VM: CMS Callable Services Referencev z/VM: CMS Application Development Guide for Assemblerv z/VM: CMS Macros and Functions Reference

For the complete list of documents in the z/VM library, see the “Bibliography” on page D-1.

Links to Other Documents and WebsitesThe PDF version of this document contains links to other documents and websites. A link from thisdocument to another document works only when both documents are in the same directory or database,and a link to a website works only if you have access to the Internet. A document link is to a specificedition. If a new edition of a linked document has been published since the publication of this document,the linked document might not be the latest edition.

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About This Document xi

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xii z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Summary of Changes

This document contains terminology, maintenance, and editorial changes. Technical changes are indicatedby a vertical line to the left of the changes. Some product changes might be provided through service andmight be available for some prior releases.

SC24-6192-01, z/VM Version 6 Release 4 (August 2017)This edition includes changes to support product changes provided or announced after the generalavailability of z/VM® V6.4.

© Copyright IBM Corp. 1991, 2017 xiii

xiv z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Chapter 1. Introduction

Highlights of ESA/XC . . . . . . . . . . 1-1The ESA/390 Base . . . . . . . . . . . 1-2

System Program . . . . . . . . . . . . 1-2Compatibility . . . . . . . . . . . . . 1-2

Compatibility among ESA/XC Implementations 1-2Compatibility among ESA/XC, ESA/390,ESA/370, 370-XA and System/370 . . . . . 1-3

Supervisor-State Compatibility . . . . . . 1-3Problem-State Compatibility . . . . . . 1-3

Relationship to z/Architecture . . . . . . . 1-3

This document describes, for reference purposes,the operation of virtual machines that execute inthe ESA/XC virtual-machine architecture asprovided by z/VM. It is organized as asupplement to the definition of the ESA/390architecture described in IBM Enterprise SystemsArchitecture/390 Principles of Operation.

If a particular element of the architecture(instruction, operation, program exception, etc.) isdescribed in this document, then the definitioncontained in this document supersedes thedefinition in IBM Enterprise SystemsArchitecture/390 Principles of Operation. If there isno discussion of a particular element of thearchitecture in this document, then the definitioncontained in IBM Enterprise SystemsArchitecture/390 Principles of Operation applies toESA/XC as well.

ESA/XC comprises the architectural facilitiesavailable to the program that is executing in thevirtual machine. ESA/XC virtual machinesoperate under the control of the z/VM ControlProgram (CP), a host program that runs in theESA/390 processor complex and manages thestructures that establish the virtual machines. Thedetails of these structures do not directly affectthe program in the virtual machine and aretherefore not described in this document.

Highlights of ESA/XCThe ESA/XC virtual-machine architecture is aderivative of Enterprise Systems Architecture/390(ESA/390) that is designed for the DAT-offvirtual-machine environment. Thisvirtual-machine architecture includes most of thefacilities of ESA/390 and offers major newcapabilities.

ESA/XC was designed with special emphasis onthe requirements of the interactive andservice-virtual-machine environments of z/VM. Inthese environments, the supervisor running in thevirtual machine is not an elaborate controlprogram, but rather an application-programmonitor. Consistent with such a virtual-machinesupervisor, ESA/XC allows application programsto benefit from architectural extensions providedby ESA/390 without requiring thevirtual-machine supervisor to perform complexmanagement functions. Instead, the host bears theresponsibility for the support and management ofthe real-machine facilities.

ESA/XC is also designed to take into account themultiple-virtual-machine environment of z/VM.By giving the responsibility for support andcontrol of the architecture to the host, the scope ofaccess that can be allowed using the architecturecan be extended in a controlled and securemanner across multiple virtual machines.Previously, the scope of access possible usingarchitectural facilities was necessarily limited to asingle virtual machine.

When compared to ESA/390, ESA/XC offers thefollowing extensions:v DAT-off access-register addressing makes the

access-register-addressing facility of ESA/370and ESA/390 available to z/VM applications.The facility can be used by a virtual machine toaccess its own address spaces as well as theaddress spaces of other virtual machines,subject to appropriate authorization.

v Multiple absolute-storage address spacessignificantly extend the amount of storageavailable to z/VM applications. Previously, thestorage available to an application was limitedto a single 2 gigabyte absolute-storage addressspace. With this facility, an application can havemultiple 2 gigabyte data-only spaces inaddition to the instruction space, providinggreatly increased application storage.

v Address-space sharing provides a basis forhigh-performance data sharing within a z/VMsystem. A virtual machine can authorize othervirtual machines to access, by means ofaccess-register addressing, any of its addressspaces (the instruction address space, or any

© Copyright IBM Corp. 1991, 2017 1-1

data-only address spaces). The shared accesscan be subsequently revoked when the sharedaccess is no longer appropriate.

The ESA/390 BaseESA/XC includes, as its base, most of thefacilities available to ESA/390 virtual machines.However, some of the facilities available inESA/390 are not provided in ESA/XC. Thissection summarizes these differences.

The most significant difference between ESA/390and ESA/XC is that in ESA/XC, guest dynamicaddress translation (DAT) is not provided.Consequently, in ESA/XC:v Guest virtual-storage address spaces are not

provided. Therefore, there are no guest segmenttables or page tables, nor is there a guesttranslation-lookaside buffer.

v The dual-address-space facility is not provided.Therefore, the EXTRACT PRIMARY ASN,EXTRACT SECONDARY ASN, INSERTVIRTUAL STORAGE KEY, LOAD ADDRESSSPACE PARAMETERS, MOVE TO PRIMARY,MOVE TO SECONDARY, PROGRAM CALL,PROGRAM TRANSFER and SET SECONDARYASN instructions are not provided. TheASN-translation and PC-number translationprocesses are never performed, andconsequently, there are no guest ASN firsttables, ASN second tables, linkage tables andentry tables. There are no guest primary andsecondary spaces, nor is the secondary-spacemode provided.

v Guest access-register translation is notprovided. Therefore, there are no guest accesslists, nor dispatchable-unit-control tables. Aguest ART-lookaside buffer is not provided.(Host access-register translation is provided asa comparable replacement for guestaccess-register translation.)

v The linkage stack is not provided, nor are theinstructions BRANCH AND STACK, EXTRACTSTACKED REGISTERS, EXTRACT STACKEDSTATE, MODIFY STACKED STATE, andPROGRAM RETURN.

v The home address space is not provided, nor isthe home-space mode.

v The private-space facility is not provided.

In addition, ESA/XC does not provide theinstructions LOAD REAL ADDRESS, SETCLOCK, and START INTERPRETIVEEXECUTION.

In contrast, the facilities previously mentioned aswell as extensions to them are available to thehost program. Since this document provides indetail only the architecture of the virtual-machineenvironment, reference is made to host facilitiesonly as needed to clearly describe theprogramming environment provided by thevirtual machine.

Except for facilities specifically identified in thisdocument as not provided, ESA/XC includes allfacilities that are defined in ESA/390.

System ProgramESA/XC is typically used with a virtual-machinesupervisor program, such as CMS, that cooperateswith the host to provide application-level serviceinterfaces for application programs executedwithin a single virtual machine. An ESA/XCvirtual machine operates under the control of thez/VM Control Program (CP) running in theESA/390 processor complex. The z/VM ControlProgram acts as the host program, managing theexecution of virtual machines and providingsystem-level services to the virtual machines.

Compatibility

Compatibility among ESA/XCImplementationsESA/XC virtual machines can be provided whenz/VM is operating on different real-processorimplementations, and may be provided bydifferent implementations of the host program.These different implementations of ESA/XC arelogically compatible. Specifically, any programwritten for ESA/XC gives identical results on anyESA/XC implementation, provided that theprogram:1. Is not time dependent.2. Does not depend on system facilities (such as

storage capacity, I/O equipment, optionalmachine facilities or optional orrelease-dependent host-program facilities)being present when the facilities are notincluded in the configuration or are notprovided by the host programimplementation.

3. Does not depend on system facilities beingabsent when the facilities are included in theconfiguration. For example, the program mustnot depend on interruptions caused by the useof operation codes or command codes that are

1-2 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

not installed in some real-processor models, ornot provided by some host program versions.Also, it must not use or depend on fieldsassociated with uninstalled facilities. Forexample, data should not be placed in an areaused by another model for fixed-logoutinformation. Similarly, the program must notuse or depend on unassigned fields inmachine formats (control registers, instructionformats, etc.) that are not explicitly madeavailable for program use.

4. Does not depend on results or functions thatare defined to be unpredictable ormodel-dependent or are identified asundefined. This includes the requirement thatthe program should not depend on theassignment of device numbers and CPUaddresses.

5. Does not depend on results or functions thatare defined in the functional-characteristicspublication for a particular real-processormodel to be deviations from the ESA/390architecture where those results or functions ofESA/390 are applicable in ESA/XC.

6. Takes into account any changes made to thearchitecture that are identified as affectingcompatibility.

Compatibility among ESA/XC,ESA/390, ESA/370, 370-XA andSystem/370

Supervisor-State CompatibilityA supervisor-state program written for 370-XA,ESA/370 or ESA/390 that uses thedynamic-address-translation (DAT) facility cannotbe transferred to an ESA/XC virtual machinebecause ESA/XC does not provide DAT.

A supervisor-state program written for 370-XA,ESA/370 or ESA/390 that does not use the DATfacilities can be transferred to an ESA/XC virtualmachine, provided that the control program:1. Complies with the limitations described in the

section “Compatibility among ESA/XCImplementations” on page 1-2 in this chapter.

2. Does not depend for correct operation onreceiving a special-operation exception when acontrol instruction that in ESA/390 requiresDAT to be on for successful execution isattempted in an ESA/XC virtual machine.

3. Does not use the following instructions:v LOAD ADDRESS SPACE PARAMETERSv LOAD REAL ADDRESS

v SET CLOCKv START INTERPRETIVE EXECUTION

Supervisor-state programs written forSystem/370*, regardless of whether the DATfacility is used, cannot be directly transferred tovirtual machines operating as defined byESA/XC. This is because the basic-control modeis not present and the facilities for I/O arechanged in the ESA/390 base of ESA/XC. (SeeAppendixes D, E and F of IBM Enterprise SystemsArchitecture/390 Principles of Operation for adetailed comparison among ESA/390, ESA/370,370-XA and System/370. See “Comparisonbetween ESA/390 and ESA/XC,” on page A-1 ofthis publication for a detailed comparisonbetween ESA/XC and ESA/390.)

Problem-State CompatibilityA high degree of compatibility exists at theproblem-state level in transferring from ESA/390,ESA/370, 370-XA or System/370 to ESA/XCoperation.

A problem-state program written for ESA/390,ESA/370, 370-XA or System/370 operates withESA/XC provided that the program:1. Complies with the limitations described in the

section “Compatibility among ESA/XCImplementations” on page 1-2 in this chapter.

2. Is not dependent on host or virtual-machinesupervisor facilities that are unavailable on thesystem.

3. Takes into account other changes made to theSystem/370 architectural definition that affectcompatibility between System/370 and the370-XA base of ESA/390. These changes aredescribed in Appendix F of IBM EnterpriseSystems Architecture/390 Principles of Operation.

Relationship to z/Architecturez/Architecture™ extends ESA/390 by providing64-bit addressing registers and arithmeticoperations. z/VM runs only in z/Architecture(64-bit) mode. However, ESA/XC remains aderivative of ESA/390. ESA/XC virtual machinesare supported, but are limited to 31-bit addressingand 32-bit registers and arithmetic operations. AnESA/XC virtual machine cannot operate in 64-bitmode.

Chapter 1. Introduction 1-3


Chapter 2. Organization

Main Storage . . . . . . . . . . . . . 2-1Central Processing Unit . . . . . . . . . . 2-1

Access Registers . . . . . . . . . . . 2-1Host Access List . . . . . . . . . . . . 2-2Host Program . . . . . . . . . . . . . 2-2

The basic organization of an ESA/XC virtualmachine follows the definition of systemorganization provided in Chapter 2 of ESA/390Principles of Operation. In addition, an ESA/XCvirtual machine has an extended configurationthat is described by the information in thischapter.

An ESA/XC virtual-machine configurationcontains all of the basic organizational elementsdefined for ESA/390 systems: main storage, oneor more central processing units (CPUs), operatorfacilities, a channel subsystem and I/O devices. Inaddition, an ESA/XC configuration has availableadditional separate absolute-storage addressspaces, up to 15 of which are concurrentlyaddressable as provided by access-registeraddressing. These 15 absolute-storage addressspaces are selected from among a larger set asdetermined by a table called a host access list.

Certain elements of an ESA/XC virtual-machineconfiguration are regulated by host controlsavailable to the z/VM installation. For example,the total main storage provided to a virtualmachine is regulated by host controls. These hostcontrols are specified in the host (CP) directoryentry for the virtual machine.

Contrary to the ESA/390 definition, the mainstorage of an ESA/XC virtual machine is notnecessarily isolated from access by the CPUs ofother virtual machines. By using host services, themain storage of one virtual machine can be madedirectly addressable by the CPUs of anotherconfiguration. This shared main storage can beused to provide shared data for a collection ofvirtual machines executing on a single z/VMsystem.

Main StorageAs in ESA/390, directly addressable main storageis provided for high-speed processing of data bythe CPU and the channel subsystem.

Main storage is allocated in extents known asabsolute-storage address spaces, or simplyaddress spaces. When a virtual machine is createdby the host, an initial address space is providedfor the virtual machine; this address space isknown as the host-primary address space.Initially, the host-primary address space is directlyaddressable only by the CPUs of the associatedvirtual machine. However, through the use ofhost services, the host-primary address space maybe made directly addressable by the CPUs ofother virtual machines.

Optionally, additional absolute-storage addressspaces may be added to the virtual configurationby means of host services. These additionaladdress spaces can be established as directlyaddressable by the CPUs of the associated virtualmachine and by the CPUs of other virtualmachines as appropriate.

Central Processing UnitA central processing unit (CPU) of an ESA/XCvirtual configuration includes all of the registersprovided in ESA/390: the PSW, general registers,floating-point registers, control registers, accessregisters, the prefix register, and the registers forthe clock comparator and CPU timer.

Access RegistersAs in ESA/390, ESA/XC provides 16 accessregisters numbered 0-15. An access registercontains an indirect specification of anabsolute-storage address space. When the CPU isin a mode called the access-register mode(controlled by a bit in the PSW), an instruction Bfield used to specify a logical or real address for astorage-operand reference designates an accessregister. The storage-operand is considered toreside within the absolute-storage address spacespecified by the access register. For someinstructions, an R field is used instead of a Bfield. Instructions are provided for loading andstoring the contents of access registers and formoving the contents of one access register toanother.

Each of access registers 1-15 can designate anyaddress space, including the instruction space (the


host-primary address space). Access register 0always designates the instruction space. Whenone of the access registers 1-15 is used todesignate an address space, the CPU determineswhich address space is designated by translatingthe contents of the access register usinghost-managed tables. When access register 0 isused to designate an address space, the CPUtreats the access register as designating theinstruction space, and it does not examine theactual contents of the access register. Therefore,the 16 access registers can designate, at any onetime, the instruction space and a maximum of 15other address spaces.

Host Access ListAn ESA/XC virtual machine has a host access listthat specifies the set of address spaces, inaddition to the virtual machine's host-primaryaddress space, that are available to a CPU when itis in the access-register mode. The host access listcontains a directory-specified number of hostaccess-list entries, each of which either designatesa particular address space or is consideredunused.

Through the use of host services, a host access-listentry can be set to designate a particular addressspace or can be returned to the unused state.

Host ProgramAn ESA/XC virtual machine operates under thecontrol of the z/VM Control Program (CP); thissupervisory program is called the host program,or simply the host. The host runs inz/Architecture mode or the ESA/390 processorcomplex and manages the execution of virtualmachines, possibly of varying architectures. It alsoprovides special service functions in addition tothe facilities described by the architecture(s).

The extended addressing capabilities of ESA/XCare under the control of the host, whichdetermines the extent to which a particularESA/XC virtual machine can use these extendedcapabilities. Services are provided by which anESA/XC virtual machine can request that itscapabilities be altered. These services include thecreation and deletion of additional address spacesand the modification of host access lists. Thesehost services are described in detail in thepublication z/VM: CP Programming Services.


Chapter 3. Storage

Storage Addressing . . . . . . . . . . . 3-1Absolute-Storage Address Spaces . . . . . . . 3-1

Private and Shareable Address Spaces . . . . 3-2Identification of Address Spaces . . . . . . 3-2

Address Types and Formats . . . . . . . . 3-2Address Types . . . . . . . . . . . . 3-2

Absolute Address . . . . . . . . . . 3-3Host-Primary Absolute Address . . . . . 3-3AR-Specified Absolute Address . . . . . 3-3Real Address . . . . . . . . . . . 3-3Host-Primary Real Address . . . . . . . 3-3AR-Specified Real Address . . . . . . . 3-3Virtual Addresses . . . . . . . . . . 3-3Logical Addresses . . . . . . . . . . 3-3Instruction Address . . . . . . . . . 3-3

Protection. . . . . . . . . . . . . . . 3-3Key-Controlled Protection . . . . . . . . 3-4

Fetch-Protection-Override Control . . . . 3-4Host Access-List-Controlled Protection . . . . 3-4Host Page Protection . . . . . . . . . . 3-5Low-Address Protection . . . . . . . . . 3-5Suppression on Protection . . . . . . . . 3-5

Prefixing . . . . . . . . . . . . . . . 3-6Dynamic Address Translation . . . . . . . . 3-6Translation Control . . . . . . . . . . . 3-6

Translation Modes . . . . . . . . . . . 3-6Address Summary . . . . . . . . . . . . 3-6

Addresses Translated . . . . . . . . . . 3-6Handling of Addresses . . . . . . . . . 3-7

Assigned Storage Locations . . . . . . . . . 3-8

This chapter describes the structure of mainstorage, including addressing and protectionaspects, for an ESA/XC virtual machine. Exceptas described in this chapter, the handling ofstorage for an ESA/XC virtual machine followsthe definition of storage provided in Chapter 3 ofIBM Enterprise Systems Architecture/390 Principles ofOperation.

Note: Because most references to storage for anESA/XC virtual machine apply to (guest) realstorage, the abbreviated term “storage” is oftenused in place of “real storage”. The term“storage” may also be used in place of “mainstorage” or “absolute storage” when the meaningis clear.

Storage AddressingThe addressable storage of an ESA/XC virtualmachine consists of one or more extents of mainstorage known as absolute-storage address spaces.The storage contained within a singleabsolute-storage address space is viewed as along horizontal string of bits, subdivided intobytes as is usual for ESA/390.

Absolute-Storage AddressSpacesAn absolute-storage address space is a singleextent of main storage that is directly addressableby a CPU or the channel subsystem. Anabsolute-storage address space consists of acollection of byte locations, and a set of byteaddresses assigned to those byte locations.

Note: Because all references to address spaces foran ESA/XC virtual machine apply toabsolute-storage address space and not tovirtual-storage address spaces, the abbreviatedterm “address space” is often used in place of“absolute-storage address space”.

Each byte location in storage is identified by anon-negative integer which is the byte address ofthe storage location within an absolute-storageaddress space. Byte locations are assignedaddresses starting at 0, and the addresses arealways assigned in complete 4K-byte blocks onintegral boundaries.

A byte address uniquely identifies a byte withinthe collection of bytes associated with a specificabsolute-storage address space. However, aparticular value of a byte address may notidentify a unique byte since a particular byteaddress may be associated with more than oneabsolute-storage address space.

A virtual machine has at least oneabsolute-storage address space, known as itshost-primary address space. This address space isprovided by the host when the virtual machine iscreated.


A virtual machine may obtain additionalabsolute-storage address spaces by using theADRSPACE CREATE host service. Theseadditional absolute-storage address spaces may besubsequently destroyed by using the ADRSPACEDESTROY host service. Subsystem reset will alsodestroy all absolute-storage address spacescreated by the ADRSPACE CREATE service.

In an absolute-storage address space created bymeans of the ADRSPACE CREATE host service,addresses are assigned in a single contiguousrange. However, in the host-primary addressspace of a virtual machine, there may be multiplediscontiguous ranges of assigned addresses.

The number and total size of absolute-storageaddress spaces permitted for the virtual machineis subject to directory-specified limits.

Programming Note: The ADRSPACE CREATEhost service is described in the publication z/VM:CP Programming Services. The number and totalsize of address spaces that the virtual machinecan create by means of ADRSPACE CREATE isspecified by the XCONFIG ADDRSPACEstatement in the CP directory. The size of thevirtual machine's host-primary address space isspecified by the USER or IDENTITY statement inthe CP directory. These three directory statementsare described in the publication z/VM: CPPlanning and Administration.

Private and Shareable AddressSpacesAn absolute-storage address space is consideredto be either a private address space, or ashareable address space, as follows.

An address space is a private address space if theaddress space is directly addressable only by theCPUs of a single virtual machine. An addressspace is a shareable address space if the addressspace can be directly addressed by the CPUs ofmore than one virtual machine.

Immediately after an address space is created bythe host, the address space is a private addressspace. Through the use of the ADRSPACEPERMIT host service, a private address space maybe transformed into a shareable address space,subject to a directory-specified authorization toshare address spaces. Subsequently, through theuse of the ADRSPACE ISOLATE host service, ashareable address space can be transformed into a

private address space. Subsystem reset will alsotransform a shareable address space into a privateaddress space.

Programming Note: The ADRSPACE PERMITand ADRSPACE ISOLATE host services aredescribed in the publication z/VM: CPProgramming Services.

Identification of Address SpacesAs a mechanism for differentiating one addressspace from another, each address space hasassociated with it an eight-byte identifying valuecalled an address-space identification token, orASIT.

The host assigns an ASIT to each address spacewhen the address space is created. The ASITassociated with a particular absolute-storageaddress space is fixed from the time the addressspace is created by the host until it issubsequently destroyed.

The host assigns ASITs in such a way that aparticular ASIT value will be associated with atmost one absolute-storage address space for thescope of the host IPL. That is, once a particularASIT value has been assigned to anabsolute-storage address space, that ASIT valuewill not be reassigned to another absolute-storageaddress space within the scope of the same hostIPL, even if the absolute-storage address space towhich the ASIT value was originally assigned issubsequently destroyed. ASIT values are notguaranteed to be assigned in any particularmanner across a host IPL.

The value 0000000000000000 hex is never assignedas an ASIT.

The specific format of an ASIT is undefined. Ingeneral, a particular ASIT value will have nosignificance to ESA/XC programs.

Address Types and Formats

Address TypesFor purposes of addressing main storage, twobasic types of addresses are recognized: absoluteand real. The addresses are distinguished on thebasis of the transformations that are applied tothe address during a storage access. In addition tothe two basic address types, additional types are


defined which are treated as one or another of thetwo basic types depending on the instruction andthe current mode.

Absolute AddressAn absolute address is the address assigned to amain-storage location within a particular addressspace. An absolute address is used for access tostorage contained in a particular address spacewithout any transformations performed on it.

Host-Primary Absolute AddressA host-primary absolute address is an absoluteaddress that identifies a location contained withinthe host-primary address space.

AR-Specified Absolute AddressAn AR-specified absolute address is an absoluteaddress that identifies a location contained withinan address space determined by hostaccess-register translation.

Real AddressA real address identifies a location within a realaddress space. In ESA/XC, each real address isconsidered to be one of two types: type-R ortype-A. These types determine the way in whichthe real address is converted into an absoluteaddress. They also determine the applicability oflow-address protection and fetch protection toreferences using the real address.

When a type-R real address is used for access tomain storage, it is converted by means ofprefixing to an absolute address. Low-addressprotection is applied to storage references madeusing a type-R real address subject to the settingof the low-address-protection control in controlregister 0. Fetch-protection checking is performedfor storage references made using a type-R realaddress subject to the setting of thefetch-protection-override control in controlregister 0.

When a type-A real address is used for access tomain storage, it is treated unchanged as anabsolute address; no prefixing is applied.Low-address protection is never applied to astorage references made using a type-A realaddress, regardless of the setting of thelow-address-protection control in control register0. Fetch-protection checking is always applied toa storage reference made using a type-A realaddress, regardless of the setting of thefetch-protection-override control in controlregister 0.

The set of byte locations with a singleabsolute-storage address space sequencedaccording to their real addresses is referred to asa real address space.

Host-Primary Real AddressA host-primary real address is a real address thatidentifies a location contained within thehost-primary address space. A host-primary realaddress is considered to be a type-R real address.

AR-Specified Real AddressAn AR-specified real address is a real addressthat identifies a location contained within anaddress space determined by host access-registertranslation. An AR-specified real address isconsidered to be a type-R real address when theALET used is 00000000 hex. An AR-specified realaddress is considered to be a type-A real addresswhen the ALET used is other than 00000000 hex.

Virtual AddressesSince the dynamic-address-translation facility isnot provided in ESA/XC, virtual addresses andvirtual storage are not available for ESA/XCvirtual machines.

Logical AddressesExcept where otherwise specified, thestorage-operand addresses for instructions arelogical addresses. Logical addresses are treated ashost-primary real addresses when in theprimary-space mode, and as AR-specified realaddresses when in the access-register mode. Someinstructions have storage operand addresses orstorage accesses associated with the instructionwhich do not follow the rules for logicaladdresses. In all such cases, the instructiondefinition contains a definition of the type ofaddress.

Instruction AddressAddresses used to fetch instructions from storageare called instruction addresses. An instructionaddress is treated as a host-primary real addressin all cases. The instruction address in the currentPSW and the target address of EXECUTE areinstruction addresses.

ProtectionFour protection facilities are provided to protectthe contents of main storage from destruction ormisuse by programs that contain errors or areunauthorized: key-controlled protection, hostaccess-list-controlled protection, host page

Chapter 3. Storage 3-3

protection, and low-address protection. Theseprotection facilities are applied independently;access to main storage is only permitted whennone of the facilities prohibits the access.

Key-controlled protection affords protectionagainst improper storing or against improperstoring and fetching, but not against improperfetching alone. The key-controlled-protectionmechanism is under the control of the program inthe virtual machine.

Host access-list-controlled protection, host pageprotection, and low-address protection affordprotection against improper storing. Hostaccess-list-controlled protection and host pageprotection are under control of the host andcannot be circumvented by a program in thevirtual machine. Low-address protection is undercontrol of the program in the virtual machine.

Guest access-list-controlled protection and pageprotection as defined in ESA/390 is not availablein ESA/XC since the dynamic address translationfacility is not provided.

Programming Note: In contrast, if the host hasapplied either host access-list-controlledprotection or host page protection to prevent aparticular storage or storage-key alteration by thevirtual machine, the program in the virtualmachine cannot circumvent this protection. Thisattribute makes host access-list-controlledprotection and host page protection appropriatefor sharing of storage among virtual machineswhere protection is required.

Host access-list-controlled protection isparticularly useful for sharing of storage amongvirtual machines because it regulates accessesusing an attribute of an individual referencerather than using an attribute of the sharedstorage itself. This allows some virtual machinesto be given authorization to store into the sharestorage while other, less authorized, virtualmachines are prevented from storing.

Low-address protection is not discussed in thisnote because low-address protection applies onlyto a virtual machine's references to its ownhost-primary address space and is therefore notapplicable to cross-virtual-machine sharing ofstorage under z/VM.

Key-Controlled ProtectionKey-controlled protection as defined in ESA/390applies, except for the applicability of thefetch-protection-override control as stated in thefollowing section.

Fetch-Protection-Override ControlWhen the fetch-protection-override control (bit 6of control register 0) is one, fetch protection isignored for storage references to locations ateffective addresses 0-2047 if the storage referenceis made with a type-R real address or a logicaladdress that is treated as a type-R real address.Fetch protection checking is always performed forstorage references made with a type-A realaddress or a logical address that is treated as atype-A real address, regardless of the setting ofthe fetch-protection-override control.

Host Access-List-ControlledProtectionHost access-list-controlled protection controlsstore accesses to an address space by means of aread-only or read/write access type maintained ineach host access-list entry. The access-type controlis not directly accessible to any virtual machine.Host access-list-controlled protection providesprotection against unauthorized storing or explicitstorage-key alteration.

In the access-register mode, when a hostaccess-list entry is used in thehost-access-register-translation part of a referenceand the host access-list entry indicates read/writeaccess, both fetch and store accesses are permittedto the address space specified by the hostaccess-list entry. Explicit alteration of storage keyswithin the address space is also permitted. Whenthe host access-list entry indicates read-onlyaccess, fetch accesses to storage or storage keysare permitted, and an attempt to store or to alterexplicitly a storage key causes a protectionexception to be recognized and the execution ofthe instruction to be terminated or suppressed.

Host access-list-controlled protection applies to allstore accesses or storage-key alterations made bymeans of a host access-list entry.

The access type permitted by a host access-listentry is established when the host access-list entryis made valid by means of the ALSERV ADD hostservice. If the host access-list entry designates anaddress space owned by another virtual machine,establishing a host access-list entry permitting


read/write access is subject to authorization. Thisauthorization is granted by means of theADRSPACE PERMIT host service by the virtualmachine that owns the address space.

Programming Note: The ALSERV ADD andADRSPACE PERMIT host services are describedin the publication z/VM: CP Programming Services.

Host Page ProtectionHost page protection controls store-typereferences to a 4K-byte block of storage (page) bymeans of a read-only or read/write authorizationassociated with each 4K-byte block of storage.The authorization control is not accessible by anyvirtual machine. Host page protection providesprotection against unauthorized storing orstorage-key alteration.

When the authorization associated with a 4K-byteblock of storage indicates read/write access, bothfetching of and storing into the block arepermitted, including the explicit alteration of thestorage key for the block. When the authorizationassociated with the block indicates read-onlyaccess, only fetching is permitted. When anattempt is made to store into a protected block oralter the storage key for a protected block, aprotection exception is recognized and theoperation is terminated or suppressed. Thecontents of the protected location remainunchanged.

Host page protection applies to all store accessesor storage-key alterations made by a virtualmachine.

The access authorization associated with a4K-byte block of storage is established by the hostbased on the host-defined characteristics of thatblock of storage.

Programming Note: The only 4K-byte blocks ofstorage established by z/VM as read-only pagesare:v those that correspond to shared read-only (SR)

or exclusive read-only (ER) ranges of namedsaved systems or named saved segmentsembedded in the host-primary address space.

v those that are mapped by means of theMAPMDISK host service to minidisk blocks ona read-only minidisk. The MAPMDISK hostservice is described in the publication z/VM: CPProgramming Services.

All other 4K-byte blocks of storage addressable bythe virtual machine are established as read/writepages.

Low-Address ProtectionLow-address protection operates as defined inESA/390, except as stated in the following.

When the low-address-protection control (bit 3 ofcontrol register 0) is one, low-address protectionapplies to storage references to locations ateffective addresses 0-511 if the storage referencesare made with a type-R real address or a logicaladdress that is treated as a type-R real address.Low-address protection does not apply forstorage references made with a type-A realaddress or a logical address that is treated as atype-A real address, regardless of the setting ofthe low-address-protection control.

Suppression on ProtectionIf the suppression-on-protection facility isinstalled, then, during a program interruption dueto a protection exception, either a one or a zero isstored in bit position 29 of real locations 144-147.The storing of a one in bit position 29 indicatesthat:v The unit of operation or instruction execution

during which the exception was recognizedwas suppressed, except that, if the instructionexecution would set the condition code ifcompleted normally, the condition code isunpredictable.

v Bit positions 1-19 of real locations 144-147contain bits 1-19 of the effective address thatcaused the exception. The effective address isthe address which exists before anytransformation by prefixing. Bit positions 30and 31 of real locations 144-147, and reallocations 160, contain information identifyingthe address space containing the protectedaddress.

Bit 29 being zero indicates that the operation waseither suppressed or terminated and that thecontents of the remainder of real locations144-147, and of real location 160, areunpredictable.

No protection-exception conditions necessarily setbit 29 to one.


PrefixingPrefixing operates as defined in ESA/390, exceptas stated in the following.

Prefixing is applied to convert a type-R realaddress into an absolute address. Prefixing is notapplied to convert a type-A real address into anabsolute address, but rather the type-A realaddress is treated unchanged as an absoluteaddress.

Dynamic Address TranslationThe dynamic address translation facility providedin ESA/390 is not available in ESA/XC.

Consequently, the following additionalDAT-related facilities defined in ESA/390 are alsonot available in ESA/XC:v Virtual-storage address spacesv Address-space numbers (ASNs)v ASN-translation controls, tables and processv ASN-authorization controls and process

Translation ControlAddress translation is controlled by a bit in thePSW as described in this section.

Additionally, the execution of the INVALIDATEPAGE TABLE ENTRY instruction is controlled bythe translation format, bits 8-12 of control register0. The definition of the translation format is thesame as provided in ESA/390.

Additional controls are provided as described inChapter 5, “Program Execution,” on page 5-1.These additional controls determine whether thecontents of each access register can be used todesignate an address space.

Translation ModesThe PSW bit that controls address translation isbit 17, the address-space-control bit. When bit 17is zero, the CPU is in the primary-space mode.When bit 17 is one, the CPU is in theaccess-register mode. The handling of addressesin these two modes is summarized in Table 3-1.

Table 3-1. Translation Modes

PSWBit17 Mode

Handling of Addresses

InstructionAddresses

Logical1

Addresses

0 Primary-space mode Host-primaryreal

Host-primaryreal

Table 3-1. Translation Modes (continued)

PSWBit17 Mode

Handling of Addresses

InstructionAddresses

Logical1

Addresses

1 Access-register mode Host-primaryreal

AR-specifiedreal

Explanation:

1 Certain real addresses are also handled differentlyaccording to the address-space-control mode. These realaddresses are explicitly specified elsewhere in thispublication.

Address Summary

Addresses TranslatedMost addresses that are explicitly specified by theprogram and are used by the CPU to refer tostorage operands are logical addresses and aresubject to implicit translation by means of hostaccess-register translation when the CPU is in theaccess-register mode. Analogously, the addressesindicated to the program as the result ofexecuting an instruction are logical.

The addresses used by the CPU for fetching ofinstructions are instruction addresses and arehost-primary real addresses. Similarly, theinstruction addresses indicated to the program onan interruption are host-primary real addresses.

Translation is not applied to quantities that areformed from the values specified in the B and Dfields of an instruction byte that are not used toaddress storage. This includes operand addressesin LOAD ADDRESS, LOAD ADDRESSEXTENDED, MONITOR CALL, and the shiftinginstructions. This also includes the addresses incontrol registers 10 and 11 designating thestarting and ending locations for PER.

With the exception of TEST PROTECTION,addresses explicitly designating storage keys(operand addresses in SET STORAGE KEYEXTENDED, INSERT STORAGE KEYEXTENDED, and RESET REFERENCE BITEXTENDED) are real addresses that are resolvedaccording to the translation mode. Theseaddresses are considered host-primary realaddresses when in the primary-space mode, andAR-specified real addresses when in theaccess-register mode. Similarly, the address of thestorage operand for TEST BLOCK is a realaddress that is resolved according to theaddressing mode.


The addresses implicitly used by the CPU forsuch sequences as interruptions are host-primaryreal addresses.

The addresses used by channel programs totransfer data and to refer to CCWs or IDAWs arehost-primary absolute addresses.

The handling of storage addresses associated withDIAGNOSE is dependent on the particular

DIAGNOSE code. See z/VM: CP ProgrammingServices for more information.

Handling of AddressesThe handling of addresses in ESA/XC issummarized in Figure 3-1. This figure lists alladdresses that are encountered by the programand specifies the address type.

Instruction Addressesv Instruction address in PSWv Branch addressv Target of EXECUTEv Address stored in the word at real location 152 on a program interruption for PERv Address placed in general register by BRANCH AND LINK, BRANCH AND SAVE, BRANCH AND SAVE

AND SET MODE, BRANCH AND STACK, and BRANCH RELATIVE AND SAVE

Logical Addressesv Addresses of storage operands for instructions not otherwise specifiedv Address placed in general register 1 by EDIT AND MARK and TRANSLATE AND TESTv Addresses in general registers updated by MOVE LONG, MOVE LONG EXTENDED, COMPARE LOGICAL

LONG, and COMPARE LOGICAL LONG EXTENDEDv Addresses in general registers updated by CHECKSUM COMPARE AND FORM CODEWORD, and UPDATE

TREEv Address for TEST PENDING INTERRUPTION when the second-operand address is nonzerov Addresses for parameter list of RESUME PROGRAM

Real Addresses Resolved According to the Translation Modev Address of storage key for INSERT STORAGE KEY EXTENDED, RESET REFERENCE BIT EXTENDED, and

SET STORAGE KEY EXTENDEDv Address of storage operand for TEST BLOCK

Host-Primary Real Addressesv Storage operand of INVALIDATE PAGE TABLE ENTRY, LOAD USING REAL ADDRESS, and STORE USING

REAL ADDRESSv Trace-entry address in control register 12v Dispatchable-unit-control-table origin in control register 2 (used by BRANCH AND SET AUTHORITY)

Permanently Assigned Host-Primary Real Addressesv Address of the doubleword into which TEST PENDING INTERRUPTION stores when the second-operand

address is zerov Addresses of PSWs, interruption codes, and the associated information used during interruptionv Addresses used for machine-check logout and save areas

Absolute Addressesv Failing-storage address stored in the word at real location 248

Figure 3-1. Handling of Addresses (Part 1 of 2)


Assigned Storage LocationsAll of the storage locations assigned in ESA/390are also assigned for the same purpose inESA/XC, except as specified in the following. Allassigned storage locations reside within thehost-primary address space.

144-147(Real Address)

Translation-Exception Identification: Duringa program interruption due to aprotection exception, if thesuppression-on-protection facility isinstalled, information is stored atlocations 144-147 describing the exception,as discussed in “Suppression onProtection” on page 3-5. Bit 29 being oneindicates that the unit of operation orinstruction execution during which theexception was recognized wassuppressed, except that, if the instructionexecution would set the condition code ifcompleted normally, the condition code isunpredictable. Bit 29 being zero indicatesthat the operation was either suppressedor terminated. If bit 29 is set to one, bitpositions 1-19 contain bits 1-19 of theeffective address that caused the

exception. The effective address is theaddress which exists before anytransformation by prefixing. Bit positions30-31 of real locations 144-147 are set toidentify the address space containing theprotected address, as follows:

00 A type-R real address was used.

01 CPU was in the access-registermode, and either the access wasan instruction fetch or it was astorage-operand reference thatused an AR-specified real address.The exception access id, reallocation 160, can be examined todetermine the address spacecontaining the address. However,if a type-R real address was used,bits 30 and 31 may be set to 00instead.

Bits 0 and 20-28 of real address 144-147are unpredictable.

160 (Real Address)

Exception Access Identification: During aprogram interruption due to anALEN-translation or addressing-capabilityexception, if the ALET being translatedwas obtained from an access register, thenumber of the access register used is

Host-Primary Absolute Addressesv Prefix valuev Channel-program address in ORBv Data address in CCWv IDAW address in a CCW specifying indirect data addressingv CCW address in a CCW specifying transfer in channelv Data address in IDAWv Measurement-block origin specified in SET CHANNEL MONITORv Address limit specified in SET ADDRESS LIMITv Addresses used by the store-status-at-address SIGNAL PROCESSOR orderv CCW address in SCSW

Permanently Assigned Host-Primary Absolute Addressesv Addresses used for the store-status functionv Addresses of PSW and first two CCWs used for initial program loading

Addresses Not Used to Reference Storagev PER starting address in control register 10v PER ending address in control register 11v Address stored in the word at real location 156 for a monitor eventv Address in shift instructions and other instructions specified not to use the address to reference storage

Figure 3-2. Handling of Addresses (Part 2 of 2)


stored in bit positions 4-7 of location 160,and zeros are stored in bit positions 0-3. Ifthe ALET being translated was notobtained from an access register, thenzeros are stored at location 160.

During a program interruption due to aprotection exception, an indication of theaddress space to which the exceptionapplies may be stored at location 160 ifthe suppression-on-protection facility isinstalled and bit 29 of thetranslation-exception identification is setto one. If the CPU was in theaccess-register mode and the access wasan instruction fetch, including a fetch ofthe target of an EXECUTE instruction,zeros are stored at location 160. If theCPU was in the access-register mode andthe access was a storage-operandreference to an AR-specified real address,the number of the access register used isstored in bit positions 4-7 of location 160,and zeros are stored in bit positions 0-3. Ifthe CPU was not in the access-registermode, the contents of location 160 areunpredictable.


Exception ALET: During a programinterruption due to an ALEN-translationor addressing-capability exception, theALET being translated is stored atlocations 168-171.


Failing-Storage ASIT: During amachine-check interruption, afailing-storage ASIT may be stored atlocations 256-263. A failing-storage ASITis stored whenever a failing-storageaddress is stored at locations 248-251.



Chapter 4. Control

Program-Status Word . . . . . . . . . . . 4-1Program-Status-Word Format . . . . . . . 4-1

Address-Space Control (AS) . . . . . . 4-1Control Registers . . . . . . . . . . . . 4-1Tracing . . . . . . . . . . . . . . . 4-1Program-Event Recording . . . . . . . . . 4-1Timing. . . . . . . . . . . . . . . . 4-2

Time-of-Day Clock . . . . . . . . . . . 4-2Externally Initiated Functions . . . . . . . . 4-2

Resets . . . . . . . . . . . . . . . 4-2Subsystem Reset . . . . . . . . . . 4-2

This chapter describes how the facilities forcontrolling, measuring and recording theoperation of one or more CPUs for ESA/XC differfrom those defined in ESA/390. Except asdescribed in the following, the definition forcontrol facilities provided in Chapter 4 of IBMEnterprise Systems Architecture/390 Principles ofOperation applies to ESA/XC as well.

Program-Status WordThe program-status word (PSW) is the same asdefined in ESA/390, except as described in thefollowing section.

Program-Status-Word Format

All PSW fields (that is, those bit positions that arenot required to be zeros) have the same functionas in ESA/390, with the exception of PSW bit 17.

Address-Space Control (AS)Bit 17 controls the translation mode. When bit 17is zero, the CPU is in the primary-space mode; alllogical, real and absolute addresses are consideredhost-primary addresses. When bit 17 is one, theCPU is in the access-register mode; all logical andcertain real and absolute addresses are considered

AR-specified addresses that reside within theaddress space determined by host access-registertranslation.

In addition to those bit positions unassigned inESA/390, bit positions 5 and 16 are alsounassigned in ESA/XC. A specification exceptionis recognized when these bit positions do notcontain zeros.

Control RegistersControl registers and control-register fields are thesame as defined in ESA/390, except as specifiedin the following.

In ESA/XC, all bit positions of control registers 1,4, 5, 7, 13, and 15 are unassigned. In addition, bits1, 2, and 5 of control register 0; bits 16-31 ofcontrol register 3; bits 0-15 of control register 8;bit 30 of control register 12; and bits 12-31 ofcontrol register 14 are unassigned. All of theseunassigned control-register positions areinitialized to zero.

The section “Changes in Control-RegisterAssignments” on page A-2 identifies the functionsassociated with these control registers andcontrol-register fields in ESA/390.

TracingTracing as defined in ESA/390 applies in ESA/XCexcept that ASN tracing is not provided. TheASN-trace-control bit is not provided, and SETSECONDARY ASN, PROGRAM CALL,PROGRAM RETURN and PROGRAMTRANSFER trace entries are never formed.

Program-Event RecordingThe ESA/390 definition of program-eventrecording (both PER 1 and PER 2) applies inESA/XC except as stated in this section.

The PER-2 means of restricting storage-alterationevents to occurring only when the storage iswithin designated address spaces is not providedin ESA/XC. In ESA/XC, storage-alteration eventsare not restricted to particular address spaces.

┌─┬─┬───────┬─┬─┬─────┬─┬─┬─┬─┬─┬─┬────┬──────┬───────────────┐│ │ │ │I│E│ │ │ │ │ │ │A│ │ Prog │ ││0│R│0 0 0 0│O│X│ Key │1│M│W│P│0│S│ CC │ Mask │0 0 0 0 0 0 0 0│└─┴─┴───────┴─┴─┴─────┴─┴─┴─┴─┴─┴─┴────┴──────┴───────────────┘0 1 2 5 6 7 8 12 16 18 20 24 31

┌─┬───────────────────────────────────────────────────────────┐│ │ ││A│ Instruction Address │└─┴───────────────────────────────────────────────────────────┘32 33 63

Figure 4-1. PSW Format


With PER 2, bit 10 of control register 9 is notignored when DAT is off. Instead, when bit 10 ofcontrol register 9 is one, it is unpredictablewhether any storage-alteration events areindicated.

TimingThe timing facilities include three facilities formeasuring time: the TOD clock, the clockcomparator, and the CPU timer. Except asdescribed in this section, the operation of thetiming facilities is as defined in ESA/390.

Time-of-Day ClockAn ESA/XC configuration does not have a TODclock distinct from the TOD clocks of otherESA/XC configurations. Instead, all ESA/XCconfigurations are provided with shared access tothe TOD clock of the host processor. The sharedhost TOD clock cannot be altered by the virtualmachine. However, if the extended-TOD-clockfacility is installed, SET CLOCKPROGRAMMABLE FIELD may be used to set theTOD programmable register for the virtual CPU.

The TOD clock is always in the set state. TheSTORE CLOCK and STORE CLOCK EXTENDEDinstructions store the current value of the hostprocessor TOD clock, and always set conditioncode 0. On a single host system, two executionsof STORE CLOCK or STORE CLOCKEXTENDED, possibly on different CPUs ofdifferent ESA/XC virtual machines, always storedifferent values.

The SET CLOCK instruction is not provided. Anattempt to execute the instruction results in anoperation exception.

The TOD-clock synchronization facility is notprovided.

Externally Initiated Functions

ResetsThe five reset functions provided in ESA/390 arealso provided in ESA/XC, and perform all of thefunctions defined in ESA/390. In addition, thesubsystem reset function performs additionalactions in ESA/XC, as defined in the following.

Subsystem reset provides a means for clearingfloating interruption conditions as well as for

invoking I/O-system reset. It also provides ameans for resetting elements of the ESA/XCenvironment that are controlled by the host onbehalf of the virtual machine.

Subsystem ResetSubsystem reset operates only on those elementsin the configuration which are not CPUs. Inaddition to the actions defined in ESA/390,subsystem reset in ESA/XC also performs thefollowing actions:1. All entries in the host access list are set to the

unused state.2. Any address spaces created using the

ADRSPACE CREATE host service aredestroyed.

3. The host-primary address space, if in theshareable state, is placed in the private stateand access permission granted to other virtualmachines is rescinded.

4. Certain other host-controlled entities are reset.

Programming Note: A list of the subsystem-resetactions on host-controlled entities is provided inthe description of the SYSTEM RESET commandin the publication z/VM: CP Commands andUtilities Reference.


Chapter 5. Program Execution

Authorization Mechanisms . . . . . . . . . 5-1Extraction-Authority Control . . . . . . . 5-1Access-Register Mechanisms . . . . . . . 5-1

PC-Number Translation . . . . . . . . . . 5-1Home Address Space . . . . . . . . . . . 5-1Access-Register Introduction . . . . . . . . 5-2

Summary . . . . . . . . . . . . . . 5-2Access-Register Functions . . . . . . . . 5-2

Access-Register-Specified Address Spaces . . 5-2Access-Register Instructions. . . . . . . 5-6

Host Access-Register Translation . . . . . . . 5-6Host-Access-Register-Translation Control . . . 5-6

Address-Space-Function Control . . . . . 5-6Access Registers . . . . . . . . . . . 5-6Host-Access-Register-Translation Structures . . 5-7

Host Access List . . . . . . . . . . 5-7Host Access-List Entries . . . . . . . . 5-7

Host-Access-Register-Translation Process . . . 5-8Selecting the Access-List-Entry Token . . . 5-8Making the Host-Primary Address Space theTarget Space . . . . . . . . . . . . 5-8Checking the ALET for Validity . . . . . 5-9Access-List Lookup . . . . . . . . . 5-9Checking for Host Access-List-ControlledProtection. . . . . . . . . . . . . 5-9Establishing the Target Address Space . . . 5-9Exceptions during Host Access-RegisterTranslation . . . . . . . . . . . . 5-9

Linkage Stack . . . . . . . . . . . . . 5-9Sequence of Storage References . . . . . . . 5-9

Program execution for ESA/XC proceeds asdefined in Chapter 5 of the IBM Enterprise SystemsArchitecture/390 Principles of Operation except forreferences in that publication to facilities definedelsewhere in this publication as not applicable toESA/XC and except for other differencesdescribed in this chapter.

Authorization MechanismsESA/390 includes several authorizationmechanisms to permit the control program toestablish the degree of function which is providedto a particular semiprivileged program. Most ofthese authorization mechanisms are related tofunctions that are not provided in ESA/XC andtherefore do not apply in ESA/XC. In particular,the following ESA/390 authorization mechanismsdo not apply in ESA/XC:v Mode requirements (DAT on)v Secondary-space controlv Subsystem-linkage control

v ASN-translation controlv Authorization index

The following ESA/390 authorization mechanismsapply in ESA/XC as defined in ESA/390 exceptas stated in the following sections:v Extraction-authority controlv PSW-key maskv Access-register mechanisms

Extraction-Authority ControlIn ESA/XC, the extraction-authority control doesnot apply to the execution of the INSERTADDRESS SPACE CONTROL instruction. That is,the instruction can be successfully executedregardless of the setting of bit 4 of control register0.

Access-Register MechanismsBit 15 of control register 0 is the address-spacefunction (ASF) control bit. Bit 15 must be one toallow completion of the BRANCH AND SETAUTHORITY, RESUME PROGRAM and TESTACCESS instructions. The ASF control alsocontrols the setting of the access-register mode bythe SET ADDRESS SPACE CONTROL and SETADDRESS SPACE CONTROL FAST instructions.The ASF control has no other effect in ESA/XC.

The use of access registers also involves varioushost-managed authorization mechanisms. Thesemechanisms are described in the publicationz/VM: CP Programming Services.

PC-Number TranslationNeither the PC-number translation process, northe PROGRAM CALL instruction, is provided inESA/XC.

Home Address SpaceNeither the home address space nor thehome-space mode is provided in ESA/XC.


Access-Register IntroductionBecause of the importance of this section toESA/XC, it is being provided in the form of acomplete replacement for the correspondingsection of IBM Enterprise Systems Architecture/390Principles of Operation rather than merely statingthe differences from ESA/390.

Many of the functions related to access registersare described in this section and in the sections“Host Access-Register Translation” on page 5-6and “Sequence of Storage References” on page 5-9in this chapter and “Sequence of StorageReferences” in Chapter 5 of IBM EnterpriseSystems Architecture/390 Principles of Operation.Additionally, Chapter 3, “Storage,” on page 3-1, ofthis publication describes translation modes andhost access-list-controlled protection; Chapter 4,“Control,” on page 4-1, describes the handling ofaddress spaces, access registers and host accesslists during resets and during the store-statusoperation; Chapter 6, “Interruptions,” on page 6-1,describes interruptions; and Chapter 7,“Instructions,” on page 7-1, describes theinstructions. Also, Chapter 11, “Machine-CheckHandling”. of IBM Enterprise SystemsArchitecture/390 Principles of Operation describesthe handling of access registers during amachine-check interruption and the validation ofthe access registers; and Chapter 12, “OperatorFacilities”, of that publication describes thealter-and-display controls for access registers. Thepublication z/VM: CP Commands and UtilitiesReference also describes alter and display facilitiesfor access registers and access-register-specifiedstorage.

SummaryThese major functions are provided:v A maximum of 16 absolute-storage address

spaces, including the instruction space, forimmediate and simultaneous use by asemiprivileged program; the address spaces arespecified by 16 special registers called accessregisters.

v Instructions for examining and changing thecontents of the access registers.

In addition, control and authority mechanisms areincorporated to control these functions.

Access registers allow a sequence of instructions,or even a single instruction such as MOVE (MVC)or MOVE LONG (MVCL), to operate on storage

operands in multiple address spaces. Thus, aprogram residing in one address space can usethe complete instruction set to operate on data inthat address space and in up to 15 other addressspaces, and it can move data between any and allpairs of these address spaces. Furthermore, theprogram can change the contents of the accessregisters in order to access still other addressspaces.

The instructions for examining and changingaccess-register contents are unprivileged and aredescribed in Chapter 7, “General Instructions” ofIBM Enterprise Systems Architecture/390 Principles ofOperation and Chapter 7, “Instructions,” on page7-1 of this publication. They are:v COPY ACCESSv EXTRACT ACCESSv LOAD ACCESS MULTIPLEv LOAD ADDRESS EXTENDEDv SET ACCESSv STORE ACCESS MULTIPLE

Access registers specify address spaces when theCPU is in the access-register mode. The SETADDRESS SPACE CONTROL and SET ADDRESSSPACE CONTROL FAST instructions allowsetting of the access-register mode, and theINSERT ADDRESS SPACE CONTROL instructionprovides an indication of the access-registermode. These instructions are described inChapter 7, “Instructions,” on page 7-1.

Access-Register Functions

Access-Register-Specified AddressSpacesThe CPU includes sixteen 32-bit access registersnumbered 0-15. In the access-register mode,which results when PSW bit 17 is one, aninstruction B or R field that is used to specify thelogical address of a storage operand designatesnot only a general register but also an accessregister. In certain cases, an instruction R fieldthat is used to specify the real address of astorage operand designates both a general registerand an access register. The designated generalregister is used in the ordinary way to form thelogical or real address of the storage operand. Thedesignated access register contains a parametercalled an access-list-entry token (ALET) that isused to determine the address space to which thelogical or real address is relative. This addressspace is known as the target address space.


For certain host services invoked in theaccess-register mode, ALETs may be provided inthe parameter list for the host service as well asproviding an ALET in access registers. Theseparameter-list ALETs specify the target addressspaces for particular storage operands of the hostservice.

Regardless of its source, an ALET specifies thetarget address space for an operand by indirectlyspecifying the address-space identification token(ASIT) for the target address space.

In the general case, the ALET specifies an addressspace through the use of a host-managed tablecalled a host access list. The ALET selects anentry in a host access list, and the selected hostaccess-list entry in turn specifies the targetaddress space. However, a special ALET valuecan specify the host-primary address spacewithout using a host access-list entry.

The process of using an ALET to determine theaddress space containing an operand is calledhost access-register translation (ART). This isdepicted, for an ALET obtained from an accessregister, in Figure 5-1.

An access register is said to specify anAR-specified address space. The addresses in anAR-specified address space are AR-specified realor AR-specified absolute addresses.

In the access-register mode, as in theprimary-space mode, all instruction addresses arehost-primary real.

Designating Access Registers: In theaccess-register mode, an instruction B or R field

designates an access register, for use in hostaccess-register translation, under the followingconditions:v The field is a B field that designates a general

register containing a base address. The baseaddress is used, along with a displacement (D)and possibly an index (X), to form the logicaladdress of a storage operand.

v The field is an R field that designates a generalregister containing the logical address, or forcertain instructions the real address, of astorage operand.

For example, consider the following instruction:MVC 0(L,1),0(2)

The second operand, of length L, is to be movedto the first-operand location. The logical addressof the second operand is in general register 2, andthat of the first-operand location is in generalregister 1. The address space containing thesecond operand is specified by access register 2,and that containing the first-operand location isspecified by access register 1. These two addressspaces may be different address spaces, and eachmay be different from the instruction space (thehost-primary address space).

The COMPARE AND FORM CODEWORD andUPDATE TREE instructions specify storageoperands by means of implicitly designatedgeneral registers and access registers.

An instruction R field may designate an accessregister for other than the purpose of hostaccess-register translation.

The fields that may designate access registers,whether or not for host access-register translation,are indicated in the summary figure at thebeginning of each instruction chapter in IBMEnterprise Systems Architecture/390 Principles ofOperation.

Determining the Target Address Space: Thissection and the following ones introduce thehost-access-register-translation process andpresent the concepts related to access lists.

The target address space specified by an ALET isdetermined by host access-register translation asfollows:v If the ALET contained in the access register or

in the parameter list supplied to a host service

Instruction┌────────────┬───┬─────────┐ Displacement│ │ B │ D ├────────────────┐└────────────┴┬─┬┴─────────┘ │

│ │ ││ │ General Register │

In Access-Register Mode │ │ ┌─────────────────────┐ │┌──────────────────────────┘ └─→│ Base Address │ ││ └──────────┬──────────┘ ││ │ ││ Access Register ↓ ││ ┌─────────────────────┐ ┌───┐ │└─→│ ALET │ │ + │←──────────┘

└──────────┬──────────┘ └─┬─┘│ │↓ │

┌─────┐ ││ ART │ │└──┬──┘ │

│ │↓ ↓

ASIT Identifying Address Within theTarget Address Space Address Space

Figure 5-1. Use of Access Registers

Chapter 5. Program Execution 5-3

is 00000000 hex, the target address space is thehost-primary address space.

v If the ALET contained in the access register orin the parameter list supplied to a host serviceis any other value, the target address space isidentified by an address-space identificationtoken (ASIT) obtained from a host access-listentry. The ALET selects a host access-list entry,which contains the address-space identificationtoken that identifies the address space.

Access register 0 is treated in a special way byhost access-register translation; it is treated ascontaining 00000000 hex, and its actual contentsare not examined. Thus, a logical or real addressspecified by means of a zero B or R field in theaccess-register mode is always relative to thehost-primary address space, regardless of thecontents of access register 0. However, there isone exception to how access register 0 is treated:the TEST ACCESS instruction uses the actualcontents of access register 0, instead of treatingaccess register 0 as containing 00000000 hex.

The treatment of an access register containing thevalue 00000000 hex as designating thehost-primary address space allows that addressspace to be addressed, in the access-registermode, without requiring the use of a hostaccess-list entry. This is useful for moving data toor from the host-primary address space.

Access Lists: Each ESA/XC virtual machine isprovided with a separate host access list for itsuse in accessing address spaces when in theaccess-register mode. The access list is protectedfrom direct examination or modification by thevirtual machine. The virtual machine for which ahost access list is provided can alter the set ofaddress spaces designated by the host access listby using host services.

An access list can contain from 6 to 1022 entries,each of which can designate a different addressspace. The size of virtual machine's access list iscontrolled by the host directory entry for thevirtual machine.

Access-List-Entry Token: The contents of anaccess register are called an access-list-entry token(ALET) since, in the general case, they select anentry in a host access list. The ALET is a 32-bittoken, the structure of which is not furtherdefined.

An ALET can exist in an access register, in ageneral register, in a parameter list for certainhost services, or in storage, and it has no specialprotection from manipulation by the program.Any program can transfer ALETs back and forthamong access registers, general registers, andstorage. A called program can save the contents ofthe access registers in any storage area availableto it, load and use the access registers for its ownpurposes, and then restore the original contents ofthe access registers before returning to its caller.

Allocating and Invalidating Access-List Entries:The host provides to each ESA/XC virtualmachine a separate host access list. The hostaccess list associated with a particular virtualmachine specifies the collection of address spaces,in addition to the virtual machine's host-primaryaddress space, that are available to a programwhen it is in the access-register mode. Allalterations of host access lists are performed bymeans of host services.

Each entry in a host access list is considered to bein one of three states: valid, revoked or unused. Avalid host access-list entry specifies an addressspace and can be used in the access-register modeto reference that space. An unused host access-listentry is available for allocation as a valid entry. Arevoked host access-list entry is an entry that waspreviously valid, but at some time after theallocation of the entry the virtual machine'sauthorization to access the designated addressspace was revoked. (Revoked host access-listentries are described further in the section“Revoking Accessing Capability” on page 5-5.)The host provides services for allocating a validhost access-list entry (changing an unused entryto valid) and for deallocating a valid or revokedentry (making it unused).

Allocation of a host access-list entry consists ofthe following steps. A program invokes theALSERV ADD host service, passing theaddress-space identification token (ASIT)specifying the address space for which access isbeing requested, and passing an indication ofwhether read-only or read/write access is desired.If the ASIT identifies a space not owned by therequesting virtual machine, the host checks thatthe requesting virtual machine has beenauthorized for the requested type of access. Thisauthorization is granted through use of theADRSPACE PERMIT by the virtual machine thatowns the address space. If the ASIT identifies aspace owned by the requesting virtual machine, it


is always authorized for read/write access. If thevirtual machine's request is authorized, the hostselects an unused entry in the virtual machine'shost access list, changes it to a valid entryspecifying the subject address space, establishesthe entry as permitting read-only or read/writeaccess as requested, and returns to the programan access-list-entry token (ALET) that designatesthe entry. Once assigned, the ALET remainsuniquely associated with the entry until the entryreturns to the unused state.

The program can place the ALET in an accessregister in order to access the address space. Theprogram can also place the ALET in a parameterlist for a host service to access the address spacethrough certain host services.

Later, through the use of the ALSERV REMOVEhost service, the host access-list entry that wasallocated may be returned to the unused state.This makes the entry available for reallocation todesignate a different address space.

Notes on the Authorization Mechanism: A hostaccess list is a kind of capability list, in the sensein which the word “capability” is used incomputer science. The host establishes the policiesthat are used to allocate entries in a host accesslist and performs appropriate authorizationchecking during the allocation of an entry. After avalid entry has been made in a host access list,the host-access-register-translation processenforces the host policies in a well-performingway.

Revoking Accessing Capability: It may be that aparticular valid host access-list entry specifies anaddress space owned by another virtual machineand the owning virtual machine revokes theaccessing virtual machine's authority to access theaddress space. In this case, the revocation processcauses all host access-list entries of the accessingvirtual machines that designate the subject spaceto be changed from the valid to the revoked state.The owning virtual machine revokes accessauthority through the use of the ADRSPACEISOLATE host service.

Similarly, a particular valid host access-list entrymay specify an address space (owned by thesame or another virtual machine) that issubsequently destroyed before the host access-listentry is deallocated. The destroy process causesall host access-list entries of all virtual machinesthat designate the subject space to be changed

from the valid to the revoked state. The owningvirtual machine destroys an address spacethrough the use of the ADRSPACE DESTROYhost service.

An exception is recognized during hostaccess-register translation if an ALET is used thatselects a revoked host access-list entry. Nodistinction is made between the two causes of ahost access-list entry's entering the revoked state.

Preventing Store Accesses: Each host access-listentry contains an access-type indicator whichdetermines if the entry can be used for fetch andstore accesses to the subject address space or onlyfor fetch accesses. This access-type indicator isestablished when the entry is allocated by thehost, depending on the requested type of accessto the address space and the requesting virtualmachine's authorization. When the access-typeindicator in a host access-list entry specifiesread-only access, the entry cannot be used toperform store accesses or explicit storage-keyalterations. The principal description of thisprotection mechanism is in the section “HostAccess-List-Controlled Protection” on page 3-4.

Improving Translation Performance: Hostaccess-register translation (ART) conceptuallyoccurs each time a logical or real address is usedto reference a storage operand in theaccess-register mode. To improve performance,ART normally is implemented such that some orall of the information contained in thehost-managed ART structures is maintained in aspecial buffer referred to as the ART-lookasidebuffer (ALB). The information in the ARTstructures may be placed in the ALB andsubsequent translations may be performed usingthe information in the ALB. Conceptually, theALB buffers information necessary to transforman ALET into the identification of the addressspace which the ALET designates. The ALB istypically implemented such that it is capable ofbuffering the ART structures related to a relativelysmall number of recent translations.

The host manages the ALB to ensure that thecontents of the ALB never represent obsolete ARTstructures. Other than the effect on performance,the structure and management of the ALB are notvisible to the ESA/XC virtual machine. The ALBis not further described in this publication.


Access-Register InstructionsThe following instructions are provided forexamining and changing the contents of accessregisters:v COPY ACCESSv EXTRACT ACCESSv LOAD ACCESS MULTIPLEv LOAD ADDRESS EXTENDEDv SET ACCESSv STORE ACCESS MULTIPLE

The SET ACCESS instruction replaces the contentsof a specified access register with the contents ofa specified general register. Conversely, theEXTRACT ACCESS instruction moves thecontents of an access register to a general register.The COPY ACCESS instruction moves thecontents of one access register to another.

The LOAD ACCESS MULTIPLE instruction loadsa specified set of consecutively numbered accessregisters from a specified storage location whoselength in words equals the number of accessregisters loaded. Conversely, the STORE ACCESSMULTIPLE instruction function stores thecontents of a set of access registers at a storagelocation.

The LOAD ADDRESS EXTENDED instruction issimilar to the LOAD ADDRESS instruction in thatit loads a specified general register with aneffective address specified by means of the B, X,and D fields of the instruction. In addition, LOADADDRESS EXTENDED operates on the accessregister having the same number as the generalregister loaded. When the address-space control,PSW bit 17, is zero, LOAD ADDRESSEXTENDED loads the access register with00000000 hex. When the address-space control isone, LOAD ADDRESS EXTENDED loads thetarget access register with a value that dependson the B field of the instruction. If the B field iszero, LOAD ADDRESS EXTENDED loads thetarget access register with 00000000 hex. If the Bfield is nonzero, LOAD ADDRESS EXTENDEDloads the target access register with the contentsof the access register designated by the B field.However, in the last case, when the contents ofthe access register designated by the B field arenot a correctly-formed ALET, the results in thetarget general register and access register areunpredictable.

The address-space-control values zero and onespecify the primary-space mode and theaccess-register mode, respectively.

When used in host access-register translation, theaccess-register value 00000000 hex specifies thehost-primary address space.

Host Access-Register TranslationBecause of the importance of this section toESA/XC, it is being provided in the form of acomplete replacement for the correspondingsection of IBM Enterprise Systems Architecture/390Principles of Operation rather than merely statingthe differences from ESA/390.

Host access-register translation is introduced inthe section “Access-Register-Specified AddressSpaces” on page 5-2.

Host-Access-Register-TranslationControlHost access-register translation is controlled by anaddress-space control, and by theaddress-space-function (ASF) control in controlregister 0. The address-space control, PSW bit 17,is described in the section “Translation Modes” onpage 3-6. The address-space-function (ASF)control is described in the following section.

Additional controls are located in thehost-managed access-register-translationstructures.

Address-Space-Function ControlBit 15 of control register 0 is theaddress-space-function (ASF) control. This bitmust be one when a SET ADDRESS SPACECONTROL or SET ADDRESS SPACE CONTROLFAST instruction that is to set the access-registermode is executed, and when a TEST ACCESSinstruction is executed; otherwise, aspecial-operation exception is recognized. Theaddress-space-function control has no other effectin an ESA/XC virtual machine.

Access RegistersThere are sixteen 32-bit access registers numbered0-15. The contents of an access register are calledan access-list-entry token (ALET). An ALET hasthe following format:┌───────────────────────────────────┐│ ALET │└───────────────────────────────────┘0 31

When the ALET is not 00000000 hex, it is treatedas a 32-bit token that may be associated with at


most one entry in the virtual machine's hostaccess list. During host access-register translation,the ALET is used as a selection token todetermine whether there is an entry in the hostaccess list that is associated with the ALET. Ifthere is no such entry, an ALEN-translationexception is recognized.

Not all possible 32-bit values are valid for use asan ALET. If an incorrectly-formed value is used asan ALET during host access-register translation,an ALET-specification exception is recognized.

When the ALET is 00000000 hex, it specifies thehost-primary address space and is not used toselect an entry from the host access list. A logicalor real address used in conjunction with an ALETequal to 00000000 hex is treated as a type-R realaddress.

Access register 0 usually is treated in hostaccess-register translation as containing 00000000hex, and its actual contents are not examined; thehost access-register translation done as part ofTEST ACCESS is the only exception. Accessregister 0 is also treated as containing 00000000hex when it is designated by the B field of LOADADDRESS EXTENDED when PSW bit 17 is one.When access register 0 is specified for TESTACCESS or as a source for COPY ACCESS,EXTRACT ACCESS, or STORE ACCESSMULTIPLE, the actual contents of the accessregister are used. Access register 0, like any otheraccess register, can be loaded by COPY ACCESS,LOAD ACCESS MULTIPLE, LOAD ADDRESSEXTENDED, and SET ACCESS.

Host-Access-Register-TranslationStructuresWhen the ALET being translated is not 00000000hex, host access-register translation selects anentry in the virtual machine's host access list.

Host Access ListEach ESA/XC virtual machine has associatedwith it a host access list that specifies thoseaddress spaces, in addition to the host-primaryaddress space, that are available to a virtual CPUwhen it is in the access-register mode. The hostaccess list contains a directory-specified numberof host access-list entries, each of whichconceptually contains the information defined inthe following section. The host access list is notexplicitly addressable by the virtual machine.

Instead, entries in the host access list aremanipulated by means of host services.

Programming Notes: The size of the host accesslist allocated for a virtual machine is specified bythe XCONFIG ACCESSLIST statement in the CPdirectory. This CP directory statement is describedin the publication z/VM: CP Planning andAdministration.

Host Access-List EntriesEach host access-list entry has the followinglogical structure:┌───┬──────┬──────────┬───┬───┐│ S │ ALET │ ASIT │ A │ F │└───┴──────┴──────────┴───┴───┘

The fields within the host access-list entry havethe following meanings:

Access-list-entry state (S): This field indicatesthe state of the host access-list entry: valid,revoked, or unused.

Host access-list entries in the valid or revokedstate have been allocated for use by the programand can be selected by host access-registertranslation. If the entry selected by hostaccess-register translation is in the valid state, thetranslation process proceeds. If the entry selectedby host access-register translation is in therevoked state, an addressing-capability exceptionis recognized.

Host access-list entries in the unused state are notcurrently allocated for use by the program andcannot be selected by host access-registertranslation. The other fields of the host access-listentry have no meaning when the entry is in theunused state.

Selection ALET (ALET): For a host access-listentry in the valid or revoked state, this fieldspecifies the ALET that selects the entry duringhost access-register translation. There is at mostone valid or revoked entry in the host access listthat contains a particular ALET value as theselection ALET. This field has no meaning in anentry in the unused state.

Designated address space (ASIT): For a hostaccess-list entry in the valid state, this fieldcontains the address-space identification token(ASIT) identifying the address space designated


by the host access-list entry. This field has nomeaning in an entry in the revoked or unusedstate.

Access type (A): For a host access-list entry inthe valid state, this field specifies the types ofaccess permitted to the address space designatedby the host access-list entry: read-only orread/write access. If this field indicatesread/write access, both fetch and store accessesare permitted. If this field indicates read-onlyaccess, only fetch accesses are permitted, and anattempt to store causes a protection exception forhost access-list-controlled protection to berecognized. This field has no meaning in an entryin the revoked or unused state.

Fault handling (F): For a host access-list entry inthe valid state, this field indicates the manner inwhich host segment or page faults are to behandled: synchronously or asynchronously. Forinformation on the options for handling of hostsegment and page faults, see the description ofthe PFAULT and ALSERV services in thepublication z/VM: CP Programming Services. Thisfield has no meaning in an entry in the revokedor unused state.

Host-Access-Register-TranslationProcessThis section describes the host-access-register-translation process as it is performed during astorage-operand reference in the access-registermode by any instruction except TEST ACCESSand TEST PROTECTION. TEST PROTECTION inthe access-register mode, and TEST ACCESS inany translation mode, perform host access-registertranslation the same as described here, except thatthe following exceptions cause a setting of thecondition code instead of being treated asprogram-interruption conditions:v Addressing capabilityv ALET specificationv ALEN translation

Host access-register translation operates on theaccess register designated in a storage-operandreference in order to determine the address spacecontaining the storage operand, hereafter calledthe target address space. When one ofaccess-registers 1-15 is designated, theaccess-list-entry token (ALET) that is in the accessregister is used to determine the address space.When access register 0 is designated, an ALEThaving the value 00000000 hex is used, except that

TEST ACCESS uses the actual contents of accessregister 0. In certain cases, host access-registertranslation operates on an ALET obtained from aparameter list for a host service.

When the ALET is 00000000 hex, the host-primaryaddress space is the target address space.

When the ALET is other than 00000000 hex, theALET is verified to be correctly formed and isthen used in a lookup process to select an entryin the virtual machine's host access list.

The selected host access-list entry is checked forbeing in the valid state.

If a store access or an explicit storage-keyalteration is to be performed, the access-typeindication in the host access-list entry is checkedto determine if read/write access is permitted.

When no exceptions are recognized, the ASIT inthe selected host access-list entry identifies thetarget address space.

Selecting the Access-List-Entry TokenWhen one of access registers 1-15 is designated,or for the access register designated by the R1field of TEST ACCESS, host access-registertranslation uses the access-list-entry token (ALET)that is in the access register. When access register0 is designated, except for TEST ACCESS, anALET having the value 00000000 hex is used, andthe contents of access register 0 are not examined.

In certain cases, host access-register translationuses an ALET contained in a parameter list for ahost service. The ALET associated with storageoperands for host services is described as part ofthe definition of the service in the publicationz/VM: CP Programming Services.

When LOAD ACCESS MULTIPLE changes thecontents of an access register being used by hostaccess-register translation, or when a store accesschanges the contents of an ALET field in aparameter list for a host service, the ALETobtained at the start of the operation is in effectfor the duration of the operation.

Making the Host-Primary AddressSpace the Target SpaceWhen the ALET being translated is 00000000 hex,the virtual machine's host-primary address spaceis established as the target address space and hostaccess-register translation is completed.


Checking the ALET for ValidityThe ALET is checked for being a correctly-formedALET. If the ALET is not correctly formed, anALET-specification exception is recognized, andthe operation is suppressed.

Access-List LookupA lookup in the virtual machine's host access listis performed.

Conceptually, each host access-list entry in thevalid or revoked state is examined to determinewhether the selection ALET in the host access-listentry matches the ALET being translated. Hostaccess-list entries in the unused state are notconsidered by this lookup process.

There is at most one valid or revoked hostaccess-list entry containing a selection ALETmatching the ALET being translated. If there is anentry with a selection ALET matching the ALETbeing translated, that entry is said to be the entryselected by the ALET being translated. If theselected entry is in the valid state, thehost-access-register-translation process proceeds.If the selected entry is in the revoked state, anaddressing-capability exception is recognized, andthe operation is terminated. If there is no valid orrevoked host access-list entry containing aselection ALET matching the ALET beingtranslated, an ALEN-translation exception isrecognized, and the operation is nullified.

Checking for Host Access-List-Controlled ProtectionIf a store access or an explicit storage-keyalteration is to be performed and the access-typeindication in the selected host access-list entryspecifies read-only access, a protection exceptionis recognized, and the operation is terminated.

Establishing the Target Address SpaceWhen the ALET being translated is other than00000000 hex and no exception is recognized inthe steps described previously, the address spaceidentified by the ASIT field in the selected hostaccess-list entry is established as the targetaddress space and host access-register translationis completed.

Exceptions during HostAccess-Register TranslationThe exceptions which can be encountered duringthe host-access-register-translation process andtheir priority are shown in the section “Access

Exceptions” on page 6-4 in Chapter 6,“Interruptions,” on page 6-1.

Linkage StackThe linkage stack is not provided in ESA/XC.

Sequence of Storage ReferencesThe ESA/390 definition of the effects which canbe observed in storage due to overlappedoperations and piecemeal execution of a CPUprogram apply to ESA/XC as well.

However, in interpreting the definition containedin IBM Enterprise Systems Architecture/390Principles of Operation for ESA/XC, references tovirtual storage or virtual addresses in thatpublication apply instead to real storage, realaddresses (type-R and type-A) and absoluteaddresses in ESA/XC. Additionally, references inthat publication to the following do not apply toESA/XC: the real mode, the secondary-spacemode, and the home-space mode; ART-table andDAT-table fetches; and ALB entries.



Chapter 6. Interruptions

Interruption Action . . . . . . . . . . . 6-1Exceptions Associated with the PSW. . . . . 6-1

Early Exception Recognition . . . . . . 6-1Program Interruption . . . . . . . . . . . 6-1

Program-Interruption Conditions . . . . . . 6-1Addressing-Capability Exception . . . . . 6-2ALEN-Translation Exception . . . . . . 6-2ALET-Specification Exception . . . . . . 6-2Privileged-Operation Exception . . . . . 6-2Protection Exception . . . . . . . . . 6-3Special-Operation Exception . . . . . . 6-3Specification Exception . . . . . . . . 6-3

Multiple Program-Interruption Conditions . . . 6-3Access Exceptions . . . . . . . . . . 6-4ASN-Translation Exceptions. . . . . . . 6-4

This chapter describes how the interruptionmechanism for ESA/XC differs from that definedfor ESA/390. Except as described in the followingsection, the definition for interruptions providedin Chapter 6 of IBM Enterprise SystemsArchitecture/390 Principles of Operation applies toESA/XC as well.

Interruption ActionExcept as described in this section, theinterruption action in ESA/XC is the same asdefined for ESA/390.

During an interruption, the old PSW andinterruption parameters are stored in, and thenew PSW fetched from, the host-primary addressspace.

Exceptions Associated with thePSWIn addition to those defined in ESA/390, ESA/XCincludes some additional error conditions thatcause recognition of PSW-format errors when theerroneous information is introduced into the PSW.Error conditions that are recognized as part of theexecution of the next instruction are the same asdefined in ESA/390.

Early Exception RecognitionIn addition to the error conditions defined inESA/390, a program interruption for aspecification exception occurs immediately afterthe PSW becomes active if a one is introducedinto bit positions 5 or 16 of the PSW.

For these additional causes, interruption occurs asdefined in ESA/390 for other PSW-format errorsthat are recognized early.

Program InterruptionProgram interruptions follow the definition inESA/390 except as described in this section.

Program-Interruption ConditionsThe following is a detailed description of eachprogram-interruption condition that is eitherrecognized only in ESA/XC, or is defineddifferently in ESA/XC that it is in ESA/390.

The following program-interruption conditionsthat are defined in ESA/390 are never recognizedin ESA/XC:v AFX-translation exceptionv ALE-sequence exceptionv ASN-translation-specification exceptionv ASTE-sequence exceptionv ASTE-validity exceptionv ASX-translation exceptionv EX-translation exceptionv Extended-authority exceptionv LX-translation exceptionv Page-translation exceptionv PC-translation-specification exceptionv Primary-authority exceptionv Secondary-authority exceptionv Segment-translation exceptionv Space-switch eventv Stack-empty exceptionv Stack-full exceptionv Stack-operation exceptionv Stack-specification exceptionv Stack-type exception

Any other ESA/390 program-interruptionconditions not described in one of the followingsections is defined in ESA/XC in the same waythat it is defined for ESA/390 except that theESA/390 definition may include causes notapplicable to ESA/XC because the relatedfacilities are not provided.

The addressing-capability exception, defined inthe following section, is recognized only inESA/XC.


Addressing-Capability ExceptionAn addressing-capability exception is recognizedduring host access-register translation when theaccess-list-entry token used is correctly formedbut designates a host access-list entry that is inthe revoked state.

The access-list-entry token being translated isstored at real locations 168-171. If theaccess-list-entry token was obtained from anaccess register, the number of the access register isstored in bit positions 4-7 at real location 160, andbits 0-3 are set to zeros. If the access-list-entrytoken was obtained from the parameter list for ahost service, then zeros are stored in bit positions0-7 at real location 160.

The operation is terminated.

The instruction-length code is 1, 2 or 3.

The addressing-capability exception is indicatedby a program-interruption code of 0136 hex (or01B6 hex if a concurrent PER event is indicated).

Programming Note: An addressing-capabilityexception indicates that the program's authorityto access an address space has been revoked bythe owner of that address space. Depending onthe programs involved, this exception may resultfrom normal operation and does not necessarilyindicate a failure on the part of the programreceiving the exception.

ALEN-Translation ExceptionAn ALEN-translation exception is recognizedduring host access-register translation when theaccess-list-entry token used is correctly formedbut does not designate a host access-list entry thatis in either the valid or revoked state.

The access-list-entry token being translated isstored at real locations 168-171. If theaccess-list-entry token was obtained from anaccess register, the number of the access register isstored in bit positions 4-7 at real location 160, andbits 0-3 are set to zeros. If the access-list-entrytoken was obtained from a host-service parameterlist, then zeros are stored in bit positions 0-7 atreal location 160.

The operation is nullified.

The instruction-length code is 1, 2, or 3.

The ALEN-translation exception is indicated by aprogram-interruption code of 0029 hex (or 00A9hex if a concurrent PER event is indicated).

Programming Note: An ALEN-translationexception indicates that the program attempted touse a correctly formed but currently-unassignedALET. The ALET may have been associated witha valid host access-list entry that wassubsequently deallocated.

ALET-Specification ExceptionAn ALET-specification exception is recognizedduring host access-register translation when theaccess-list-entry token used is not acorrectly-formed ALET.

The operation is suppressed.

The instruction-length code is 1, 2, or 3.

The ALET-specification exception is indicated by aprogram-interruption code of 0028 hex (or 00A8hex if a concurrent PER event is indicated).

Programming Note: An ALET-specificationexception indicates that the program attempted touse as an ALET a 32-bit value that is never validfor use as an ALET. That is, the value used isnever assigned by the host as the selection ALETfor a valid or revoked host access-list entry. (Thisis in contrast to an ALEN-translation-exceptioncondition, which indicates that the programattempted to use an ALET that might be assignedto a host access-list entry, but currently is not.)Often, this exception indicates that the programloaded an access register from storage locationsnot currently containing an ALET value providedby the host.

Privileged-Operation ExceptionThe definition for the privileged-operationexception is the same as for ESA/390, except that:v No privileged-operation exception is recognized

if the INSERT ADDRESS SPACE CONTROLinstruction is executed when theextraction-authority control, bit 4 of controlregister 0, is zero.

v No privileged-operation exception is recognizedif bits 20-23 of the second-operand address ofthe SET ADDRESS SPACE CONTROL or SETADDRESS SPACE CONTROL FAST instructionshave the value 0011. Instead, a specificationexception is recognized.


Protection ExceptionThe definition for the protection exception is thesame as for ESA/390, except as stated in thefollowing.

In ESA/XC, a protection exception is notrecognized due to access-list-controlled protectionor page protection as defined in ESA/390.Instead, a protection exception is recognized forhost access-list-controlled protection or host pageprotection when either of the following is true:1. Host Page Protection: The CPU attempts to

store into, or change explicitly the storage keyof, a 4K-byte block of storage that has hostpage protection applied.

2. Host Access-List-Controlled Protection: The CPUattempts a store access, or an explicitstorage-key alteration using an ALET thatdesignates a host access-list entry that permitsonly fetch accesses.

If the exception is due to host page protection orhost access-list-controlled protection, theoperation is terminated. However, if thesuppression-on-protection facility is installed, theoperation may be suppressed (except for thecondition code) as described in “Suppression onProtection” on page 3-5. Otherwise, the operationis suppressed or terminated as defined forESA/390.

Special-Operation ExceptionA special-operation exception is recognized whenexecution of a SET ADDRESS SPACE CONTROLor SET ADDRESS SPACE CONTROL FASTinstruction that is to set the access-register modeis attempted and the address-space-functioncontrol, bit 15 of control register 0, is zero.

The operation is suppressed.

The instruction-length code is 2.

The special-operation exception is indicated by aprogram-interruption code of 0013 hex (or 0093hex if a concurrent PER event is indicated).

Specification ExceptionThe specification exception is defined as inESA/390, except that SET SYSTEM MASK doesnot give a specification exception due to bit 1 ofcontrol register 0 being one. In addition, aspecification exception is recognized in ESA/XCwhen either of the following is true:

1. A one is introduced into bit position 5 or 16 ofthe PSW. This is handled as an early PSWspecification exception.

2. Bits 22-23 of the second-operand address ofSET ADDRESS SPACE CONTROL or SETADDRESS SPACE CONTROL FAST are not 00or 10.

The execution of the instruction identified by theold PSW is suppressed. However, for early PSWspecification exceptions (causes 1-3 in IBMEnterprise Systems Architecture/390 Principles ofOperation, and cause 1 previously described) theoperation that introduces the new PSW iscompleted, but an interruption occursimmediately thereafter.

When the exception is recognized because of anearly PSW specification exception (causes 1-3 inIBM Enterprise Systems Architecture/390 Principles ofOperation, and cause 1 previously described), andthe exception has been introduced by LOAD PSWor an interruption, the ILC is 0. When theexception is introduced by SET SYSTEM MASKor by STORE THEN OR SYSTEM MASK, the ILCis 2.

Multiple Program-InterruptionConditionsAs in ESA/390, except for PER events, whenmultiple program-interruption conditions exist,only the condition having the highest priority isindicated in the interruption code. When twoconditions have the same priority, it isunpredictable which is indicated.

The priority of all program-interruptionconditions other than PER events and exceptionsassociated with some of the more complex controlinstructions is the same as defined in Figure 6-4of IBM Enterprise Systems Architecture/390Principles of Operation. In that figure, all exceptionsassociated with references to storage for aparticular instruction halfword or a particularoperand byte are grouped as a single entry called“access exceptions”. Figure 6-1 on page 6-4 of thispublication lists the priority of access exceptionsfor a single access. Thus, Figure 6-4 of IBMEnterprise Systems Architecture/390 Principles ofOperation specifies the priority of anaccess-exception condition in relation to otherconditions detected in the operation, andFigure 6-1 on page 6-4 of this publication specifieswhich of several access exceptions, encounteredeither in the access of a particular portion of an

Chapter 6. Interruptions 6-3

instruction or in any particular access associatedwith an operand, has highest priority.

The priority for exceptions occurring as part oftracing is the same as defined in Figure 6-7 ofIBM Enterprise Systems Architecture/390 Principles ofOperation.

For some instructions, the priority is shown in theindividual instruction description.

Access ExceptionsThe access exceptions consist of those exceptionsthat can be encountered while using an absolute,instruction, logical, or real address to accessstorage. Thus, in the access-register mode, theexceptions are:1. ALET specification

2. ALEN translation3. Addressing capability4. Protection (host access-list controlled)5. Addressing6. Protection (key-controlled, host page, and

low-address)

When in the primary-space mode, onlyexceptions 5 and 6 can be encountered.

Additionally, the instruction INVALIDATE PAGETABLE ENTRY can encounter atranslation-specification exception.

ASN-Translation ExceptionsNone of the ESA/390 ASN-translation exceptionsis applicable to ESA/XC.

A. Protection exception (low-address protection) due to a store-type operand reference with an effectiveaddress in the range 0-511.

B.1.A.1 ALET-specification exception due to an incorrectly-formed ALET.

B.1.A.2 ALEN-translation exception due to an ALET not selecting a host access-list entry in either the valid orrevoked states.

B.1.B Translation-specification exception due to invalid encoding of bits 8-12 of control register 0. Thisexception is applicable only to the execution of INVALIDATE PAGE TABLE ENTRY.

B.1.C Addressing-capability exception due to an ALET designating a host access-list entry in the revoked state.

B.2. Protection exception (host access-list controlled protection) due to a store-type operand reference using ahost access-list entry that permits read-only access.

B.3. Addressing exception for access to instruction or operand.

B.4. Protection exception (host page protection) due to a store-type operand reference to an address that isprotected by the host against stores.

B.5. Protection exception (key-controlled protection) due to an attempt to access a protected instruction oroperand location.

Figure 6-1. Priority of Access Exceptions


Chapter 7. Instructions

ESA/390 Instructions Not Provided . . . . . . 7-1Modified ESA/390 Instructions . . . . . . . 7-1

DIAGNOSE . . . . . . . . . . . . . 7-1INSERT ADDRESS SPACE CONTROL . . . . 7-1

Resulting Condition Code . . . . . . . 7-2INSERT STORAGE KEY EXTENDED . . . . 7-2INVALIDATE PAGE TABLE ENTRY . . . . . 7-2LOAD ADDRESS EXTENDED . . . . . . . 7-2LOAD PSW . . . . . . . . . . . . . 7-2LOAD USING REAL ADDRESS . . . . . . 7-2PURGE ALB . . . . . . . . . . . . . 7-2PURGE TLB . . . . . . . . . . . . . 7-2RESET REFERENCE BIT EXTENDED . . . . 7-3RESUME PROGRAM . . . . . . . . . . 7-3SET ADDRESS SPACE CONTROL and SETADDRESS SPACE CONTROL FAST . . . . . 7-3

Condition Code. . . . . . . . . . . 7-3Program Exceptions . . . . . . . . . 7-3

SET STORAGE KEY EXTENDED . . . . . . 7-4SET SYSTEM MASK . . . . . . . . . . 7-4SIGNAL PROCESSOR . . . . . . . . . 7-4STORE THEN OR SYSTEM MASK . . . . . 7-4STORE USING REAL ADDRESS . . . . . . 7-4TEST ACCESS . . . . . . . . . . . . 7-4

Resulting Condition Code . . . . . . . 7-5TEST BLOCK . . . . . . . . . . . . 7-5TEST PROTECTION . . . . . . . . . . 7-5

Resulting Condition Code . . . . . . . 7-6Program Exceptions . . . . . . . . . 7-6

TRACE . . . . . . . . . . . . . . 7-6TRAP . . . . . . . . . . . . . . . 7-6

This chapter describes the operation ofinstructions, other than the instructions forinput/output, in ESA/XC as compared toESA/390.

Except as specified in the following section,ESA/XC provides all general, decimal, floatingpoint, and control instructions provided byESA/390, and these instructions operate asdescribed in Chapters 7 to 10, 18 and 19 of IBMEnterprise Systems Architecture/390 Principles ofOperation.

ESA/390 Instructions NotProvidedThe following instructions are provided inESA/390 but are not provided in ESA/XC:v BRANCH AND STACKv BRANCH IN SUBSPACE GROUPv EXTRACT PRIMARY ASN

v EXTRACT SECONDARY ASNv EXTRACT STACKED REGISTERSv EXTRACT STACKED STATEv INSERT VIRTUAL STORAGE KEYv LOAD ADDRESS SPACE PARAMETERSv LOAD REAL ADDRESSv MODIFY STACKED STATEv MOVE TO PRIMARYv MOVE TO SECONDARYv PROGRAM CALLv PROGRAM RETURNv PROGRAM TRANSFERv SET CLOCKv SET SECONDARY ASNv START INTERPRETIVE EXECUTIONv TRAP2v TRAP4

An operation exception is recognized on anattempt to execute any of the instructionsdescribed previously.

Modified ESA/390 InstructionsThe following sections describe the operation ofinstructions that operate differently in ESA/XCthan in ESA/390.

DIAGNOSEThe DIAGNOSE instruction is used in avirtual-machine environment to request servicesfrom the host. Operation of the DIAGNOSEinstruction in an ESA/XC virtual machine isdocumented in the publication z/VM: CPProgramming Services.

INSERT ADDRESS SPACECONTROLThe address-space-control bit, bit 17 of the currentPSW, is placed in bit position 22 of the generalregister designated by the R1 field. Bits 16-21 and23 of the register are set to zeros, and bits 0-15and 24-31 of the register remain unchanged. Theaddress-space-control bit is also used to set thecondition code.

Bits 16-23 and 28-31 of the instruction are ignored.


||

Resulting Condition Code0 PSW bit is 17 zero (indicating

primary-space mode)1 --2 PSW bit 17 is one (indicating

access-register mode)3 --

Programming Note: See the programming notesfor the INSERT ADDRESS SPACE CONTROLinstruction in IBM Enterprise SystemsArchitecture/390 Principles of Operation.

INSERT STORAGE KEYEXTENDEDThis instruction operates as defined for ESA/390,with the following addition:

When the CPU is in the primary-space mode, theaddress of the 4K-byte block designated by thecontents of the general register R2 is ahost-primary real address. When the CPU is inthe access-register mode, the address of the4K-byte block designated by the contents ofgeneral register R2 is an AR-specified real address,interpreted as being within the address spacespecified by the access register designated by theR2 field.

INVALIDATE PAGE TABLE ENTRYThis instruction operates as defined for ESA/390,with the following additions:

The real address formed from the page-tableorigin contained in the register designated by theR1 field and the page index contained in theregister designated by the R2 field is treated as ahost-primary real address.

Programming Note: In ESA/XC, (guest) DAT isnot provided and (guest) TLB entries are neverformed. This instruction provides little utility inESA/XC; the setting of a bit in storage can beaccomplished more efficiently using the ORinstruction. On some models, the INVALIDATEPAGE TABLE ENTRY instruction requires asignificant amount of time, and may cause aperformance degradation.

LOAD ADDRESS EXTENDEDThe operation is performed as defined forESA/390, except that the value placed in accessregister R1 is as shown in the following table:

PSWBit 17

Value Placed in Access Register R1

0 00000000 hex (zeros in bits positions 0-31)

1 If B2 field is zero: 00000000 hex (zeros in bitpositions 0-31)

If B2 field is nonzero: contents of accessregister B2

LOAD PSWThis instruction operates as defined for ESA/390,with the following additional special conditions:

Special Conditions: The value that is to beloaded by the instruction is not checked forvalidity before it is loaded. However, immediatelyafter loading, a specification exception isrecognized and a program interruption occurs ifthe newly loaded PSW contains a one in bitposition 5 or 16. In these cases, the operation iscompleted, and the resulting instruction-lengthcode is zero. (These reasons for a specificationexception are in addition to those described inIBM Enterprise Systems Architecture/390 Principles ofOperation.)

LOAD USING REAL ADDRESSThis instruction operates as defined for ESA/390,with the following addition:

The contents of the general register designated bythe R2 field are treated as a host-primary realaddress.

PURGE ALBThe instruction is executed as a no-operation.

Programming Note: In ESA/XC, (guest) ART isnot provided and (guest) ALB entries are neverused. This instruction performs no useful functionin the ESA/XC mode. On some models, thisinstruction requires a significant amount of time,and may cause a performance degradation, so itsuse should be avoided.

PURGE TLBThe instruction is executed as a no-operation.

Programming Note: In ESA/XC, (guest) DAT isnot provided and (guest) TLB entries are neverused. This instruction performs no useful functionin the ESA/XC mode. On some models, this


instruction requires a significant amount of time,and may cause a performance degradation, so itsuse should be avoided.

RESET REFERENCE BITEXTENDEDThis instruction operates as defined for ESA/390,with the following additions:


The reference to the storage key is subject to hostpage protection and host access-list-controlledprotection.

RESUME PROGRAMIn ESA/XC, bit 16 of the PSW field in the secondoperand must be zero; otherwise, a specificationexception is recognized. This exception has thesame priority as the special-operation exceptionbecause of the attempt to set bit 17 of the PSWfield to one when bit 15 of control register 0 iszero.

SET ADDRESS SPACE CONTROLand SET ADDRESS SPACECONTROL FASTBits 20-23 of the second-operand address are usedas a code to set the address-space-control bit inthe PSW. The second-operand address is not usedto address data; instead, bits 20-23 form the code.Bits 0-19 and 24-31 of the second-operand addressare ignored. Bits 20, 21 and 23 of thesecond-operand address must be zeros; otherwisea specification exception is recognized. However,in the problem state, a privileged-operationexception may be recognized instead of aspecification exception.

The following table summarizes the operation ofSET ADDRESS SPACE CONTROL and SETADDRESS SPACE CONTROL FAST:

Code Name of Mode Result in PSWbit 17

0000 Primary space 0

0010 Access register 1

Any other Invalid Unchanged

The address-space-function control, bit 15 ofcontrol register 0, must be one when theoperation is to set the access-register mode;otherwise a special-operation exception isrecognized.

For SET ADDRESS SPACE CONTROL, aserialization and checkpoint-synchronizationfunction is performed before the operation beginsand again after the operation is completed. Thisfunction is not performed for SET ADDRESSSPACE CONTROL FAST.

Special Conditions: The priority of recognition ofprogram exceptions for the instruction is shownin Figure 7-1.

Condition CodeThe code remains unchanged.

Program Exceptionsv Operation (for SET ADDRESS SPACE

CONTROL FAST, if the set-address-space-control-fast facility is not installed)

v Privileged operationv Special operationv Specification

1.-6. Exceptions with the same priority as thepriority of program-interruption conditionsfor the general case.

7. Access exceptions for the second instructionhalfword.

8. Special-operation exception due to theaddress-space-function control, bit 15 ofcontrol register 0, being zero on an attemptto set access-register mode.

9. Specification exception due to non-zerovalue in bit positions 20, 21 or 23 of thesecond-operand address. In the problemstate, a privileged-operation exception maybe recognized instead of a specificationexception.

Figure 7-1. Priority of Execution: SET ADDRESSSPACE CONTROL and SET ADDRESS SPACECONTROL FAST

Chapter 7. Instructions 7-3

Programming Note: See the programming notesfor the SET ADDRESS SPACE CONTROL andSET ADDRESS SPACE CONTROL FASTinstructions in the IBM Enterprise SystemsArchitecture/390 Principles of Operation.

SET STORAGE KEY EXTENDEDThis instruction operates as defined for ESA/390,with the following additions:


The reference to the storage key is subject to hostpage protection and host access-list-controlledprotection.

SET SYSTEM MASKThis instruction operates as defined for ESA/390,with the following modifications:

The SSM-suppression control (bit 1 of controlregister 0) is not checked, and nospecial-operation exception is recognized if thecontrol is one.

Special Conditions: The value that is to beloaded into the PSW is not checked for validitybefore it is loaded. However, immediately afterloading, a specification exception is recognizedand a program interruption occurs if the PSWcontains a one in bit position 5. In this case, theinstruction is completed, and theinstruction-length code is set to 2. (This reason fora specification exception is in addition to thosedescribed in IBM Enterprise SystemsArchitecture/390 Principles of Operation.)

SIGNAL PROCESSORThis instruction operates as defined for ESA/390with the following addition:

For the “store status at address” order, theaddress specified in the parameter register is ahost-primary absolute address.

STORE THEN OR SYSTEM MASKThis instruction operates as defined for ESA/390,with the following additional special conditions:

Special Conditions: The value that is to beloaded into the PSW is not checked for validitybefore it is loaded. However, immediately afterloading, a specification exception is recognizedand a program interruption occurs if the PSWcontains a one in bit position 5. In this case, theinstruction is completed, and theinstruction-length code is set to 2. (This reason fora specification exception is in addition to thosedescribed in IBM Enterprise SystemsArchitecture/390 Principles of Operation.)

STORE USING REAL ADDRESSThis instruction operates as defined for ESA/390,with the following addition:

The contents of the general register designated bythe R2 field are treated as a host-primary realaddress.

TEST ACCESSThe access-list-entry token (ALET) in accessregister R1 is tested for exceptions recognizedduring host access-register translation (ART). TheALET is also tested for being 00000000 hex.

The contents of bits 0-15 of general register R2should be 0001 hex.

When the R1 field is 0, the actual contents ofaccess register 0 are used in ART, instead of the00000000 hex that is usually used.

Bits 16-31 of general register R2 are ignored. Bits16-23 of the instruction are ignored.

The operation does not depend on the translationmode; bit 17 of the PSW is ignored.

When the ALET in access register R1 is 00000000hex, the instruction is completed by settingcondition code 0.

When the ALET in access register R1 is other than00000000 hex, the ART process is applied to theALET. When a situation exists that wouldnormally cause one of the exceptions shown inthe following table, the instruction is completedby setting condition code 3.


Exception Name CauseAddressing capability ALET is correctly formed and

selects a host access-list entryin the revoked state

ALET specification ALET is not correctly formedALEN translation ALET is correctly formed but

does not select a hostaccess-list entry in either thevalid or revoked state

When ART is completed without one of theprevious situations being recognized, theinstruction is completed by setting condition code2. ART is described in the section “HostAccess-Register Translation” on page 5-6.

If the instruction is executed with the contents ofbits 0-15 of general register R2 not 0001 hex, theresulting condition code is unpredictable.

Special Conditions: The operation is performedonly when the address-space-function control, bit15 of control register 0, is one. When the

address-space-function control is zero, it isunpredictable whether a special-operationexception is recognized.

The priority of recognition of program exceptionsfor the instruction is shown in Figure 7-2.

Resulting Condition CodeWhen the contents of bits 0-15 of general registerR2 are 0001 hex:0 Access-list-entry token (ALET) is 00000000

hex1 --2 ALET is not 00000000 hex and does not

cause exceptions in ART3 ALET causes exceptions in ART

When the contents of bits 0-15 of general registerR2 are not 0001 hex, the resulting condition codeis unpredictable.

Program Exceptions:v Special operation

TEST BLOCKThis instruction operates as defined for ESA/390,with the following additions:

When the CPU is in the primary-space mode, theaddress of the 4K-byte block designated by thecontents of the general register R2 is ahost-primary real address. When the CPU is inthe access-register mode, the address of the4K-byte block designated by the contents ofgeneral register R2 is an AR-specified real address,

interpreted as being within the address spacespecified by the access register designated by theR2 field.

The access to the block designated by the secondoperand address is subject to host page protectionand host access-list-controlled protection.

TEST PROTECTIONThe location designated by the first-operandaddress is tested for protection exceptions byusing the access key specified in bits 24-27 of thesecond-operand address.

1.-6. Exceptions with the same priority as the priority of program-interruption conditions for the general case.

7.A Access exceptions for the second instruction halfword.

7.B Special-operation exception due to the address-space-function control, bit 15 of control register 0, beingzero.

8. Condition code 0 due to the access-list-entry-token (ALET) being 00000000 hex.

9. Condition code 3 due to the ALET not being correctly formed.

10. Condition code 3 due to the ALET not selecting a host access-list entry that is in the valid or revokedstate.

11. Condition code 3 due to the ALET selecting a host access-list entry that is in the revoked state.

12. Condition code 2

Figure 7-2. Priority of Execution: TEST ACCESS

Chapter 7. Instructions 7-5

|||

The second-operand address is not used toaddress data; instead, bits 24-27 of the addressform the access key to be used in testing. Bits 0-23and 28-31 of the second-operand address areignored.

The first-operand address is a logical address.When the CPU is in the access-register mode(when PSW bit 17 is one), the first-operandaddress is subject to translation by means of theaccess-register-translation process. ART applies tothe access register designated by the B1 field todetermine the address space containing the firstoperand.

When ART is performed and a situation existsthat would normally cause one of the exceptionsshown in the following table, the instruction iscompleted by setting condition code 3.

Exception Name CauseAddressing capability ALET is correctly formed and

selects a host access-list entryin the revoked state

ALET specification ALET is not correctly formedALEN translation ALET is correctly formed but

does not select a hostaccess-list entry in either thevalid or revoked state

When the access register contains 00000000 hex,the first operand is contained in the host-primaryaddress space and ART does not performtranslation through the host access list. When theB1 field designates access register 0, ART treatsthe access register as containing 00000000 hex anddoes not examine the actual contents of the accessregister.

When translation of the first-operand address canbe completed, or when the CPU is in theprimary-space mode, the storage key for the blockdesignated by the first-operand address is testedagainst the access key specified in bits 24-27 ofthe second-operand address, and the conditioncode is set to indicate whether store and fetchaccesses are permitted, taking into account allapplicable protection mechanisms. Thus, forexample, if low-address protection is active andthe first-operand effective address is less than 512,then a store access is not permitted. Host pageprotection, host access-list-controlled protection,storage-protection override, and fetch-protectionoverride are also taken into account.

The contents of storage, including the change bit,are not affected. Depending on the model, thereference bit for the first-operand address may beset to one, even for the case in which the locationis protected against fetching.

Resulting Condition Code0 Fetching permitted; storing permitted1 Fetching permitted; storing not permitted2 Fetching not permitted; storing not

permitted3 ALET causes exceptions in ART

Program Exceptionsv Privileged operation

TRACEThis instruction operates as defined for theESA/390, with the following addition:

The contents of bits 1-29 of control register 12,with two zero bits appended on the right, aretreated as a host-primary real address.

TRAPThe TRAP2 and TRAP4 instructions are notoperational in ESA/XC. They always result in anoperation or special-operation exception.


Chapter 8. Machine-Check Handling

Handling of Machine Checks . . . . . . . . 8-1Validation. . . . . . . . . . . . . . 8-1

Machine-Check Extended Interruption Information 8-1Failing-Storage Address and ASIT . . . . . 8-1

This chapter describes how the handling ofmachine checks for ESA/XC differs from thatdefined for ESA/390. Except as described in thefollowing section, the definition formachine-check handling provided in Chapter 11of IBM Enterprise Systems Architecture/390Principles of Operation applies to ESA/XC as well.

Handling of Machine ChecksThe overall handling of machine checks inESA/XC is the same as defined for ESA/390,except that ESA/XC provides automaticvalidation of certain register entities. Thisvalidation is described in the next section.

ValidationIn ESA/XC, certain register entities areautomatically validated as part of themachine-check interruption sequence after theoriginal contents of the registers are placed in theappropriate save areas. After validation, thecontents of these registers are restored to thevalues placed in the corresponding save areas,even if the associated machine-check-interruption-code validity bit for the logged-out copy is zero.The register entities for which this automaticvalidation is performed are:v General registersv Access registersv Control registersv Floating-point registers 0, 2, 4, and 6v Clock comparatorv CPU timerv Floating-point registers 1, 3, 5, and 7-15 if

floating-point extensions are installed

Machine-Check ExtendedInterruption InformationIn ESA/XC, all of the machine-check extendedinterruption information defined for ESA/390 isprovided in the same cases as defined forESA/390. In addition, ESA/XC provides a

failing-storage ASIT for certain interruptions, asdefined in the next section.

Failing-Storage Address and ASITAs defined in ESA/390, when storage erroruncorrected, storage error corrected, orstorage-key error uncorrected is indicated in themachine-check-interruption code, the associatedaddress, called the failing-storage address, isstored in bit positions 1-31 of the word at reallocation 248 and bit 0 of this word is set to zero.In addition, an indication of the address space inwhich the error occurred, called thefailing-storage ASIT, is stored at locations 256-263.The failing-storage address and failing-storageASIT fields are valid only if thefailing-storage-address validity bit, bit 24 of themachine-check-interruption code, is one.

When a storage error or storage-key error occursin the host-primary address space, zeros arestored as the failing-storage ASIT. When thestorage error or storage-key error occurs in anaddress space other than the host-primaryaddress space, the ASIT for the address space isstored as the failing-storage ASIT.



Chapter 9. Input/Output

Handling of Addresses for I/O . . . . . . . 9-1

This chapter describes how input/outputprocessing for ESA/XC differs from that definedfor ESA/390. Except as described in this chapter,the definition for I/O instructions, I/O functions,I/O interruptions and I/O support functionsprovided in Chapters 13 to 17 of IBM EnterpriseSystems Architecture/390 Principles of Operationapplies to ESA/XC as well.

Handling of Addresses for I/OExcept for the logical-address operands of the I/Oinstructions, all main-storage addresses used bythe channel subsystem in performing I/Ooperations, or in performing I/O-measurementoperations, refer to the host-primary addressspace. That is, they are host-primary absolute orhost-primary real addresses, as appropriate.

More specifically, the following addresses arehost-primary absolute addresses:v Address limit specified in SET ADDRESS

LIMIT

v Measurement-block origin specified in SETCHANNEL MONITOR

v Channel-program address in operation requestblock

v Data address in channel-command word(CCW)

v CCW address in a CCW specifying transfer inchannel

v Indirect-data-address word (IDAW) address ina CCW specifying indirect data addressing

v Data address in IDAWv CCW address in subchannel status wordv Failing-storage address in format-0

extended-status wordv Addresses of PSW and first two CCWs used for

initial program loading

The following addresses are host-primary realaddresses:v Address into which TEST PENDING

INTERRUPTION stores when thesecond-operand address is zero

v Addresses into which information is stored andfrom which the PSW is fetched on an I/Ointerruption



Appendix. Comparison between ESA/390 and ESA/XC

This appendix provides1. A list of the facilities that are new in ESA/XC

and not provided in ESA/3902. A description of the handling in ESA/XC of

the facilities available in ESA/3903. A list of changes between ESA/XC and

ESA/390.

New Facilities in ESA/XCThe following facilities are new in ESA/XC andare not provided in ESA/390.

DAT-Off Access-RegisterAddressingA variation of the ESA/390 access-registeraddressing facility is provided that operates inDAT-off virtual machines, allowing exploitationby z/VM applications. As in ESA/390, sixteenaccess registers and a translation mode called theaccess-register mode allow designation of storageoperands in up to sixteen different address spacesby means of the B fields of instructions and the Rfields of certain instructions. A host-managedtable called the host access list controls theaddress spaces that can be accessed by means ofthe access registers. Through the use of hostservices, entries in the host access list can beestablished to provide addressability to addressspaces owned by the virtual machine as well asaddress spaces owned by other virtual machines,subject to appropriate authorization. Other hostservices allow the addressing capability providedby an entry to be relinquished when no longerneeded.

Multiple Absolute-StorageAddress SpacesHost services are provided that allow a virtualmachine to obtain large amounts of storage in theform of multiple data-only absolute-storageaddress spaces, each up to 2 gigabytes in size.Previously, the storage available to an applicationprogram was limited to a single 2 gigabyteabsolute-storage address space. With this facility,an application program has access to a practicallyunlimited amount of application storage. Theadditional address spaces are accessed by meansof access-register addressing.

Address-Space SharingA virtual machine can use host services to makethe address spaces that it owns accessible byother virtual machines on the z/VM system. Thiscapability provides the basis for high-performancesharing of large amounts of data within a z/VMsystem. The shared access can be subsequentlyrevoked when address-space sharing is no longerappropriate. The sharing virtual machines accessthe shared address spaces using access-registeraddressing.

Comparison of FacilitiesTable A-1 shows the facilities offered in ESA/390and how each facility is provided in ESA/XC.

Table A-1. Availability of ESA/390 Facilities in ESA/XC

ESA/390 Facility*Availabilityin ESA/XC

Access registersBimodal addressingCalled-space identificationChannel subsystem I/ODual address spaceDynamic address translationExpanded storage

B1

B-B--O

Home address spaceInterpretive executionLinkage stackMove inverseMove pagePage protectionPrivate space

---OP2

-3

-4

Square rootStorage-protection overrideSubspace groupSuppression on ProtectionTracing31-bit logical addressing31-bit real and absolute addressing

OO-O6

P5

BB

© Copyright IBM Corp. 1991, 2017 A-1

Table A-1. Availability of ESA/390 Facilities inESA/XC (continued)

ESA/390 Facility*Availabilityin ESA/XC

Explanation:

* All basic ESA/390 facilities not otherwise listed in thistable are also basic in ESA/XC. All optional ESA/390facilities not otherwise listed in this table are also optionalin ESA/XC.

- Not provided in ESA/XC.

1 The ESA/390 access-register-translation process is replacedby the host-access-register-translation process in ESA/XC.As viewed by application programs, these two translationprocesses offer comparable function.

2 Movement of data from main storage to main storage isprovided, but movement of data to or from expandedstorage is not. Either the move-page facility 1 or themove-page facility 2 is provided in ESA/XC.

3 The host has the ability to make selected 4K-byte blocksand the associated storage key read-only to an ESA/XCvirtual machine. However, page protection per se is notprovided in ESA/XC.

4 In ESA/390, the private-space facility is used to eliminatespecial treatment of low addresses in data-only addressspaces so that all locations in such address spaces areavailable for application use. It is standard in ESA/XCthat all locations in data-only address spaces are availablefor the application.

5 All parts of the tracing facility are provided except forASN tracing.

6 Although the suppression-on-protection facility is(optionally) provided in ESA/XC, its usefulness is greatlydiminished since no protection-exception conditions areguaranteed to suppress in ESA/XC.

B Basic in ESA/XC.

P Partially available in ESA/XC.

O Provided as an optional facility in both ESA/390 andESA/XC.

Summary of Changes

Changes in Instructions ProvidedTable A-2 lists those instructions that are basic inESA/390 but are not provided in ESA/XC.

Table A-2. ESA/390 Instructions Not Provided inESA/XC

Instruction Name*Mne-monic

OpCode

BRANCH AND STACKEXTRACT PRIMARY ASNEXTRACT SECONDARY ASNEXTRACT STACKED REGISTERSEXTRACT STACKED STATE

BAKREPARESAREREGESTA

B240B226B227B249B24A

Table A-2. ESA/390 Instructions Not Provided inESA/XC (continued)

Instruction Name*Mne-monic

OpCode

INSERT VIRTUAL STORAGE KEYLOAD ADDRESS SPACE PARAMETERS 1

LOAD REAL ADDRESS 1

MODIFY STACKED STATEMOVE TO PRIMARY

IVSKLASPLRAMSTAMVCP

B223E500B1B247DA

MOVE TO SECONDARYPROGRAM CALLPROGRAM CALL FASTPROGRAM RETURNPROGRAM TRANSFERSET CLOCK 1

MVCSPCPCFPRPTSCK

DBB218B2180101B228B204

SET SECONDARY ASNSTART INTERPRETIVE EXECUTION 2

TRAPTRAP

SSARSIETRAP2TRAP4

B225B21401FFB2FF

Explanation:

* Except as indicated, in ESA/390 these instructions can beexecuted successfully only when DAT is on; otherwise, aspecial-operation exception is recognized.

1 Instruction can be executed successfully when DAT is off.

2 Instruction can be executed successfully when DAT is offbut implies the use of DAT.

Comparison of PSW FormatsIn ESA/390, PSW bit 5 is the translation (DAT)control, and bits 16 and 17 are the address-spacecontrol. PSW bits 16 and 17 are ignored whenDAT is off.

In ESA/XC, PSW bits 5 and 16 are unassigned; aone in either bit position is invalid. PSW bit 17 isthe address-space control.

Changes in Control-RegisterAssignmentsTable A-3 shows those control-register bits andfields assigned in ESA/390 but unassigned inESA/XC.

Table A-3. ESA/390 Control-Register Fields NotAssigned in ESA/XCCtrlReg Bits Name of Bit or Field

0 12527

SSM-suppression controlTOD-clock-sync controlSecondary-space controlETR Subclass mask

1 01-1922232425-31

Primary space-switch-event controlPrimary segment-table originPrimary subspace-group controlPrimary private-space controlPrimary storage-alteration-event controlPrimary segment-table length

3 16-31 Secondary ASN

A-2 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

||||||

Table A-3. ESA/390 Control-Register Fields NotAssigned in ESA/XC (continued)CtrlReg Bits Name of Bit or Field

4 0-1516-31

Authorization indexPrimary ASN

5 1-25 Primary-ASTE origin 1

7 1-1922232425-31

Secondary segment-table originSecondary subspace-group controlSecondary private-space controlSecondary storage-alteration-event controlSecondary segment-table length

8 0-15 Extended authorization index

12 30 ASN-trace control

13 01-19232425-31

Home space-switch-event controlHome segment-table originHome private-space controlHome storage-alteration-even controlHome segment-table length

14 101213-31

TOD-clock-control-override controlASN-translation controlASN-first-table origin

15 1-28 Linkage-stack entry address

Explanation:

1 This assignment applies only if bit 15 of control register 0is one. If bit 15 is zero, control register 5 contains thelinkage-table designation as in 370-XA.

Changes in Assigned StorageLocationsTable A-4 summarizes the changes in assignedstorage locations between ESA/390 and ESA/XC.

Table A-4. Changes in Assigned Storage Locations

Name of Field

Assigned Storage Locationand Length* for

ESA/390 ESA/XC

Exception ALET - 168 4

Failing-storage ASIT - 256 81

Explanation:

* The first number is the real address, the second is thelength.

- Not assigned

1 This field is assigned within the area defined as thefixed-logout area in ESA/390

Changes in ExceptionsESA/XC includes an exception, theaddressing-capability exception, that is notdefined in ESA/390. The addressing-capabilityexception may be recognized duringaccess-register translation and is indicated by aprogram-interruption code of 0136 hex.

In addition, there are several exceptions definedin ESA/390 but never recognized in ESA/XC.These exceptions are summarized in Table A-5.

Table A-5. ESA/390 Exceptions Not Recognized

Exception NameInterruptionCode (hex)

AFX-translationALE-sequenceASN-translation specificationASTE-sequenceASTE-validity

0020002A0017002C002B

ASX-translationEX-translationExtended-authorityLX-translationPage-translationPC-translation specification

00210023002D00220011001F

Primary-authoritySecondary-authoritySegment-translationSpace-switch eventStack-empty

002400250010001C0031

Stack-fullStack-operationStack-specificationStack-type

0030003400320033

Changes to Insert Address SpaceControlIn ESA/390, INSERT ADDRESS SPACECONTROL can be executed successfully onlywhen DAT is on and further, when in theproblem state, only when the extraction-authoritycontrol (bit 4 of control register 0) is one. InESA/XC, the instruction can be executedsuccessfully even though DAT is not provided,and it is not subject to the control by bit 4 ofcontrol register 0.

Changes to Resume ProgramIn ESA/390, RESUME PROGRAM can set anyvalue in PSW bits 16-17 with the properauthorization. In ESA/XC, PSW bit 16 may not beset to one.

Changes to Set Address SpaceControl (SASC) and SASC FastIn ESA/390, SET ADDRESS SPACE CONTROLand SET ADDRESS SPACE CONTROL FAST canbe executed successfully only when DAT is on.Also, SET ADDRESS SPACE CONTROL, andunpredictably SET ADDRESS SPACE CONTROLFAST, can be executed successfully in ESA/390only when the secondary-space control (bit 5 ofcontrol register 0) is one. The instructions can beused to set the primary-space mode, the

Appendix. Comparison between ESA/390 and ESA/XC A-3

secondary-space mode, the access-register modeand the home-space mode.

In ESA/XC, the instructions can be executedsuccessfully even though DAT is not provided,and they are not subject to the secondary-spacecontrol. The instructions can be used to set onlythe primary-space mode and the access-registermode. As in ESA/390, the address-space-functioncontrol (bit 15 of control register 0) must be onein order to set the access-register mode.

Changes to Set System MaskIn ESA/390, SET SYSTEM MASK can be executedsuccessfully only when the SSM-suppressioncontrol (bit 1 of control register 0) is zero. InESA/XC, bit 1 of control register 0 is not checked.

Changes to Test AccessIn ESA/390, TEST ACCESS can be executedsuccessfully only when DAT is on. In ESA/XC,the instruction can be executed successfully eventhough DAT is not provided.

Changes to TrapIn ESA/XC, TRAP2 and TRAP4 always result inan operation or special-operation exception.

A-4 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

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B-4 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Glossary

For a list of z/VM terms and their definitions, seez/VM: Glossary.

The z/VM glossary is also available through theonline z/VM HELP Facility, if HELP files areinstalled on your z/VM system. For example, todisplay the definition of the term “dedicateddevice”, issue the following HELP command:help glossary dedicated device

While you are in the glossary help file, you cando additional searches:v To display the definition of a new term, type a

new HELP command on the command line:help glossary newterm

This command opens a new help file inside theprevious help file. You can repeat this processmany times. The status area in the lower rightcorner of the screen shows how many help filesyou have open. To close the current file, pressthe Quit key (PF3/F3). To exit from the HELPFacility, press the Return key (PF4/F4).

v To search for a word, phrase, or characterstring, type it on the command line and pressthe Clocate key (PF5/F5). To find otheroccurrences, press the key multiple times.The Clocate function searches from the currentlocation to the end of the file. It does not wrap.To search the whole file, press the Top key(PF2/F2) to go to the top of the file beforeusing Clocate.

© Copyright IBM Corp. 1991, 2017 C-1

C-2 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Bibliography

See the following publications for additionalinformation about z/VM. For abstracts of thez/VM publications, see z/VM: General Information,GC24-6193.

Where to Get z/VM Informationz/VM product documentation and other z/VMinformation is available in IBM Knowledge Center- z/VM (www.ibm.com/support/knowledgecenter/SSB27U).

You can also obtain z/VM product publicationsfrom IBM Publications Center(www.ibm.com/e-business/linkweb/publications/servlet/pbi.wss).

z/VM Base LibraryOverviewv z/VM: License Information, GC24-6200v z/VM: General Information, GC24-6193v z/VM: Glossary, GC24-6195

Installation, Migration, and Servicev z/VM: Installation Guide, GC24-6246v z/VM: Migration Guide, GC24-6201v z/VM: Service Guide, GC24-6247v z/VM: VMSES/E Introduction and Reference,

GC24-6243

Planning and Administrationv z/VM: CMS File Pool Planning, Administration,

and Operation, SC24-6167v z/VM: CMS Planning and Administration,

SC24-6171v z/VM: Connectivity, SC24-6174v z/VM: CP Planning and Administration,

SC24-6178v z/VM: Enabling z/VM for OpenStack (Support for

OpenStack Liberty Release), SC24-6251v z/VM: Getting Started with Linux on z Systems,

SC24-6194v z/VM: Group Control System, SC24-6196v z/VM: I/O Configuration, SC24-6198v z/VM: Running Guest Operating Systems,

SC24-6228

v z/VM: Saved Segments Planning andAdministration, SC24-6229

v z/VM: Secure Configuration Guide, SC24-6230v z/VM: TCP/IP LDAP Administration Guide,

SC24-6236v z/VM: TCP/IP Planning and Customization,

SC24-6238v z/OS and z/VM: Hardware Configuration Manager

User's Guide, SC34-2670

Customization and Tuningv z/VM: CP Exit Customization, SC24-6176v z/VM: Performance, SC24-6208

Operation and Usev z/VM: CMS Commands and Utilities Reference,

SC24-6166v z/VM: CMS Primer, SC24-6172v z/VM: CMS User's Guide, SC24-6173v z/VM: CP Commands and Utilities Reference,

SC24-6175v z/VM: System Operation, SC24-6233v z/VM: TCP/IP User's Guide, SC24-6240v z/VM: Virtual Machine Operation, SC24-6241v z/VM: XEDIT Commands and Macros Reference,

SC24-6244v z/VM: XEDIT User's Guide, SC24-6245

Application Programmingv z/VM: CMS Application Development Guide,

SC24-6162v z/VM: CMS Application Development Guide for

Assembler, SC24-6163v z/VM: CMS Application Multitasking, SC24-6164v z/VM: CMS Callable Services Reference, SC24-6165v z/VM: CMS Macros and Functions Reference,

SC24-6168v z/VM: CMS Pipelines User's Guide and Reference,

SC24-6252v z/VM: CP Programming Services, SC24-6179v z/VM: CPI Communications User's Guide,

SC24-6180v z/VM: Enterprise Systems Architecture/Extended

Configuration Principles of Operation, SC24-6192

© Copyright IBM Corp. 1991, 2017 D-1

http://www.ibm.com/support/knowledgecenter/SSB27U

http://www.ibm.com/support/knowledgecenter/SSB27U

http://www.ibm.com/e-business/linkweb/publications/servlet/pbi.wss

v z/VM: Language Environment User's Guide,SC24-6199

v z/VM: OpenExtensions Advanced ApplicationProgramming Tools, SC24-6202

v z/VM: OpenExtensions Callable Services Reference,SC24-6203

v z/VM: OpenExtensions Commands Reference,SC24-6204

v z/VM: OpenExtensions POSIX ConformanceDocument, GC24-6205

v z/VM: OpenExtensions User's Guide, SC24-6206v z/VM: Program Management Binder for CMS,

SC24-6211v z/VM: Reusable Server Kernel Programmer's Guide

and Reference, SC24-6220v z/VM: REXX/VM Reference, SC24-6221v z/VM: REXX/VM User's Guide, SC24-6222v z/VM: Systems Management Application

Programming, SC24-6234v z/VM: TCP/IP Programmer's Reference, SC24-6239v Common Programming Interface Communications

Reference, SC26-4399v Common Programming Interface Resource Recovery

Reference, SC31-6821v z/OS: IBM Tivoli Directory Server Plug-in

Reference for z/OS, SA76-0169v z/OS: Language Environment Concepts Guide,

SA22-7567v z/OS: Language Environment Debugging Guide,

GA22-7560v z/OS: Language Environment Programming Guide,

SA22-7561v z/OS: Language Environment Programming

Reference, SA22-7562v z/OS: Language Environment Run-Time Messages,

SA22-7566v z/OS: Language Environment Writing

Interlanguage Communication Applications,SA22-7563

v z/OS MVS Program Management: AdvancedFacilities, SA23-1392

v z/OS MVS Program Management: User's Guideand Reference, SA23-1393

Diagnosisv z/VM: CMS and REXX/VM Messages and Codes,

GC24-6161v z/VM: CP Messages and Codes, GC24-6177v z/VM: Diagnosis Guide, GC24-6187

v z/VM: Dump Viewing Facility, GC24-6191v z/VM: Other Components Messages and Codes,

GC24-6207v z/VM: TCP/IP Diagnosis Guide, GC24-6235v z/VM: TCP/IP Messages and Codes, GC24-6237v z/VM: VM Dump Tool, GC24-6242v z/OS and z/VM: Hardware Configuration

Definition Messages, SC34-2668

z/VM Facilities and FeaturesData Facility Storage ManagementSubsystem for VMv z/VM: DFSMS/VM Customization, SC24-6181v z/VM: DFSMS/VM Diagnosis Guide, GC24-6182v z/VM: DFSMS/VM Messages and Codes,

GC24-6183v z/VM: DFSMS/VM Planning Guide, SC24-6184v z/VM: DFSMS/VM Removable Media Services,

SC24-6185v z/VM: DFSMS/VM Storage Administration,

SC24-6186

Directory Maintenance Facility for z/VMv z/VM: Directory Maintenance Facility Commands

Reference, SC24-6188v z/VM: Directory Maintenance Facility Messages,

GC24-6189v z/VM: Directory Maintenance Facility Tailoring

and Administration Guide, SC24-6190

Open Systems Adapter/Support Facilityv Open Systems Adapter-Express Customer's Guide

and Reference, SA22-7935v Open Systems Adapter-Express Integrated Console

Controller User's Guide, SA22-7990v Open Systems Adapter-Express Integrated Console

Controller 3215 Support, SA23-2247v Open Systems Adapter-Express3 Integrated Console

Controller Dual-Port User's Guide, SA23-2266

Performance Toolkit for VMv z/VM: Performance Toolkit Guide, SC24-6209v z/VM: Performance Toolkit Reference, SC24-6210

RACF® Security Server for z/VMv z/VM: RACF Security Server Auditor's Guide,

SC24-6212v z/VM: RACF Security Server Command Language

Reference, SC24-6213

D-2 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

v z/VM: RACF Security Server Diagnosis Guide,GC24-6214

v z/VM: RACF Security Server General User'sGuide, SC24-6215

v z/VM: RACF Security Server Macros andInterfaces, SC24-6216

v z/VM: RACF Security Server Messages and Codes,GC24-6217

v z/VM: RACF Security Server SecurityAdministrator's Guide, SC24-6218

v z/VM: RACF Security Server System Programmer'sGuide, SC24-6219

v z/VM: Security Server RACROUTE MacroReference, SC24-6231

Remote Spooling CommunicationsSubsystem Networking for z/VMv z/VM: RSCS Networking Diagnosis, GC24-6223v z/VM: RSCS Networking Exit Customization,

SC24-6224v z/VM: RSCS Networking Messages and Codes,

GC24-6225v z/VM: RSCS Networking Operation and Use,

SC24-6226v z/VM: RSCS Networking Planning and

Configuration, SC24-6227

Prerequisite ProductsDevice Support Facilitiesv Device Support Facilities: User's Guide and

Reference, GC35-0033

Environmental Record Editing andPrinting Programv Environmental Record Editing and Printing

Program (EREP): Reference, GC35-0152v Environmental Record Editing and Printing

Program (EREP): User's Guide, GC35-0151

Other PublicationsIBM Enterprise Systems Architecture/390Principles of Operation, SA22-7201IBM Enterprise Systems Architecture/370Principles of Operation, SA22-7200IBM System/370 Extended Architecture Principlesof Operation, SA22-7085

Bibliography D-3

D-4 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

Index

Aabsolute address 3-3access exceptions

priority of 7-1access registers

automatic validation of 8-1designating in instructions 5-3identification stored on a program interruption 3-8instructions for use of 5-6introduction to 5-2use of 5-3

access-list-controlled protectionnot provided in ESA/XC 3-4

access-register mode 3-6access-type indication (in host access-list entry) 5-8address

stored into by TEST PENDING INTERRUPTION 9-1summary information 3-7

address limit (specified in SET ADDRESS LIMIT) 9-1address space

AR-specified (access-register-specified) 5-2assignment of ASIT to 3-2deletion of, by subsystem reset 4-2determining space specified by ALET 5-3home, not provided in ESA/XC 5-1host-primary 3-1initial state of sharing 3-2isolation of, by subsystem reset 4-2private and shareable states 3-2

address translationsummary information 3-6

address-space control bit 4-1address-space number (ASN), not provided in ESA/XC 3-6address-space-function (ASF) control bit 5-6addressing exception, as an access exception 6-4addressing-capability exception

as an access exception 6-4AFX-translation exception, not recognized in ESA/XC 6-1ALB (ART lookaside buffer) 5-5ALE-sequence exception, not recognized in ESA/XC 6-1ALEN-translation exception

as an access exception 6-4ALET (access-list-entry token)

stored on a program interruption 3-9values treated specially by ART 5-4

ALET-specification exceptionas an access exception 6-4

AR-specified (access-register-specified) address spaces 5-2AR-specified absolute address 3-3AR-specified real address 3-3ART lookaside buffer (ALB) 5-5ASIT (address-space identification token)

in host access-list entry 5-7special value never assigned as ASIT 3-2stored on a machine-check interruption 3-9

ASN authorization, not provided in ESA/XC 3-6ASN tracing, not provided in ESA/XC 4-1ASN translation, not provided in ESA/XC 3-6ASN-first-table origin, not provided in ESA/XC A-2ASN-trace-control bit, not provided in ESA/XC A-2ASN-translation control bit, not provided in ESA/XC 5-1

ASN-translation exceptions, not recognized in ESA/XC 6-4ASN-translation-control bit, not provided in ESA/XC A-2ASN-translation-specification exception, not recognized in

ESA/XC 6-1assigned storage locations

comparison of ESA/XC with ESA/390 A-3ASTE-sequence exception, not recognized in ESA/XC 6-1ASTE-validity exception, not recognized in ESA/XC 6-1ASX-translation exception, not recognized in ESA/XC 6-1asynchronous page-fault handling option (in host access-list

entry) 5-8authorization index (AX), not provided in ESA/XC 5-1, A-2authorization mechanisms 5-1automatic validation of registers 8-1

BBAKR (BRANCH AND STACK) instruction, not provided in

ESA/XC 7-1BRANCH AND STACK (BAKR) instruction, not provided in

ESA/XC 7-1BRANCH IN SUBSPACE GROUP (BSG) instruction, not

provided in ESA/XC 7-1BSG (BRANCH IN SUBSPACE GROUP) instruction, not

provided in ESA/XC 7-1

CCCW address

in subchannel status word 9-1in TIC CCW 9-1

channel-program address, in ORB 9-1clock comparator

automatic validation of 8-1compatibility

among ESA/XC implementations 1-2of ESA/XC with ESA/390, ESA/370 and 370-XA 1-3problem-state 1-3supervisor-state 1-3

configuration 2-1control instructions 7-1control registers

assignment of 4-1automatic validation of 8-1comparison of assignments between ESA/XC and

ESA/390 A-2CPU timer

automatic validation of 8-1

DDAT (dynamic address translation), not provided in

ESA/XC 3-6data address (in CCW or IDAW) 9-1decimal instructions 7-1DIAGNOSE instruction 7-1dynamic address translation (DAT), not provided in

ESA/XC 3-6

© Copyright IBM Corp. 1991, 2017 X-1

Eearly exception recognition 6-1EPAR (EXTRACT PRIMARY ASN) instruction, not provided in

ESA/XC 7-1EREG (EXTRACT STACKED REGISTERS) instruction, not

provided in ESA/XC 7-1ESA/390 architecture

availability of facilities in ESA/XC 1-2, A-1compared with ESA/XC A-1control-register fields not defined in ESA/XC A-2instructions not provided in ESA/XC A-2relationship to ESA/XC 1-1

ESA/390 Principles of Operationrelationship of this document to 1-1

ESA/XC architecturecapabilities controlled by host 2-2compared with ESA/390 A-1compatibility with ESA/390, ESA/370 and 370-XA 1-3ESA/390 facilities included in 1-2highlights of 1-1relationship to ESA/390 1-1summary of differences from ESA/390 1-2

ESAR (EXTRACT SECONDARY ASN) instruction, notprovided in ESA/XC 7-1

ESTA (EXTRACT STACKED STATE) instruction, not providedin ESA/XC 7-1

eventspace-switch, not recognized in ESA/XC 6-1

EX-translation exception, not recognized in ESA/XC 6-1exception access identification 3-8exception ALET 3-9exceptions 6-1

access (collective program-interruption name) 6-4addressing-capability 6-2AFX-translation, not recognized in ESA/XC 6-1ALE-sequence, not recognized in ESA/XC 6-1ALEN-translation 6-2ALET-specification 6-2ASN-translation (collective program-interruption

name) 6-4ASN-translation-specification, not recognized in

ESA/XC 6-1ASTE-sequence, not recognized in ESA/XC 6-1ASTE-validity, not recognized in ESA/XC 6-1ASX-translation, not recognized in ESA/XC 6-1EX-translation, not recognized in ESA/XC 6-1extended-authority, not recognized in ESA/XC 6-1LX-translation, not recognized in ESA/XC 6-1page-translation, not recognized in ESA/XC 6-1PC-translation-specification, not recognized in

ESA/XC 6-1primary-authority, not recognized in ESA/XC 6-1priority of 6-3privileged-operation 6-2protection 6-3secondary-authority, not recognized in ESA/XC 6-1segment-translation, not recognized in ESA/XC 6-1special-operation 6-3specification 6-3stack-empty, not recognized in ESA/XC 6-1stack-full, not recognized in ESA/XC 6-1stack-operation, not recognized in ESA/XC 6-1stack-specification, not recognized in ESA/XC 6-1stack-type, not recognized in ESA/XC 6-1

extended authorization index (EAX), not provided inESA/XC A-2

extended-authority exception, not recognized in ESA/XC 6-1

EXTRACT PRIMARY ASN (EPAR) instruction, not provided inESA/XC 7-1

EXTRACT SECONDARY ASN (ESAR) instruction, notprovided in ESA/XC 7-1

EXTRACT STACKED REGISTERS (EREG) instruction, notprovided in ESA/XC 7-1

EXTRACT STACKED STATE (ESTA) instruction, not providedin ESA/XC 7-1

extraction-authority control 5-1

Ffacilities of ESA/XC (compared with ESA/390) A-1failing-storage address

in format-0 extended-status word 9-1failing-storage ASIT

assigned storage locations for 3-9validity bit for 8-1

fault-handling option (in host access-list entry) 5-8fetch protection

applicability based on real-address type 3-4override control bit 3-4

floating-point instructions 7-1floating-point registers


Ggeneral instructions 7-1general registers


Hhome address space, not provided in ESA/XC 5-1home segment-table designation (HSTD), not provided in

ESA/XC A-2home-space mode, not provided in ESA/XC 5-1host

use of host page protection 3-5z/VM Control Program (CP) as 2-2

host access listaccess type provide by 5-5allocation and invalidation of entries in 5-4concepts 5-4number of entries in 5-7resetting of, by subsystem reset 4-2revocation of accessing capability 5-5

host access-list entryaccess-type indication in 5-8address space designated by 5-7ASIT contained in 5-7entry state in 5-7page fault handling options for 5-8selection ALET in 5-7valid, revoked and unused states 5-7

host access-list-controlled protection 3-4host access-register translation

as part of TEST ACCESS and TEST PROTECTION 5-8introduction to 5-3structures 5-7

host controls on virtual machinesability to share address spaces 3-2number and size of address spaces 3-2number of entries in host access list 5-7

host page protection 3-5

X-2 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

host servicesfor allocating host access-list entries 5-4for deallocating host access-list entries 5-5for destroying address spaces 3-2for establishing access type in ALE 3-4for granting access to address spaces 5-4for mapping blocks of storage to minidisk blocks 3-5for obtaining additional address spaces 3-2for revoking access to address spaces 5-5for sharing and isolating address spaces 3-2

host-primary address spaceisolation of, by subsystem reset 4-2

host-primary real address 3-3host-primaryabsolute address 3-3

IIAC (INSERT ADDRESS SPACE CONTROL) instruction 7-1IDAW (indirect-data-address word) address (in CCW) 9-1INSERT ADDRESS SPACE CONTROL (IAC) instruction 7-1INSERT STORAGE KEY EXTENDED (ISKE) instruction 7-2INSERT VIRTUAL STORAGE KEY (IVSK) instruction, not

provided in ESA/XC 7-1instruction address 3-3instructions

control 7-1decimal 7-1floating-point 7-1general 7-1

interruptionaction 6-1program 6-1

INVALIDATE PAGE TABLE ENTRY (IPTE) instruction 7-2IPTE (INVALIDATE PAGE TABLE ENTRY) instruction 7-2ISKE (INSERT STORAGE KEY EXTENDED) instruction 7-2IVSK (INSERT VIRTUAL STORAGE KEY) instruction, not

provided in ESA/XC 7-1

Kkey-controlled protection 3-4

LLAE (LOAD ADDRESS EXTENDED) instruction 7-2LASP (LOAD ADDRESS SPACE PARAMETERS) instruction,

not provided in ESA/XC 7-1linkage-stack entry address, not provided in ESA/XC A-2LOAD ADDRESS EXTENDED (LAE) instruction 7-2LOAD ADDRESS SPACE PARAMETERS (LASP) instruction,

not provided in ESA/XC 7-1LOAD PSW (LPSW) instruction 7-2LOAD REAL ADDRESS (LRA) instruction, not provided in

ESA/XC 7-1LOAD USING REAL ADDRESS (LURA) instruction 7-2logical address 3-3low-address protection

applicability based on real-address type 3-5LPSW (LOAD PSW) instruction 7-2LRA (LOAD REAL ADDRESS) instruction, not provided in

ESA/XC 7-1LURA (LOAD USING REAL ADDRESS) instruction 7-2LX-translation exception, not recognized in ESA/XC 6-1

Mmachine check

interruption information 8-1main storage 3-1measurement-block origin 9-1mode

access-register 3-6home-space, not provided in ESA/XC 5-1primary-space 3-6requirements for semiprivileged instructions, not applicable

in ESA/XC 5-1translation 3-6

MODIFY STACKED STATE (MSTA) instruction, not providedin ESA/XC 7-1

MOVE TO PRIMARY (MVCP) instruction, not provided inESA/XC 7-1

MOVE TO SECONDARY (MVCS) instruction, not provided inESA/XC 7-1

MSTA (MODIFY STACKED STATE) instruction, not providedin ESA/XC 7-1

MVCP (MOVE TO PRIMARY) instruction, not provided inESA/XC 7-1

MVCS (MOVE TO SECONDARY) instruction, not provided inESA/XC 7-1

Ppage protection

not provided in ESA/XC 3-4page-translation exception, not recognized in ESA/XC 6-1PALB (PURGE ALB) instruction 7-2PC (PROGRAM CALL) instruction, not provided in

ESA/XC 7-1PC-number translation, not provided in ESA/XC 5-1PC-translation-specification exception, not recognized in

ESA/XC 6-1PER (program-event recording) 4-1PR (PROGRAM RETURN) instruction, not provided in

ESA/XC 7-1prefix register 2-1prefixing

applicability based on real-address type 3-6primary ASN (PASN), not provided in ESA/XC A-2primary ASTE origin (PASTEO), not provided in

ESA/XC A-2primary segment-table designation (PSTD), not provided in

ESA/XC A-2primary-authority exception, not recognized in ESA/XC 6-1primary-space mode 3-6priority of exception conditions 6-3privileged-operation exception 6-2PROGRAM CALL (PC) instruction, not provided in

ESA/XC 7-1program exception 6-1program interruption 6-1PROGRAM RETURN (PR) instruction, not provided in

ESA/XC 7-1PROGRAM TRANSFER (PT) instruction, not provided in

ESA/XC 7-1protection exception

as an access exception 6-4PSW (program-status word)

comparison of ESA/XC with ESA/390 A-2format errors 6-1format of 4-1

PSW-key mask (PKM) 5-1

Index X-3

PT (PROGRAM TRANSFER) instruction, not provided inESA/XC 7-1

PTLB (PURGE TLB) instruction 7-2PURGE ALB (PALB) instruction 7-2PURGE TLB (PTLB) instruction 7-2

Rread-only access, permitted by host access-list entry 5-8read/write access, permitted by host access-list entry 5-8real address

fetch protection for references using 3-3low-address protection for references using 3-3prefixing of 3-3type-A 3-3type-R 3-3

registersaccess 2-1control 2-1floating-point 2-1general 2-1prefix 2-1

resetsubsystem 4-2

RESET REFERENCE BIT EXTENDED (RRBE) instruction 7-3revoked host access-list entry 5-7RRBE (RESET REFERENCE BIT EXTENDED) instruction 7-3

SSAC (SET ADDRESS SPACE CONTROL) instruction 7-3SACF (SET ADDRESS SPACE CONTROL FAST)

instruction 7-3SCK (SET CLOCK) instruction, not provided in ESA/XC 7-1secondary ASN (SASN), not provided in ESA/XC A-2secondary segment-table designation (SSTD), not provided in

ESA/XC A-2secondary-authority exception, not recognized in

ESA/XC 6-1secondary-space control bit, not provided in ESA/XC 5-1secondary-space-control bit, not provided in ESA/XC A-2segment-translation exception, not recognized in ESA/XC 6-1selection ALET (in host access-list entry) 5-7SET ADDRESS SPACE CONTROL (SAC) instruction 7-3SET ADDRESS SPACE CONTROL FAST (SACF)

instruction 7-3SET CLOCK (SCK) instruction, not provided in ESA/XC 7-1SET SECONDARY ASN (SSAR) instruction, not provided in

ESA/XC 7-1SET STORAGE KEY EXTENDED (SSKE) instruction 7-4SET SYSTEM MASK (SSM) instruction 7-4SIE (START INTERPRETIVE EXECUTION) instruction, not

provided in ESA/XC 7-1SIGNAL PROCESSOR (SIGP) instruction 7-4SIGP (SIGNAL PROCESSOR) instruction 7-4space-switch event, not recognized in ESA/XC 6-1special-operation exception 6-3specification exception 6-3SSAR (SET SECONDARY ASN) instruction, not provided in

ESA/XC 7-1SSKE (SET STORAGE KEY EXTENDED) instruction 7-4SSM (SET SYSTEM MASK) instruction 7-4SSM-suppression-control bit, not provided in ESA/XC A-2stack-empty exception, not recognized in ESA/XC 6-1stack-full exception, not recognized in ESA/XC 6-1stack-operation exception, not recognized in ESA/XC 6-1

stack-specification exception, not recognized in ESA/XC 6-1stack-type exception, not recognized in ESA/XC 6-1START INTERPRETIVE EXECUTION (SIE) instruction, not

provided in ESA/XC 7-1state

access-list-entry 5-7storage

main storage 3-1protection facilities 3-3

storage error corrected (machine-check condition) 8-1storage error uncorrected (machine-check condition) 8-1storage-key error uncorrected (machine-check condition) 8-1STORE THEN OR SYSTEM MASK (STOSM) instruction 7-4STORE USING REAL ADDRESS (STURA) instruction 7-4STOSM (STORE THEN OR SYSTEM MASK) instruction 7-4STURA (STORE USING REAL ADDRESS) instruction 7-4subsystem reset 4-2subsystem-linkage control bit, not provided in ESA/XC 5-1suppression on protection 3-5synchronous page-fault handling option (in host access-list

entry) 5-8

TTAR (TEST ACCESS) instruction 7-4TB (TEST BLOCK) instruction 7-5TEST ACCESS (TAR) instruction 7-4TEST BLOCK (TB) instruction 7-5TEST PROTECTION (TPROT) instruction 7-5timing facilities 4-2TOD clock 4-2TOD-clock sync-check subclass mask, not provided in

ESA/XC A-2TOD-clock synchronization facility, not provided in

ESA/XC 4-2TOD-clock-sync-control bit, not provided in ESA/XC A-2TPROT (TEST PROTECTION) instruction 7-5TRACE (TRACE) instruction 7-6tracing facilities

ASN, not provided in ESA/XC 4-1translation modes 3-6translation-exception identification 3-8translation-exception identification, not provided in

ESA/XC A-3TRAP2 instruction, not provided in ESA/XC 7-1TRAP4 instruction, not provided in ESA/XC 7-1type-A real address 3-3type-R real address 3-3

Uunused host access-list entry 5-7

Vvalid host access-list entry 5-7validation of registers, automatic 8-1virtual address 3-3virtual machine supervisor 1-2virtual-storage address space, not provided in ESA/XC 3-6

Zz/VM Control Program (CP) 1-1, 2-2

X-4 z/VM V6.4 Enterprise Systems Architecture/Extended Configuration Principles of Operation

IBM®

Product Number: 5741-A07

Printed in USA

SC24-6192-01