Zigbee

Wireless Data Transmission Using X-Bee

WIRELESS Data Transmission Using X-BeeABSTRACT

In order to establish the wireless data transmission by using Zig Bee we need both transmitter and receiver. We use Zig Bee transceiver with 9600 baud rate. We will interface these transceivers at two different Personal Computers [PCs] by using microcontroller through serial interface. After successful interfacing these Zig Bee transceivers with the computers, enter any data on the serial window of any computer and simultaneously we can observe the same data on the serial window of other system. It will be continued till the data transmission is completed.

This project uses regulated 5V, 500mA power supply. 7805 three terminal voltage regulator is used for voltage regulation. Bridge type full wave rectifier is used to rectify the ac output of secondary of 230/12V step down transformer.

1


Block Diagram:TRANSMITTER:

RECEIVER:

2


Software Used: Keil C Protues Topwin

HardWare used: X-Bee/ Zig-Bee Transceiver Personal computer RS232 cable Power Supply Micro Controller

Schematic diagrams

3


4


5


EMBEDDED SYSTEMSIntroduction An embedded system is a system which is going to do a predefined specified task is the embedded system and is even defined as combination of both software and hardware. A generalpurpose definition of embedded systems is that they are devices used to control, monitor or assist the operation of equipment, machinery or plant. "Embedded" reflects the fact that they are an integral part of the system. At the other extreme a general-purpose computer may be used to control the operation of a large complex processing plant, and its presence will be obvious. All embedded systems are including computers or microprocessors. Some of these computers are however very simple systems as compared with a personal computer. The very simplest embedded systems are capable of performing only a single function or set of functions to meet a single predetermined purpose. In more complex systems an application program that enables the embedded system to be used for a particular purpose in a specific application determines the functioning of the embedded system. The ability to have programs means that the same embedded system can be used for a variety of different purposes. In some cases a microprocessor may be designed in such a way that application software for a particular purpose can be added to the basic software in a second process, after which it is not possible to make further changes. The applications software on such processors is sometimes referred to as firmware. The simplest devices consist of a single microprocessor (often called a "chip), which may itself be packaged with other chips in a hybrid system or Application Specific Integrated Circuit (ASIC). Its input comes from a detector or sensor and its output goes to a switch or activator which (for example) may start or stop the operation of a machine or, by operating a valve, may control the flow of fuel to an engine. As the embedded system is the combination of both software and hardware

6


Embedded System

Software

Hardware

o o o

ALP C VB Etc.,

o o o

Processor Peripherals memory

Figure: Block diagram of Embedded System Software deals with the languages like ALP, C, and VB etc., and Hardware deals with Processors, Peripherals, and Memory. Memory: It is used to store data or address. Peripherals: These are the external devices connected Processor: It is an IC which is used to perform some task Applications of embedded systems Manufacturing and process control Construction industry Transport Buildings and premises Domestic service Communications Office systems and mobile equipment Banking, finance and commercial Medical diagnostics, monitoring and life support Testing, monitoring and diagnostic systems

7


Processors are classified into four types like: Micro Processor (p) Micro controller (c) Digital Signal Processor (DSP) Application Specific Integrated Circuits (ASIC)

Micro Processor (p): A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably. At the heart of all personal computers and most workstations sits a microprocessor. Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for automobiles. Three basic characteristics differentiate microprocessors: Instruction set: The set of instructions that the microprocessor can execute. Bandwidth : The number of bits processed in a single instruction. Clock speed : Given in megahertz (MHz), the clock speed determines how many

instructions per second the processor can execute. In both cases, the higher the value, the more powerful the CPU. For example, a 32-bit microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz. In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer). A microprocessor has three basic elements, as shown above. The ALU performs all arithmetic computations, such as addition, subtraction and logic operations (AND, OR, etc). It is controlled by the Control Unit and receives its data from the Register Array. The Register Array is a set of registers used for storing data. These registers can be accessed by the ALU very quickly. Some registers have specific functions - we will deal with these later. The Control Unit controls the entire process. It provides the timing and a control signal for getting data into and out of the registers and the ALU and it synchronizes the execution of instructions (we will deal with instruction execution at a later date).

8


Three Basic Elements of a Microprocessor Micro Controller (c) A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.

ALU CU Memory

Figure: Block Diagram of Micro Digital Signal Processors (DSPs)

Timer, Counter, serial communication ROM, ADC, DAC, Timers, USART, Oscillators Controller (c)

Etc.,

Digital Signal Processors is one which performs scientific and mathematical operation. Digital Signal Processor chips - specialized microprocessors with architectures designed specifically for 9


the types of operations required in digital signal processing. Like a general-purpose microprocessor, a DSP is a programmable device, with its own native instruction code. DSP chips are capable of carrying out millions of floating point operations per second, and like their better-known general-purpose cousins, faster and more powerful versions are continually being introduced. DSPs can also be embedded within complex "system-on-chip" devices, often containing both analog and digital circuitry. Application Specific Integrated Circuit (ASIC) ASIC is a combination of digital and analog circuits packed into an IC to achieve the desired control/computation function CPU cores for computation and control Peripherals to control timing critical functions Memories to store data and program Analog circuits to provide clocks and interface to the real world which is analog

in nature I/Os to connect to external components like LEDs, memories, monitors etc.

Computer Instruction Set There are two different types of computer instruction set there are: 1. RISC (Reduced Instruction Set Computer) and 2. CISC (Complex Instruction Set computer) Reduced Instruction Set Computer (RISC) A RISC (reduced instruction set computer) is a microprocessor that is designed to perform a smaller number of types of computer instruction so that it can operate at a higher speed (perform more million instructions per second, or millions of instructions per second). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation.Besides performance improvement, some advantages of RISC and related design improvements are:

10


A new microprocessor can be developed and tested more quickly if one of its aims is to

be less complicated. Operating system and application programmers who use the microprocessor's instructions

will find it easier to develop code with a smaller instruction set. The simplicity of RISC allows more freedom to choose how to use the space on a

microprocessor. Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer. RISC characteristics Simple instruction set In a RISC machine, the instruction set contains simple, basic instructions, from which more. complex instructions can be composed. Same length instructions Each instruction is the same length, so that it may be fetched in a single operation. Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines. Complex Instruction Set Computer (CISC) CISC, which stands for Complex Instruction Set Computer, is a philosophy for designing chips that are easy to program and which make efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. This reduces the number of instructions required to implement a given program, and allows the programmer to learn a small but flexible set of instructions. Complex Instruction Set Computer (CISC) CISC, which stands for Complex Instruction Set Computer, is a philosophy for designing chips that are easy to program and which make efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. This reduces the number of instructions required to implement a given program, and allows the programmer to learn a small but flexible set of instructions. 11


The advantages of CISC At the time of their initial development, CISC machines used available technologies to optimize computer performance. Microprogramming is as easy as assembly language to implement, and much less

expensive than hardwiring a control unit. The ease of micro-coding new instructions allowed designers to make CISC machines

upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers. Disadvantages of CISC Still, designers soon realized that the CISC philosophy had its own problems, including: Earlier generations of a processor family generally were contained as a subset in every As each instruction became more capable, fewer instructions could be used to implement

a given task. This made more efficient use of the relatively slow main memory. Because micro program instruction sets can be written to match the constructs of high-

level languages, the compiler does not have to be as complicated.

new version --- so instruction set & chip hardware become more complex with each generation of computers. So that as many instructions as possible could be stored in memory with the least possible

wasted space, individual instructions could be of almost any length---this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine. Many specialized instructions aren't used frequently enough to justify their existence ---

approximately 20% of the available instructions are used in a typical program. CISC instructions typically set the condition codes as a side effect of the instruction. Not

only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them. Memory Architecture There two different types memory architectures there are: 12


Harvard Architecture Von-Neumann Architecture

Harvard Architecture Computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus. The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electromechanical counters. These early machines had limited data storage, entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator, the processor could not boot itself.

Figure: Harvard Architecture Modern uses of the Harvard architecture The principal advantage of the pure Harvard architecture - simultaneous access to more than one memory system - has been reduced by modified Harvard processors using modern CPU cache systems. Relatively pure Harvard architecture machines are used mostly in applications where tradeoffs, such as the cost and power savings from omitting caches, outweigh the programming penalties from having distinct code and data address spaces. Digital signal processors (DSPs) generally execute small, highly-optimized audio or

video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple address spaces are of secondary concern to 13


speed of execution. As a result, some DSPs have multiple data memories in distinct address spaces to facilitate SIMD and VLIW processing. Texas Instruments TMS320 C55x processors, as one example, have multiple parallel data busses (two write, three read) and one instruction bus. Microcontrollers are characterized by having small amounts of program (flash memory)

and data (SRAM) memory, with no cache, and take advantage of the Harvard architecture to speed processing by concurrent instruction and data access. The separate storage means the program and data memories can have different bit depths, for example using 16-bit wide instructions and 8-bit wide data. They also mean that instruction pre-fetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp, the PIC by Microchip Technology, Inc. and the ARM Cortex-M3 processor (not all ARM chips have Harvard architecture). Even in these cases, it is common to have special instructions to access program memory as data for read-only tables, or for reprogramming. Von-Neumann Architecture A computer has a single, common memory space in which both program instructions and data are stored. There is a single internal data bus that fetches both instructions and data. They cannot be performed at the same timeThe von Neumann architecture is a design model for a storedprogram digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data. It is named after the mathematician and early computer scientist John von Neumann. Such computers implement a universal Turing machine and have a sequential architecture. A stored-program digital computer is one that keeps its programmed instructions, as well as its data, in read-write, random-access memory (RAM). Stored-program computers were advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which were programmed by setting switches and inserting patch leads to route data and to control signals between various functional units. In the vast majority of modern computers, the same memory is used for both data and program instructions. The mechanisms for transferring the data and instructions between the CPU and memory are, however, considerably more complex than the original von Neumann architecture.The terms "von Neumann architecture" and 14


"stored-program computer" are generally used interchangeably, and that usage is followed in this article.

Figure: Schematic of the Von-Neumann Architecture. Basic Difference between Harvard and Von-Neumann Architecture The primary difference between Harvard architecture and the Von Neumann architecture

is in the Von Neumann architecture data and programs are stored in the same memory and managed by the same information handling system. Whereas the Harvard architecture stores data and programs in separate memory devices

and they are handled by different subsystems. In a computer using the Von-Neumann architecture without cache; the central processing

unit (CPU) can either be reading and instruction or writing/reading data to/from the memory. Both of these operations cannot occur simultaneously as the data and instructions use the same system bus. In a computer using the Harvard architecture the CPU can both read an instruction and

access data memory at the same time without cache. This means that a computer with Harvard architecture can potentially be faster for a given circuit complexity because data access and instruction fetches do not contend for use of a single memory pathway. Today, the vast majority of computers are designed and built using the Von Neumann

architecture template primarily because of the dynamic capabilities and efficiencies gained in designing, implementing, operating one memory system as opposed to two. Von Neumann architecture may be somewhat slower than the contrasting Harvard Architecture for certain

15


specific tasks, but it is much more flexible and allows for many concepts unavailable to Harvard architecture such as self programming, word processing and so on. Harvard architectures are typically only used in either specialized systems or for very

specific uses. It is used in specialized digital signal processing (DSP), typically for video and audio processing products. It is also used in many small microcontrollers used in electronics applications such as Advanced RISK Machine (ARM) based products for many vendors.

AT89C51 MICROCONTROLLERFEATURES 80C51 based architecture 4-Kbytes of on-chip Reprogrammable Flash Memory 128 x 8 RAM Two 16-bit Timer/Counters Full duplex serial channel Boolean processor Four 8-bit I/O ports, 32 I/O lines Memory addressing capability 64K ROM and 64K RAM

Power save modes: Idle and power-down

Six interrupt sources Most instructions execute in 0.3 us CMOS and TTL compatible Maximum speed: 40 MHz @ Vcc = 5V Industrial temperature available Packages available:

40-pin DIP 44-pin PLCC 44-pin PQFP

16


GENERAL DESCRIPTION THE MICROCONTROLLER A microcontroller is a general purpose device, but that is meant to read data, perform limited calculations on that data and control its environment based on those calculations. The prime use of a microcontroller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the lifetime of the system. The microcontroller design uses a much more limited set of single and double byte instructions that are used to move data and code from internal memory to the ALU. The microcontroller is concerned with getting data from and to its own pins; the architecture and instruction set are optimized to handle data in bit and byte size. The AT89C51 is a low-power, high-performance CMOS 8-bit microcontroller with 4k bytes of Flash Programmable and erasable read only memory (EROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is functionally compatible with the industry-standard 80C51 microcontroller instruction set and pin out. By combining versatile 8-bit CPU with Flash on a monolithic chip, the Atmels AT89c51 is a powerful microcomputer, which provides a high flexible and cost- effective solution to many embedded control applications.

17


Pin configuration of AT89c51 Microcontroller

18


AT89C51 Block Diagram

19


PIN DESCRIPTION: VCC Supply voltage GND Ground Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during access to external program and data memory. In this mode, P 0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The port 1output buffers can sink/source four TTL inputs. When 1s are written to port 1 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (1) because of the internal pull-ups. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The port 2 output buffers can sink/source four TTL inputs. When 1s are written to port 2 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during access to DPTR. In this application Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit data address (MOVX@R1), Port 2

20


emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The port 3 output buffers can sink/source four TTL inputs. When 1s are written to port 3 pins, they are pulled high by the internal pull-ups can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the internal pull-ups. Port 3 also receives some control signals for Flash Programming and verification.

Port pin P3.0 P3.1

Alternate Functions RXD(serial input port) TXD(serial input port)

P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RST

INT0(external interrupt 0) INT1(external interrupt 1) T0(timer 0 external input) T1(timer 1 external input) WR(external data memory write strobe) RD(external data memory read strobe)

Rest input A on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during access to external memory. This pin is also the program pulse input (PROG) during Flash programming. 21


In normal operation ALE is emitted at a constant rate of 1/16 the oscillator frequency and may be used for external timing or clocking purpose. Note,however, that one ALE pulse is skipped during each access to external Data memory. PSEN Program Store Enable is the read strobe to external program memory when the AT89c51 is executing code from external program memory PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA /VPP External Access Enable (EA) must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000h up to FFFFH. Note, however, that if lock bit 1 is programmed EA will be internally latched on reset. EA should be strapped to Vcc for internal program executions. This pin also receives the 12-volt programming enable voltage (Vpp) during Flash programming when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL 2 Output from the inverting oscillator amplifier. OPERATING DESCRIPTION The detail description of the AT89C51 included in this description is: Memory Map and Registers Timer/Counters Interrupt System

22


MEMORY MAP AND REGISTERS Memory The AT89C51 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 4K program memory can reside onchip. The AT89C51 has 128 bytes of on-chip RAM. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. The lower 128 bytes of RAM can be divided into 3 segments as listed below 1. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank. 2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.

23


SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in shows that. Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect. User software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1.The functions of the SFRs are outlined in the following sections. Accumulator (ACC) ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A.

24


B Register (B) The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. Program Status Word (PSW) The PSW register contains program status information. Stack Pointer (SP) The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. Data Pointer (DPTR) The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. Serial Data Buffer (SBUF) The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for Timer/Counters 0 and 1, respectively. Control Registers Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port.

25


TIMER/COUNTERS The IS89C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. All two can be configured to operate either as Timers or event counters. As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 and T1. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating modes: 13-bit timer, 16-bit timer, 8-bit auto-reload, split timer. TIMERS:OSCILLATOR FREQUENCY

12DTLX THX TFX

TR

SFRS USED IN TIMERS The special function registers used in timers are, TMOD Register TCON Register Timer(T0) & timer(T1) Registers 26


(i) TMOD Register TMOD is dedicated solely to the two timers (T0 & T1). The timer mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may configure the timers to only count when an external pin is activated or to count events that are indicated on an external pin. It can consider as two duplicate 4-bit registers, each of which controls the action of one of the timers.

(ii) TCON Register The timer control SFR is used to configure and modify the way in which the

8051s two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in TCON SFR. These bits are used to configure the way in which the external interrupt flags are

activated, which are set when an external interrupt occurs.

(iii) TIMER 0 (T0) TO (Timer 0 low/high, address 8A/8C h)

These two SFRs taken together represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value.

TH0

TL0

27


(iv) TIMER 1 (T1) T1 (Timer 1 Low/High, address 8B/ 8D h)

These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is Configurable is how and when they increment in value.TH1 TL1

The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters, but Mode 3 is different. The four modes are described in the following sections.

Mode 0 Both Timers in Mode 0 are 8-bit Counters with a divide-by-32 pre scalar. Figure 8 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. Gate is in TMOD.The 13-bit register consists of all eight bits of TH1 and the lower five bits of TL1. The upper three bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace the corresponding Timer 1 signals. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Mode 1 Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (TL1/TH1). As clock pulses are 28


received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H overflow flag. The timer continues to count. The overflow flag is the TF1 bit in TCON that is read or written by software Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 10. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves the TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 11. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89C51 can appear to have three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. INTERRUPT SYSTEM An interrupt is an external or internal event that suspends the operation of micro controller to inform it that a device needs its service. In interrupt method, whenever any device needs its service, the device notifies the micro controller by sending it an interrupt signal. Upon receiving an interrupt signal, the micro controller interrupts whatever it is doing and serves the device. The program associated with interrupt is called as interrupt service subroutine (ISR).Main advantage with interrupts is that the micro controller can serve many devices.

29


Baud Rate The baud rate in Mode 0 is fixed as shown in the following equation. Mode 0 Baud Rate = Oscillator Frequency /12 the baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON. If SMOD = 0 the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency. Mode 2 Baud Rate = 2SMODx (Oscillator Frequency)/64.In the IS89C51, the Timer 1 overflow rate determines the baud rates in Modes 1 and 3. NUMBER OF INTERRUPTS IN 89C51 There are basically five interrupts available to the user. Reset is also considered as an interrupt. There are two interrupts for timer, two interrupts for external hardware interrupt and one interrupt for serial communication. Memory location 0000H 0003H 000BH 0013H 001BH 0023H Interrupt name Reset External interrupt 0 Timer interrupt 0 External interrupt 1 Timer interrupt 1 Serial COM interrupt

Lower the vector, higher the priority. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source (rather than the on-chip hardware) controls the request flag. 30


The Timer 0 and Timer 1 Interrupts are generated by TF0and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3).When a timer interrupt is generated, the on-chip hardware clears the flag that is generated. The Serial Port Interrupt is generated by the logical OR of RI and TI. The servicer outine normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (interrupt enable) at address 0A8H. There is a global enable/disable bit that is cleared to disable all interrupts or to set the interrupts. IE (Interrupt enable register) Steps in enabling an interrupt Bit D7 of the IE register must be set to high to allow the rest of register to take effect. If EA=1, interrupts are enabled and will be responded to if their corresponding bits in IE are high. If EA=0, no interrupt will be responded to even if the associated bit in the IE register is high. Description of each bit in IE register D7 bit: Disables all interrupts. If EA =0, no interrupt is acknowledged, if EA=1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit. D6 bit: Reserved. D5 bit: Enables or disables timer 2 over flow interrupt (in 8052). D4 bit: Enables or disables serial port interrupt. D3 bit: Enables or disables timer 1 over flow interrupt. 31


D2 bit: Enables or disables external interrupt 1. D1 bit: Enables or disables timer 0 over flow interrupt. D0 bit: Enables or disables external interrupt 0. Interrupt priority in 89C51 There is one more SRF to assign priority to the interrupts which is named as interrupt priority (IP). User has given the provision to assign priority to one interrupt. Writing one to that particular bit in the IP register fulfils the task of assigning the priority. Description of each bit in IP register D7 bit: Reserved. D6 bit: Reserved. D5 bit: Timer 2 interrupt priority bit (in 8052). D4 bit: Serial port interrupt priority bit. D3 bit: Timer 1 interrupt priority bit. D2 bit: External interrupt 1 priority bit. D1 bit: Timer 0 interrupt priority bit. D0 bit: External interrupt 0 priority bit.

POWER SUPPLYIn this project we have power supplies with +5V & -5V option normally +5V is enough for total circuit. Another (-5V) supply is used in case of OP amp circuit .Transformer primary side has 230/50HZ AC voltage whereas at the secondary winding the voltage is step downed to 12/50hz and this voltage is rectified using two full wave rectifiers .the rectified output is given to a filter circuit to fiter the unwanted ac in the signal After that the output is again applied to a regulator LM7805(to provide +5v) regulator. Whereas LM7905 is for providing 5V regulation. 32


(+12V circuit is used for stepper motors, Fan and Relay by using LM7812 regulator same process like above supplies.) HEAT SINK More often transistors gets heated when the circuit is ON for long time. In order to avoid heating up of transistors we use heat sinks. BLOCK DIAGRAM OF POWER SUPPLY

DFD is the power supply pin for the circuit. A step down transformer is used to convert 230V 50HZ line voltage 12-0-12V ac input to the supply pin of the circuit. The ac voltage is converted to pulsated dc using a center tapped full wave rectifier. Any ripples if present are eliminated using a capacitive filter at the output of the full wave rectifier. The capacitive filter output is input to 7805-voltage regulator, which produces a dc equivalent of ac 5V. This 5V dc acts as VCC to the micro controller. The excess voltage is dissipated as heat via an Aluminum heat sink attached to the voltage regulator. TAPPED FULL WAVE RECTIFIER The circuit employs two diodes D1 and D2 as shown in the figure below. A center tapped secondary winding AB is used with two diodes connected so that each uses one- half cycle of the input ac voltage. In other words, D1 utilizes the ac voltage appearing across the upper half (OA) of secondary winding for rectification while D2 uses the lower half winding OB.

33


D11 5 6 4 8

AC Supply

RL

D2

Centertap full wave rectifierOPERATION During the positive half cycle of secondary voltage, the end A of the secondary winding becomes positive and end B negative. This makes the diode D1 forward biased and D2 reverse biased. Therefore D1 conducts while D2 does not. The conventional current flow is through diode D1, load resistor RL and upper half of secondary winding as shown by the dotted arrows. During the negative half cycle, end A of the secondary winding becomes negative and end B positive. Therefore D2 conducts while D1 does not. The conventional current flow is through D2, load RL and lower half winding as shown by solid arrows in the figure above .It is seen that current in the load RL is in the same direction for both half cycles of input ac voltage. Therefore dc is obtained across the load RL. Also the polarities of the output across the load should be noted PEAK INVERSE VOLTAGE Suppose Vm is the maximum voltage across the half secondary winding at the instant secondary voltage reaches its maximum value in the positive direction. At this instant D1 is conducting while D2 is not conducting. Therefore whole of the secondary voltage appears across the non-conducting diode. Consequently the peak inverse voltage is twice the maximum voltage across the half secondary winding.

34


FILTER CIRCUIT A filter circuit is a device which removes the ac component of rectifier output but allows the dc component to the load. The most commonly used filter circuits are capacitor filter, choke input filter and capacitor input filter or pi-filter. We used capacitor filter here. CAPACITOR FILTER This consists of a capacitor C placed across the rectifier output in parallel with the load RL. The pulsating direct voltage of the rectifier is applied across the capacitor. As the rectifier voltage increases, it charges the capacitor and also supplies current to the load. At the end of quarter cycle the capacitor is charged to the peak value Vm of the rectifier voltage. Now the rectifier voltage starts to decrease. As this occurs the capacitor discharges through the load and the voltage across it decrease. The voltage across load will decrease only slightly because immediately the next voltage peak comes and recharges the capacitor. This process is repeated again and again. At the output very little ripple is left. moreover output voltage is higher as it remains substantially near the peak value of rectifier output voltage. The capacitor filter circuit is extremely popular because of its low cost, small size,little weight and good characteristics. For small load currents this type of filter is preferred. it is commonly used in transistor radio battery eliminators.

35


Rectifier O/P

C

RL

Capacitor Filter

Description: A variable regulated power supply, also called a variable bench power supply, is one where you can continuously adjust the output voltage to your requirements. Varying the output of the power supply is the recommended way to test a project after having double checked parts placement against circuit drawings and the parts placement guide. This type of regulation is ideal for having a simple variable bench power supply. Actually this is quite important because one of the first projects a hobbyist should undertake is the construction of a variable regulated power supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially for testing. Most digital logic circuits and processors need a 5 volt power supply. To use these parts we need to build a regulated 5 volt source. Usually you start with anunregulated power supply ranging from 9 volts to 24 volts DC To make a 5 volt power supply, we use a LM7805 voltage regulator IC (Integrated Circuit). The IC is shown below.

Fig: 5.2.1

36


Fig: 5.2.1

The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the common pin and then when you turn on the power, you get a 5 volt supply from the Output pin. Block Diagram:

Fig 5.2.2: - Block Diagram of Power supply

Circuit Features: Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA 37


Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot Circuit complexity: Very simple and easy to build Circuit performance: Very stable +5V output voltage, reliable operation Availability of components: Easy to get, uses only very common basic components Design testing: Based on datasheet example circuit, I have used this circuit successfully as part of many electronics projects Applications: Part of electronics devices, small laboratory power supply Power supply voltage: Unregulated DC 8-18V power supply Power supply current: Needed output current + 5 mA Component costs: Few dollars for the electronics components + the input transformer cost.

38


Pull-up & Pull-down Resistors Often we want to connect a digital input line to our microcontroller. Typically this might be to allow us to monitor the on-off state of a switch

5V

switch 0V (gnd or )

Microcontroller

At first glance this seems fine. When the switch is closed, the pin on our microcontroller is tied to 0 volt, ie. low. In contrast when the switch is open we would want the pin to be 5 volts, or high. The input pin would tend to float high. This however isnt a true input signal, it is a very weak input and can readily switch from high to low through the slightest of electrical interference in any of the wiring. A simple solution might appear to involve simply connecting the other end of the switch to our 5 volt supply

5V

switch 0V (gnd or )

Microcontrolle r

39


This will give us a 5 volt (high) signal on the input pin when the switch is open. When the switch is closed however we will get a short between supply and ground => zero resistance => infinite current - this is not good news.The problem can be remedied by simply putting a resistor into the circuit. This is the pull-up resistor.

5V 10 k switch 0V (gnd or )When the switch is open, the input to the microcontroller is high. There is no direct connection to the 5v rail, however because the input impedance to the microcontroller is high, very little of the 5v is dropped over the pull up resistor. When the switch is closed current flows down through the resistor and through the closed switch to ground. The input pin is tied to ground and so will read low. This gives us what we want. A variation on this is the pull-down resistor. This ties the input pin to ground rather than the supply voltage.

Microcontroller

5V switch 10 k 0V (gnd or )40

Microcontroller


LEDIntroduction A light-emitting diode (LED) is a semiconductor light source. LEDs are used as indicator lamps in many devices, and are increasingly used for lighting. Introduced as a practical electronic component in 1962, early LEDs emitted low-intensity red light, but modern versions are available across the visible, ultraviolet and infrared wavelengths, with very high brightness. The LED is based on the semiconductor diode. When a diode is forward biased, electrons are able to recombine with holes within the device, releasing energy in the form of photons. This effect is called electroluminescence and the color of the light (corresponding to the energy of the photon) is determined by the energy gap of the semiconductor. An LED is usually small in area (less than 1 mm2), and integrated optical components are used to shape its radiation pattern and assist in reflection. LEDs present many advantages over incandescent light sources including lower energy consumption, longer lifetime, improved robustness, smaller size, faster switching, and greater durability and reliability. However, they are relatively expensive and require more precise current and heat management than traditional light sources. Current LED products for general lighting are more expensive to buy than fluorescent lamp sources of comparable output.

41


Working:

Charge-carriers

electrons and holesflow into the junction from electrodes with different voltages.

When an electron meets a hole, it falls into a lower energy level, and releases energy in the form of a photon. The wavelength of the light emitted, and therefore its color, depends on the band gap energy of the materials forming the p-n junction. In silicon or germanium diodes, the electrons and holes recombine by produces a non-radiative no optical

transition which

emission, because these are indirect band gap materials. The materials used for the LED have a direct band gap with energies corresponding to near-infrared, visible or near-ultraviolet light.

42


Colors and materials : Color Wavelength (nm) Voltage (V) Semiconductor Material

Infrared

> 760

V < 1.9

Gallium

arsenide (GaAs)

Aluminum gallium arsenide (AlGaAs)

Aluminum Red 610 < < 760 1.63 < V < Gallium 2.03

gallium arsenide

arsenide (AlGaAs) phosphide (GaAsP)

Aluminium gallium indium phosphide (AlGaInP) Gallium(III) phosphide (GaP)

Orange

590 < < 610

2.03 < V < 2.10

Gallium

arsenide

phosphide (GaAsP)

Aluminum gallium indium phosphide (AlGaInP) Gallium(III) phosphide (GaP)

Yellow

570 < < 590

2.10 < V < 2.18

Gallium

arsenide

phosphide (GaAsP)

Aluminium gallium indium phosphide (AlGaInP) Gallium(III) phosphide (GaP)

Indium gallium nitride (InGaN) / Gallium(III) 500 < < 570 1.9[42] < V < 4.0 nitride (GaN) Gallium(III) phosphide (GaP)

Green

Aluminium gallium indium phosphide (AlGaInP) Aluminium gallium phosphide (AlGaP)

43


Zinc Blue 450 < < 500 2.48 < V < Indium 3.7 Silicon gallium carbide (SiC)

selenide (ZnSe) nitride (InGaN) as substrate

Silicon (Si) as substrate (under development)

Violet

400 < < 450

2.76 < V < 4.0

Indium gallium nitride (InGaN)

Purple

multiple types

2.48 < V < 3.7

Dual blue with

blue/red red

LEDs, phosphor,

or white with purple plastic

Diamond (235 nm) Boron Ultraviolet < 400 3.1 < V < Aluminium 4.4 Aluminium nitride (AlN) gallium nitride (215 nm) (210 nm) nitride (AlGaN)

Aluminium gallium indium nitride (AlGaInN) (down to 210 nm)

White

Broad spectrum

V = 3.5

Blue/UV diode with yellow phosphor

RS232: RS232 is a asynchronous serial communication protocol widely used in computers and digital systems. It is called asynchronous because there is no separate synchronizing clock signal as there are in other serial protocols like SPI and I2C. The protocol is such that it automatically synchronize itself. We can use RS232 to easily create a data link between our MCU based projects and standard PC. Excellent example is a commercial Serial PC mouse (not popular these days, I had got one with my old PC which I bought in year 2000 in those days these were 44


famous). You can make a data loggers that reads analog value(such as temperatures or light using proper sensors) using the ADC and send them to PC where a special program written by you shows the data using nice graphs and charts etc.. actually your imagination is the limit! Basics of Serial Communication In serial communication the whole data unit, say a byte is transmitted one bit at a time. While in parallel transmission the whole data unit, say a byte (8bits) are transmitted at once. Obviously serial transmission requires a single wire while parallel transfer requires as many wires as there are in our data unit. So parallel transfer is used to transfer data within short range (e.g. inside the computer between graphic card and CPU) while serial transfer is preferable in long range. As in serial transmission only one wire is used for data transfer. Its logic level changes according to bit being transmitted (0 or 1). But a serial communication need some way of synchronization. If you don't understand what I mean by "synchronization" then don't worry just read on it will become clear. The animation below shows you how a serial transmission would look like (if you can see electricity).

Fig- A Serial Line.(HIGH=RED & LOW=WHITE)

Can you make out what data is coming? No because you are not synchronized. You need a way to know when a new byte start and when a bit ends and new bit start. Suppose the line is low for some time that means a '0' but how many zeros? If we send data like 00001111 then line is first low for some time and high after that. Then how we know it is four '0's and four '1's? Now if we add another line called the clock line to synchronize you then it will become very easy. You need to note down the value of data line only when you see the "clock line" high. Lets understand this with help of an animation. 45


Fig- A Serial Line.(HIGH=RED & LOW=WHITE)

Now you can see how the "clock" line helps you in "synchronizing" the incoming data. In this way many serial busses like SPI and I2C works. But USART is different in USART there is no clock line. So it is called UART - Universal Asynchronous Receiver Transmitter. In USART a start bit and stop bits are used to synchronize the incoming data the. RS232 In RS232 there are two data lines RX and TX. TX is the wire in which data is sent out to other device. RX is the line in which other device put the data it need to sent to the device.

Fig- RS232 transmission. The arrows indicates the direction of data transfer. In addition to RX/TX lines there is a third line i.e. Ground (GND) or Common.

46


One more thing about RS232. We know that a HIGH =+5v and LOW=0v in TTL / MCU circuits but in RS232 a HIGH=-12V and LOW=+12V. Ya this is bit weird but it increases the range and reliability of data transfer. Now you must be wondering how to interface this to MCUs who understand only 0 and 5v? But you will be very happy to know that there is a very popular IC which can do this for you! It is MAX232 from Maxim Semiconductors. I will show you how to make a level converter using MAX232 in next tutorial. As there is no "clock" line so for synchronization accurate timing is required so transmissions are carried out with certain standard speeds. The speeds are measured in bits per second. Number of bits transmitted is also known as baud rate. Some standard baud rates are

1200 2400 4800 9600 19200 38400 57600 115200 ... etc For our example for discussion of protocol we chose the speed as 9600bps(bits per second). As we are sending 9600 bits per second one bits takes 1/9600 seconds or 0.000104 sec or 104 uS (microsecond= 10^-6 sec). To transmit a single byte we need to extra bits they are START BIT AND STOP BIT(more about them latter). Thus to send a byte a total of ten bits are required so we are sending 960 bytes per second. Note: The number of stop bits can be one or two (for simplicity we will be using single stop bit) There is one more bit the parity bit but again for simplicity we would not be using it)

47


RS232 Data Transmission. The data transfer is done in following ways Transmission 1. When there is no transmission the TX line sits HIGH (-12V See above para) ( STOP CONDITION ) 2. high=-12v and low=+12v 3. When the device needs to send data it pulls the TX line low for 104uS (This is the start bit which is always 0) 4. then it send each bits with duration = 104uS 5. Finally it sets TX lines to HIGH for at least 104uS (This is stop bits and is always 1). I said "at least" because after you send the stop bit you can either start new transmission by sending a start bit or you let the TX line remain HIGH till next transmission begin in this case the last bit is more than 104uS.

Fig- Data Transmission on RS232 line.

48


Reception 1. The receiving device is waiting for the start bit i.e. the RX line to go LOW (+12V see above para). 2. When it gets start bit it waits for half bit time i.e. 104/2 = 51uS now it is in middle of start bit it reads it again to make sure it is a valid start bit not a spike. 3. Then it waits for 104uS and now it is in middle of first bit it now reads the value of RX line. 4. In same way it reads all 8 bits. 5. Now the receiver has the data.

Fig- How the Receiver receives the data on RS232 RX l

49


ZigBeeZigBee is a specification for a suite of high level communication protocols using small, low-power digital radios based on the IEEE 802.15.4-2003 standard for wireless personal area networks (WPANs), such as wireless headphones connecting with cell phones via short-range radio. The technology defined by the ZigBee specification is intended to be simpler and less expensive than other WPANs, such as Bluetooth. ZigBee is targeted at radio-frequency (RF) applications that require a low data rate, long battery life, and secure networking. Overview ZigBee is a low-cost, low-power, wireless mesh networking proprietary standard. The low cost allows the technology to be widely deployed in wireless control and monitoring applications, the low power-usage allows longer life with smaller batteries, and the mesh networking provides high reliability and larger range. The ZigBee Alliance, the standards body that defines ZigBee, also publishes application profiles that allow multiple OEM vendors to create interoperable products. The current list of application profiles either published or in the works are:

Home Automation ZigBee Smart Energy Commercial Building Automation Telecommunication Applications Personal, Home, and Hospital Care Toys The relationship between IEEE 802.15.4 and ZigBee is similar to that between IEEE

802.11 and the Wi-Fi Alliance. The ZigBee 1.0 specification was ratified on 14 December 2004 and is available to members of the ZigBee Alliance. Most recently, the ZigBee 2007 specification was posted on 30 October 2007. The first ZigBee Application Profile, Home Automation, was announced 2 November 2007.

50


ZigBee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in Europe, 915 MHz in the USA and Australia, and 2.4 GHz in most jurisdictions worldwide. The technology is intended to be simpler and less expensive than other WPANs such as Bluetooth. ZigBee chip vendors typically sell integrated radios and microcontrollers with between 60K and 128K flash memory, such as the Jennic JN5148, the Freescale MC13213, the Ember EM250, the Texas Instruments CC2430 and the Atmel ATmega128RFA1. Radios are also available standalone to be used with any processor or microcontroller. Generally, the chip vendors also offer the ZigBee software stack, although independent ones are also available. Because ZigBee can activate (go from sleep to active mode) in 15 msec or less, the latency can be very low and devices can be very responsive particularly compared to Bluetooth wakeup delays, which are typically around three seconds. Because ZigBees can sleep most of the time, average power consumption can be very low, resulting in long battery life. The first stack release is now called ZigBee 2004. The second stack release is called ZigBee 2006, and mainly replaces the MSG/KVP structure used in 2004 with a "cluster library". The 2004 stack is now more or less obsolete.[citation needed] ZigBee 2007, now the current stack release, contains two stack profiles, stack profile 1 (simply called ZigBee), for home and light commercial use, and stack profile 2 (called ZigBee Pro). ZigBee Pro offers more features, such as multi-casting, many-to-one routing and high security with Symmetric-Key Key Exchange (SKKE), while ZigBee (stack profile 1) offers a smaller footprint in RAM and flash. Both offer full mesh networking and work with all ZigBee application profiles. ZigBee 2007 is fully backward compatible with ZigBee 2006 devices: A ZigBee 2007 device may join and operate on a ZigBee 2006 network and vice versa. Due to differences in routing options, ZigBee Pro devices must become non-routing ZigBee End-Devices (ZEDs) on a ZigBee 2006 or ZigBee 2007 network, the same as ZigBee 2006 or ZigBee 2007 devices must become ZEDs on a ZigBee Pro network. The applications running on those devices work the same, regardless of the stack profile beneath them.

51


Uses ZigBee protocols are intended for use in embedded applications requiring low data rates and low power consumption. ZigBee's current focus is to define a general-purpose, inexpensive, self-organizing mesh network that can be used for industrial control, embedded sensing, medical data collection, smoke and intruder warning, building automation, home automation, etc. The resulting network will use very small amounts of power individual devices must have a battery life of at least two years to pass ZigBee certification Typical application areas include

Home Entertainment and Control Smart lighting, advanced temperature control, safety and security, movies and music

Home Awareness Water sensors, power sensors, energy monitoring, smoke and fire detectors, smart appliances and access sensors

Mobile Services m-payment, m-monitoring and control, m-security and access control, m-healthcare and tele-assist

Commercial Building Energy monitoring, HVAC, lighting, access control Industrial Plant Process control, asset management, environmental management, energy management, industrial device control

Device types There are three different types of ZigBee devices:

ZigBee coordinator (ZC): The most capable device, the coordinator forms the root of the network tree and might bridge to other networks. There is exactly one ZigBee coordinator in each network since it is the device that started the network originally. It is able to store information about the network, including acting as the Trust Centre & repository for security keys. 52


ZigBee Router (ZR): As well as running an application function, a router can act as an intermediate router, passing on data from other devices.

ZigBee End Device (ZED): Contains just enough functionality to talk to the parent node (either the coordinator or a router); it cannot relay data from other devices. This relationship allows the node to be asleep a significant amount of the time thereby giving long battery life. A ZED requires the least amount of memory, and therefore can be less expensive to manufacture than a ZR or ZC.

Protocols The protocols build on recent algorithmic research (Ad-hoc On-demand Distance Vector, neuRFon) to automatically construct a low-speed ad-hoc network of nodes. In most large network instances, the network will be a cluster of clusters. It can also form a mesh or a single cluster. The current profiles derived from the ZigBee protocols support beacon and non-beacon enabled networks. In non-beacon-enabled networks (those whose beacon order is 15), an unslotted CSMA/CA channel access mechanism is used. In this type of network, ZigBee Routers typically have their receivers continuously active, requiring a more robust power supply. However, this allows for heterogeneous networks in which some devices receive continuously, while others only transmit when an external stimulus is detected. The typical example of a heterogeneous network is a wireless light switch: The ZigBee node at the lamp may receive constantly, since it is connected to the mains supply, while a battery-powered light switch would remain asleep until the switch is thrown. The switch then wakes up, sends a command to the lamp, receives an acknowledgment, and returns to sleep. In such a network the lamp node will be at least a ZigBee Router, if not the ZigBee Coordinator; the switch node is typically a ZigBee End Device. In beacon-enabled networks, the special network nodes called ZigBee Routers transmit periodic beacons to confirm their presence to other network nodes. Nodes may sleep between beacons, thus lowering their duty cycle and extending their battery life. Beacon intervals may range from 15.36 milliseconds to 15.36 ms * 214 = 251.65824 seconds at 250 kbit/s, from 24 milliseconds to 24 ms * 214 = 393.216 seconds at 40 kbit/s and from 48 milliseconds to 48 ms *

53


214 = 786.432 seconds at 20 kbit/s. However, low duty cycle operation with long beacon intervals requires precise timing, which can conflict with the need for low product cost. In general, the ZigBee protocols minimize the time the radio is on so as to reduce power use. In beaconing networks, nodes only need to be active while a beacon is being transmitted. In non-beacon-enabled networks, power consumption is decidedly asymmetrical: some devices are always active, while others spend most of their time sleeping. ZigBee devices are required to conform to the IEEE 802.15.4-2003 Low-Rate Wireless Personal Area Network (WPAN) standard. The standard specifies the lower protocol layersthe physical layer (PHY), and the media access control (MAC) portion of the data link layer (DLL). This standard specifies operation in the unlicensed 2.4 GHz (worldwide), 915 MHz (Americas) and 868 MHz (Europe) ISM bands. In the 2.4 GHz band there are 16 ZigBee channels, with each channel requiring 5 MHz of bandwidth. The center frequency for each channel can be calculated as, FC = (2405 + 5 * (ch - 11)) MHz, where ch = 11, 12... 26. The radios use direct-sequence spread spectrum coding, which is managed by the digital stream into the modulator. BPSK is used in the 868 and 915 MHz bands, and orthogonal QPSK that transmits two bits per symbol is used in the 2.4 GHz band. The raw, over-the-air data rate is 250 kbit/s per channel in the 2.4 GHz band, 40 kbit/s per channel in the 915 MHz band, and 20 kbit/s in the 868 MHz band. Transmission range is between 10 and 75 meters (33 and 246 feet) and up to 1500 meters for zigbee pro, although it is heavily dependent on the particular environment. The maximum output power of the radios is generally 0 dBm (1 mW). The basic channel access mode is "carrier sense, multiple access/collision avoidance" (CSMA/CA). That is, the nodes talk in the same way that people converse; they briefly check to see that no one is talking before they start. There are three notable exceptions to the use of CSMA. Beacons are sent on a fixed timing schedule, and do not use CSMA. Message acknowledgments also do not use CSMA. Finally, devices in Beacon Oriented networks that have low latency real-time requirements may also use Guaranteed Time Slots (GTS), which by definition do not use CSMA.

54


ZigBee RF4CE On March 3, 2009 the RF4CE (Radio Frequency for Consumer Electronics) Consortium agreed to work with the ZigBee Alliance to jointly deliver a standardized specification for radio frequency-based remote controls. ZigBee RF4CE is designed to be deployed in a wide range of remotely-controlled audio/visual consumer electronics products, such as TVs and set-top boxes. It promises many advantages over existing remote control solutions, including richer communication and increased reliability, enhanced features and flexibility, interoperability, and no line-of-sight barrier. Software and hardware The software is designed to be easy to develop on small, inexpensive microprocessors. The radio design used by ZigBee has been carefully optimized for low cost in large scale production. It has few analog stages and uses digital circuits wherever possible. Even though the radios themselves are inexpensive, the ZigBee Qualification Process involves a full validation of the requirements of the physical layer. This amount of concern about the Physical Layer has multiple benefits, since all radios derived from that semiconductor mask set would enjoy the same RF characteristics. On the other hand, an uncertified physical layer that malfunctions could cripple the battery lifespan of other devices on a ZigBee network. Where other protocols can mask poor sensitivity or other esoteric problems in a fade compensation response, ZigBee radios have very tight engineering constraints: they are both power and bandwidth constrained. Thus, radios are tested to the ISO 17025 standard with guidance given by Clause 6 of the 802.15.4-2006 Standard. Most vendors plan to integrate the radio and microcontroller onto a single chip. History

ZigBee-style networks began to be conceived about 1998, when many installers realized that both WiFi and Bluetooth were going to be unsuitable for many applications. In particular, many engineers saw a need for self-organizing ad-hoc digital radio networks.

The IEEE 802.15.4 standard was completed in May 2003. 55


In the summer of 2003, Philips Semiconductors, a major mesh network supporter, ceased the investment. Philips Lighting has, however, continued Philips' participation, and Philips remains a promoter member on the ZigBee Alliance Board of Directors.

The ZigBee Alliance announced in October 2004 that the membership had more than doubled in the preceding year and had grown to more than 100 member companies, in 22 countries. By April 2005 membership had grown to more than 150 companies, and by December 2005 membership had passed 200 companies.

The ZigBee specifications were ratified on 14 December 2004. The ZigBee Alliance announces public availability of Specification 1.0 on 13 June 2005, known as ZigBee 2004 Specification.

The ZigBee Alliance announces the completion and immediate member availability of the enhanced version of the ZigBee Standard in September 2006, known as ZigBee 2006 Specification.

During the last quarter of 2007, ZigBee PRO, the enhanced ZigBee specification was finalized.

Origins of ZigBee name Articles published by technology news organizations such as EDN and

Telecommunications Online claim that the term "ZigBee" originates from the zig-zag waggle dance honeybees use to share critical information, such as the location, distance, and direction of a newly discovered food source, with fellow hive members. ZigBee device manufacturer Meshnetics refers to this communication system as the "ZigBee Principle". However, no such term exists in apiology, the scientific study of honeybees. Robert Metcalfe, inventor of Ethernet and a contributor on the initial development of ZigBee, confirmed to a journalist in 2004 that the name was initially meaningless and had been chosen from a long list on the basis that it had no trademark liabilities.

56


ZigBee module. The 1 coin, shown for size reference, is about 23 mm in diameter (1-inch is 25.4mm). ZigBee specification ZigBee is the specification of a low-cost, low-power wireless communications solution, meant to be integrated as the main building block of ubiquitous networks. It is maintained by the ZigBee Alliance, which develops the specification and certifies its proper implementation. As of 2007, the latest publicly available revision is the 2006 version. Overview

ZigBee protocol stack ZigBee builds upon the physical layer and medium access control defined in IEEE standard 802.15.4 (2003 version) for low-rate WPAN's. The specification goes on to complete the standard by adding four main components: network layer, application layer, ZigBee device objects (ZDO's) and manufacturer-defined application objects which allow for customization and favor total integration.

57


Besides adding two high-level network layers to the underlying structure, the most significant improvement is the introduction of ZDO's. These are responsible for a number of tasks, which include keeping of device roles, management of requests to join a network, device discovery and security. At its core, ZigBee is a mesh network architecture. Its network layer natively supports three types of topologies: both star and tree typical networks and generic mesh networks. Every network must have one coordinator device, tasked with its creation, the control of its parameters and basic maintenance. Within star networks, the coordinator must be the central node. Both trees and meshes allow the use of ZigBee routers to extend communication at the network level (they are not ZigBee coordinators, but may act as 802.15.4 coordinators within their personal operating space), but they differ in a few important details: communication within trees is hierarchical and optionally utilizes frame beacons, whereas meshes allow generic communication structures but no router beaconing. Network layer The main functions of the network layer are to enable the correct use of the MAC sublayer and provide a suitable interface for use by the next upper layer, namely the application layer. Its capabilities and structure are those typically associated to such network layers, including routing. On the one hand, the data entity creates and manages network layer data units from the payload of the application layer and performs routing according to the current topology. On the other hand, there is the layer control, which is used to handle configuration of new devices and establish new networks: it can determine whether a neighboring device belongs to the network and discovers new neighbors and routers. The control can also detect the presence of a receiver, which allows direct communication and MAC synchronization. The routing protocol used by the Network layer is AODV. In order to find the destination device, it broadcasts out a route request to all of its neighbors. The neighbors then broadcast the request to their neighbors, etc until the destination is reached. Once the destination is reached, it sends its route reply via unicast transmission following the lowest cost path back to the source. Once the

58


source receives the reply, it will update its routing table for the destination address with the next hop in the path and the path cost. Application layer The application layer is the highest-level layer defined by the specification, and is the effective interface of the ZigBee system to its end users. It comprises the majority of components added by the ZigBee specification: both ZDO and its management procedures, together with application objects defined by the manufacturer, are considered part of this layer. Main components The ZDO is responsible for defining the role of a device as either coordinator or end device, as mentioned above, but also for the discovery of new (one-hop) devices on the network and the identification of their offered services. It may then go on to establish secure links with external devices and reply to binding requests accordingly. The application support sublayer (APS) is the other main standard component of the layer, and as such it offers a well-defined interface and control services. It works as a bridge between the network layer and the other components of the application layer: it keeps up-to-date binding tables in the form of a database, which can be used to find appropriate devices depending on the services that are needed and those the different devices offer. As the union between both specified layers, it also routes messages across the layers of the protocol stack.

59


Communication models

ZigBee high-level communication model An application may consist of communicating objects which cooperate to carry out the desired tasks. The focus of ZigBee is to distribute work among many different devices which reside within individual ZigBee nodes which in turn form a network (said work will typically be largely local to each device, for instance the control of each individual household appliance). The collection of objects that form the network communicate using the facilities provided by APS, supervised by ZDO interfaces. The application layer data service follows a typical requestconfirm/indication-response structure. Within a single device, up to 240 application objects can exist, numbered in the range 1-240. 0 is reserved for the ZDO data interface and 255 for broadcast; the 241-254 range is not currently in use but may be in the future. There are two services available for application objects to use (in ZigBee 1.0):

The key-value pair service (KPV) is meant for configuration purposes. It enables description, request and modification of object attributes through a simple interface based on get/set and event primitives, some allowing a request for response. Configuration uses compressed XML (full XML can be used) to provide an adaptable and elegant solution. 60


The message service is designed to offer a general approach to information treatment, avoiding the necessity to adapt application protocols and potential overhead incurred on by KPV. It allows arbitrary payloads to be transmitted over APS frames.

Addressing is also part of the application layer. A network node consists of an 802.15.4conformant radio transceiver and one or more device descriptions (basically collections of attributes which can be polled or set, or which can be monitored through events). The transceiver is the base for addressing, and devices within a node are specified by an endpoint identifier in the range 1-240. Communication and device discovery In order for applications to communicate, their comprising devices must use a common application protocol (types of messages, formats and so on); these sets of conventions are grouped in profiles. Furthermore, binding is decided upon by matching input and output cluster identifiers, unique within the context of a given profile and associated to an incoming or outgoing data flow in a device. Binding tables contain source and destination pairs. Depending on the available information, device discovery may follow different methods. When the network address is known, the IEEE address can be requested using unicast communication. When it is not, petitions are broadcast (the IEEE address being part of the response payload). End devices will simply respond with the requested address, while a network coordinator or a router will also send the addresses of all the devices associated with it. This extended discovery protocol permits external devices to find out about devices in a network and the services that they offer, which endpoints can report when queried by the discovering device (which has previously obtained their addresses). Matching services can also be used. The use of cluster identifiers enforces the binding of complementary entities by means of the binding tables, which are maintained by ZigBee coordinators, as the table must be always available within a network and coordinators are most likely to have a permanent power supply. Backups, managed by higher-level layers, may be needed by some applications. Binding requires

61


an established communication link; after it exists, whether to add a new node to the network is decided, according to the application and security policies. Communication can happen right after the association. Direct addressing uses both radio address and endpoint identifier, whereas indirect addressing uses every relevant field (address, endpoint, cluster and attribute) and requires that they be sent to the network coordinator, which maintains associations and translates requests for communication. Indirect addressing is particularly useful to keep some devices very simple and minimize their need for storage. Besides these two methods, broadcast to all endpoints in a device is available, and group addressing is used to communicate with groups of endpoints belonging to a set of devices. Security services As one of its defining features, ZigBee provides facilities for carrying out secure communications, protecting establishment and transport of cryptographic keys, cyphering frames and controlling devices. It builds on the basic security framework defined in IEEE 802.15.4. This part of the architecture relies on the correct management of symmetric keys and the correct implementation of methods and security policies. Basic security model The basic mechanism to ensure confidentiality is the adequate protection of all keying material. Trust must be assumed in the initial installation of the keys, as well as in the processing of security information. In order for an implementation to globally work, its general correctness (e.g., conformance to specified behaviors) is assumed. Keys are the cornerstone of the security architecture; as such their protection is of paramount importance, and keys are never supposed to be transported through an insecure channel. There is a momentary exception to this rule, which occurs during the initial phase of the addition to the network of a previously unconfigured device. The ZigBee network model must take particular care of security considerations, as ad hoc networks may be physically accessible to external devices and the particular working environment cannot be foretold; likewise, different applications running concurrently and using the same transceiver to communicate are supposed 62


to be mutually trustworthy: for cost reasons the model does not assume a firewall exists between application-level entities. Within the protocol stack, different network layers are not cryptographically separated, so access policies are needed and correct design assumed. The open trust model within a device allows for key sharing, which notably decreases potential cost. Nevertheless, the layer which creates a frame is responsible for its security. If malicious devices may exist, every network layer payload must be cyphered, so unauthorized traffic can be immediately cut off. The exception, again, is the transmission of the network key, which confers a unified security layer to the network, to a new connecting device. Point-to-point encryption is also supported. Security architecture ZigBee uses 128-bit keys to implement its security mechanisms. A key can be associated either to a network, being usable by both ZigBee layers and the MAC sublayer, or to a link, acquired through preinstallation, agreement or transport. Establishment of link keys is based on a master key which controls link key correspondence. Ultimately, at least the initial master key must be obtained through a secure medium (transport or preinstallation), as the security of the whole network depends on it. Link and master keys are only visible to the application layer. Different services use different one-way variations of the link key in order to avoid leaks and security risks. Key distribution is one of the most important security functions of the network. A secure network will designate one special device which other devices trust for the distribution of security keys: the trust center. Ideally, devices will have the trust center address and initial master key preloaded; if a momentary vulnerability is allowed, it will be sent as described above. Typical applications without special security needs will use a network key provided by the trust center (through the initially insecure channel) to communicate. Thus, the trust center maintains both the network key and provides point-to-point security. Devices will only accept communications originating from a key provided by the trust center, except for the initial master key. The security architecture is distributed among the network layers as follows: 63


The MAC sublayer is capable of single-hop reliable communications. As a rule, the security level it is to use is specified by the upper layers.

The network layer manages routing, processing received messages and being capable of broadcasting requests. Outgoing frames will use the adequate link key according to the routing, if it is available; otherwise, the network key will be used to protect the payload from external devices.

The application layer offers key establishment and transport services to both ZDO and applications. It is also responsible for the propagation across the network of changes in devices within it, which may originate in the devices themselves (for instance, a simple status change) or in the trust manager (which may inform the network that a certain device is to be eliminated from it). It also routes requests from devices to the trust center and network key renewals from the trust center to all devices. Besides this, the ZDO maintains the security policies of the device.

The security levels infrastructure is based on CCM*, which adds encryption- and integrity-only features to CCM.

64


65


KEIL SOFTWARE TOOL(STEPS) 1. 2.Click on the Keil uVision Icon on DeskTop The following fig will appear

3. 4.

Click on the Project menu from the title bar Then Click on New Project

66


5.

Save the Project by typing suitable project name with no extension in u r own folder sited in either C:\ or D:\

6.

Then Click on Save button above. 67


7. 8.

Select the component for u r project. i.e. Atmel Click on the + Symbol beside of Atmel

9.

Select AT89C52 as shown below

68


10. 11.

Then Click on OK The Following fig will appear

12. 13. 14.

Then Click either YES or NOmostly NO Now your project is ready to USE Now double click on the Target1, you would get another option Source group 1 as shown in next page.

69


15.

Click on the file option from menu bar and select new

70


16.

The next

Documents

Zigbee