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Zhixiang Zhao1 and Qiyu Peng2 1 University of Shanghai for Science and Technology
2 Lawrence Berkeley National Laboratory ([email protected] )
A novel read-out electronics design
Conventional front-end electronics
OpenPET 16-ch front-end board
Conventional front-end electronics
16-ch front-end board
24 cm
16 cm
8 x 8 MPPC array
24 mm
Expensive, high power consumption and large board size. Channel-reduction is required when using analog SiPM array. • Degradation in performances (SNR, and timing resolution) • Some applications need analog signals from individual SiPM pixels (detectors
constructed with a monolithic crystal, dMiCE detectors and etc.)
Method to read out analog SiPMs
Channel reduction – sacrifice performances
Method to read out analog SiPMs
128-ch ASIC (PETsys Inc. )
• Limited Energy resolution (ToT) • No compensation for temperature
sensitive SiPM
Method to read out analog SiPMs
Readout electronics for two 128-ch ASICs (PETsys Inc. )
dSiPM
dSiPM
dSiPM
Low-cost high-performance readout electronics for analog SiPM
Simple and easy to implement • Low cost ($ 0.49 per channel). • Low profile (about 3mm x 3mm per channel) • Low power consumption: (20mW per channel)
Great Performances: • Energy measurement: Good linearity, Robust to noise, Large dynamic range • Potential ability to compensate the temperature-related gain fluctuations
automatically (real-time measurement) • High sampling rate and precisions to support innovative detector designs (sampling
rate: 1GHz, precision: 1 bit; equivalent to 50MHz, 6.6246 bits). • High accuracy in time measurement (Potential with strong evidences). • Highly flexible in trigger, digital signal processing, calibration / correction, and readout. • Easy to implement in large scale. Automatically establish the stable operation states –
highly tolerant to variances in the circuit. No need to manually tune the circuit.
1. Method
General idea
• No analog ADC, TDC, trigger and etc. • Everything is performed in a FPGA • Minimize board size and power consumption • Maximize performance and flexibility
FPGA (ADCs, TDCs, trigger circuits,
multiplexers temperature compensation and etc.)
SiPM Array Amplifiers
2. Simulation results
Simulation results
• Typical signals
Sampling rate: 1GHz, precision: 1 bit; equivalent to 50MHz, 6.6246 bits
Input signal Output signal
Simulation results
• Performance in energy calculation
Transfer function DNL INL
Simulation results
• Performance in energy calculation
Transfer function DNL INL
3. Experimental results
Experimental system
FPGA: Cyclone II (DE2 board)
Na 22, LYSO, R9800, -1300V
Single channel ADC circuit
Test pulse
SiPM MicroFC30035
DC current
Hardware, software and firmware specifications
Single channel ADC circuit • Cost: $0.49 per channel • Power consumption: 3mA x 6.6 V =20mW • Size: 3mm x 6mm on one side of the board
FPGA • Resources: one register and one counter per channel
System specs. • Sampling rate: 1GHz, precision: 1 bit (equivalent to 50MHz, 6.6246 bits) • Precision of energy calculation: 4.1250*10^6 charges per LSB. • Dynamic range: 12 bits (0~4092). • On line (FPGA firmware) event triggering and energy calculation. • RS232 data interface.
Energy spectrum
Single channel ADC circuit OpenPET
ER: 11.4%, Ratio of peak: 2.56 ER: 11.4%, Ratio of peak: 2.32
• Similar energy spectrum • The same energy resolutions. • Better linearity.
1275 keV
511 keV
1275 keV
511 keV
Test pulse experiments
Transfer function DNL
INL Repeatability (or noise performances)
DC measurements In
crea
se 1
00nA
per
step
DC measurements
Transfer function
DC measurements
DNL INL
SiPM V-I curve measurements
• Break down voltage is 24.7 V, which the same as that measured by the vendor of the SiPM chip.
• The measured dark current at +2.5V were 310 nA, which is close to the typical value (319 nA) provided by the vendor.
SiPM gain and DCR measurements
Performance of 16 FPGA-based TDCs
• Average TR: 72.5ps ± 31.0 ps
Tigger timing Trigger charges Note
Experimental results
<51.6*10^6 charges
• triggers on p.e.#47 of PMT R9800 (gain: 1.1*10^6), • p.e.#41 of MPPC S12572-50P (gain: 1.25*10^6), • p.e.#17 of SensL MicroFC-30035-SMT (gain: 3*10^6).
Theoretic calculation (non-ideal components)
19.4*10^6 charges (delay = 3.6ns)
• triggers on p.e.#18 of PMT R9800 (gain: 1.1*10^6), • p.e.#15.6 of MPPC S12572-50P (gain: 1.25*10^6), • p.e.#6 of SensL MicroFC-30035-SMT (gain: 3*10^6).
Theoretic calculation (ideal components)
5*10^6 charges (delay = 0 ns)
• triggers on p.e.#5 of PMT R9800 (gain: 1.1*10^6), • p.e.#4 of MPPC S12572-50P (gain: 1.25*10^6), • p.e.#2 of SensL MicroFC-30035-SMT (gain: 3*10^6).
4. Summary
Features of our design Simple and easy to implement Low cost ($ 0.49 per channel). Low profile (about 3mm x 3mm per channel) Low power consumption: (20mW per channel)
Great Performances: Energy measurement: Good linearity, Robust to noise, Large dynamic range Ability to compensate the temperature-related gain fluctuations automatically (real-time
measurement) High sampling rate and precisions to support innovative detector designs (sampling rate:
1GHz, precision: 1 bit; equivalent to 50MHz, 6.6246 bits). Highly flexible in trigger, digital signal processing, calibration / correction, and readout. Easy to implement in large scale. Automatically establish the stable operation states –
highly tolerant to variances in the circuit. No need to manually tune the circuit. • High accuracy in time measurement (more testing on going).
Conclusion: A simple technology with great potentials
Ideal method for analog SiPM detectors – PET detectors using continuous crystals – Future TOF PET detectors
Questions?