58
of Sheet Date: Title: Ver: A B C D 1 2 3 4 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR ASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE SCHEM, ROHS COMPLIANT SCH P/N: 0381513 PCB P/N: 1280681 DISCLAIMER THE DOCUMENTATION. THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. DISCLAIMER: ZC706 EVALUATION PLATFORM ZC706 EVALUATION PLATFORM HW-Z7-ZC706 (XC7Z045-FFG900) REV. 2.0 2-14-2014_15:01 58 1 BF 2.0 04

ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

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Page 1: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANYDOCUMENTATION.

INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OFCONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANYMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENTSTATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OFKIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR

XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, SCHEMATIC,AND/OR SPECIFICATION (THE “DOCUMENTATION”) TO YOU SOLELY FOR USE INTHE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX HARDWARE DEVICES.YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, DOWNLOAD, DISPLAY, POST,OR TRANSMIT THE DOCUMENTATION IN ANY FORM OR BY ANY MEANS INCLUDING,BUT NOT LIMITED TO, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING,OR OTHERWISE, WITHOUT THE PRIOR WRITTEN CONSENT OF XILINX.XILINX EXPRESSLY DISCLAIMS ANY LIABILITY ARISING OUT OF YOUR USE OFTHE DOCUMENTATION. XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION,TO CHANGE THE DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMESNO OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, ORTO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLYDISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT ORASSISTANCE THAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

DISCLAIMER

THE DOCUMENTATION.

THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICHCAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTYDOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THATIS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET.

ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANYAPPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETYDEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIALRISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE

("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS ATTHE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALLSPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

DISCLAIMER:

ZC706 EVALUATION PLATFORM

ZC706 EVALUATION PLATFORM HW-Z7-ZC706

(XC7Z045-FFG900)

REV. 2.0

2-14-2014_15:01

581 BF

2.0

04

Page 2: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

p.56

Linear Regulator

p.55

Switching Dual

Switching Dual

Linear Regulator

Linear Regulator

p.57

p.57

p.57

Linear Regulator

Linear Regulator

Switching Module

TDO

TDI

TDO

TDI

JackPWR

12V

Connector

Connector

SI570

TDI TDOTDO

FPGA

TDI

JTAG Chain

TDO SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

IIC AddressingMECHANICALS

PCA9548

0bxxxxx00

0bxxxxx00

ZC706 EVALUATION PLATFORM

ZC706 Block Diagram

DDR3 Components4x256Mx8 SDRAM

Zynq-7000

SD Card

Single Ended Clock

Reset/POR pushbuttons

XADC Hdr.

JTAG

10/100/1000

RGMII Only

Xcvr. PHY &Connector

& Connector ClocksConfigurableHDMI CODECUSB 2.0 ULPI IIC MUX

IIC EEPROM

Power Supply

Power Controller 1

2mm 2X7 JTAG Hdr.

TDI

TDO

TDI

Digilent USB JTAG Module

Analog Switch3-to-1

0b1110100

0b1011101

0b0111001

0b1010100

IIC Port Expander0b0100001

Module &

LEDs, Buttons

Connectors

DDR3 SODIMM

SFP+

Clock Recovery

Dual QUAD SPI

Pages 17-20

Page 43

Pages 23

USB UART

Page 39

Page 40

Page 38

IIC RTCIIC Port Expander

Page 37

Page 36

PMOD headerARM PL PJTAG

Switches

MGT and User SMAs

Page 44

PCIe x4

Page 42

Page 35Page 34Pages 32 & 33Page 31

Pages 29 & 30

FMC LPC

Page 28

Page 24

ConnectorFMC2 HPC

Page 22

Page 41

Page 21

Page 16

Page 34, 16

FMC HPC FMC LPC

U45,46,47

U1

FMC HPC

FMC LPC

PMBUS Controller

Page 58

Pages 48-57

PMBus 0x65 U48

p.50

p.51VCC1V8/VCCAUX 1.8V @ 10ASwitching Module

U98

U85VCC1V5_PL 1.5V @ 6ASwitching Module

p.52

VCC3V3/VCC3V3_FPGA 3.3V @ 10AU15 p.54

IIC EEPROM

IIC RTC

0b1100101

J60

p.48

0b1010001

0b1010000 SFP+

0b1101000 SI5324

DDR3 SODIMM0b10100000b0011000

p.49

Switching ModuleVADJ/VADJ_FPGA 2.5V @ 6AU86 p.53

Linear RegulatorMGTAVCC 1.0V @ 3A

Linear RegulatorMGTAVTT 1.2V @ 3A

p.57

p.57

U93

U94

MGTVCCAUX 1.8V @ 3AU95

VCC2V5 2.5V @ 1.5AU19

VCCAUX_IO 2.0V @ 3A

VTTDDR_PL 0.75V @ 3A

U92

p.56

Switching DualVCCPINT 1.0V @ 1.5AU104 p.55

Switching Dual

U104VCC1V5_PS 1.5V @ 2.5A

p.55

VCCP1V8 1.8V @ 1.5AU105 p.55

U105VCC3V3_PS 3.3V @ 2.5A

U27

U28

p.56VTTDDR_PS 0.75V @ 0.5A (3A Max)

Switching Regulator

U44

Linear RegulatorV33D_CTL1 3.3V @ 0.25AU20 p.49Ethernet PHY

U1

ADV7511

J37 J5

J3

U30

2X10 JTAG Hdr.

J62

Switching Module

U42

VCC5V0 5.0V @ 3A

VCCINT 1.00V @ 16A

04

BF2 58

2-14-2014_15:01 2.0

Page 3: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

VCC3V3

GND

VCC3V3

VCC3V3

GND

GND

GND

GRN

RED

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC3V3

GND

GNDGND

VCC3V3

DIR

VCCB

B

VCCA

GND

A

VCCO_0_Y13VCCO_0_Y15

RSVDVCC_T9RSVDVCC_R9RSVDVCC_U9DONE_0_AA9

CFGBVS_0_V9PROGRAM_B_0_Y9

INIT_B_0_W9TDI_0_P10TDO_0_Y10TMS_0_V10TCK_0_Y12

RSVDGND_AA12VCCBATT_0_P9

VN_0_T14VP_0_R15

VREFP_0_T15VREFN_0_R14DXP_0_U15

GNDADC_0_P14VCCADC_0_P15

DXN_0_U14

XC7Z045FF900BANK 0

VCCO_9_Y19VCCO_9_AC20

IO_L19N_T3_VREF_9_AE20IO_L19P_T3_9_AD20

IO_L14N_T2_SRCC_9_AB20IO_L14P_T2_SRCC_9_AB19IO_L13N_T2_MRCC_9_AA19IO_L13P_T2_MRCC_9_AA18IO_L12N_T1_MRCC_9_AD19IO_L12P_T1_MRCC_9_AD18IO_L11N_T1_SRCC_9_AC19IO_L11P_T1_SRCC_9_AC18IO_L6N_T0_VREF_9_AA20

IO_L6P_T0_9_Y20

XC7Z045FF900BANK 9

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 0, 9

Zynq Bank 0, 9

BF

2-14-2014_15:01

583

2.0

04

Y19AC20

AE20AD20AB20AB19AA19AA18AD19AD18AC19AC18AA20Y20

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

Y13Y15

T9R9U9AA9V9Y9W9P10Y10V10Y12AA12P9T14R15T15R14U15P14P15U14

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

41SFP_TX_DISABLE

REC_CLOCK_C_N 4343REC_CLOCK_C_P

48SM_FAN_TACH

48SM_FAN_PWMPWRCTL1_FMC_PG_C2M_LS38

44USER_SMA_CLOCK_P

44USER_SMA_CLOCK_N

5

6

4

1

2

3

U101 SC70_6

SN74AVC1T45

2

1

5%1/10W4.7KR8

FPGA_INIT_B3

12

J65

1

2

J6

16JTAG_TDOFPGA_TMS_BUF 16

VADJ_FPGA

VCC3V3_FPGA

FMC_LPC_TDO_FPGA_TDI 28

1

2 DNPDNPDNPR423

2

1R4260

1/10W5%

2

1

B2 TS518FE_FL35ETS518FE_FL35E

2

1

X5R25V0.1UFC1

35XADC_DXN

XADC_DXP 35

35XADC_VP_R

35XADC_VN_R

XADC_VCC 35

FPGA_PROG_B 38

FPGA_TCK_BUF 16

2

1

1%1/10W10.0KR255

VCCAUX

2

1 R94.7K1/10W5%

FPGA_VBATT 3

1

2

C20.1UF25VX5R

XADC_VREFP 35

XADC_AGND

1 2

34

DS2

LED-GRN-RED

2

1

3

200MW40V

BAS40-04

D7

NC

21

R381261

1/10W1%

1 2

1%1/10W

261R382

3 FPGA_VBATT

1

32

Q2

NDS331N460MW

1

21%1/10W261

R384

2

1 R3832611/10W1%

12

LED-GRN-SMT

DS3

FPGA_DONE3,36

VCC3V3_FPGA

VCC3V3_FPGA

1

25%1/10W

0

R427

2

1R4280

1/10W5%

2

1 R424DNPDNPDNP

1

2 DNPDNPDNPR425

FPGA_INIT_B 3

FPGA_DONE 3,3639PMOD1_7_LS

39PMOD1_5_LSPMOD1_4_LS 39

PMOD1_6_LS 39

Page 4: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_10_AJ12VCCO_10_AH15VCCO_10_AG18VCCO_10_AE14VCCO_10_AD17VCCO_10_AB13VCCO_10_AA16

IO_25_10_AA17IO_L24N_T3_10_AB16IO_L24P_T3_10_AB17IO_L23N_T3_10_AC16IO_L23P_T3_10_AC17IO_L22N_T3_10_AB14IO_L22P_T3_10_AB15

IO_L21N_T3_DQS_10_AC12IO_L21P_T3_DQS_10_AB12

IO_L20N_T3_10_AA14IO_L20P_T3_10_AA15

IO_L19N_T3_VREF_10_AC13IO_L19P_T3_10_AC14IO_L18N_T2_10_AD15IO_L18P_T2_10_AD16IO_L17N_T2_10_AE17IO_L17P_T2_10_AE18IO_L16N_T2_10_AE15IO_L16P_T2_10_AE16

IO_L15N_T2_DQS_10_AF17IO_L15P_T2_DQS_10_AF18

IO_L14N_T2_SRCC_10_AG15IO_L14P_T2_SRCC_10_AF15IO_L13N_T2_MRCC_10_AG16IO_L13P_T2_MRCC_10_AG17IO_L12N_T1_MRCC_10_AG14IO_L12P_T1_MRCC_10_AF14IO_L11N_T1_SRCC_10_AF13IO_L11P_T1_SRCC_10_AE13

IO_L10N_T1_10_AH12IO_L10P_T1_10_AG12

IO_L9N_T1_DQS_10_AD13IO_L9P_T1_DQS_10_AD14

IO_L8N_T1_10_AH13IO_L8P_T1_10_AH14IO_L7N_T1_10_AF12IO_L7P_T1_10_AE12

IO_L6N_T0_VREF_10_AH16IO_L6P_T0_10_AH17IO_L5N_T0_10_AK15IO_L5P_T0_10_AJ15IO_L4N_T0_10_AK16IO_L4P_T0_10_AJ16

IO_L3N_T0_DQS_10_AJ13IO_L3P_T0_DQS_10_AJ14

IO_L2N_T0_10_AJ18IO_L2P_T0_10_AH18IO_L1N_T0_10_AK12IO_L1P_T0_10_AK13

IO_0_10_AA13

XC7Z045FF900BANK 10

VCCO_11_W22VCCO_11_AK19VCCO_11_AJ22VCCO_11_AH25VCCO_11_AF21VCCO_11_AE24VCCO_11_AB23

IO_25_11_AC21IO_L24N_T3_11_AC23IO_L24P_T3_11_AC22IO_L23N_T3_11_AA23IO_L23P_T3_11_AA22IO_L22N_T3_11_AB24IO_L22P_T3_11_AA24

IO_L21N_T3_DQS_11_Y23IO_L21P_T3_DQS_11_Y22

IO_L20N_T3_11_Y21IO_L20P_T3_11_W21

IO_L19N_T3_VREF_11_AB22IO_L19P_T3_11_AB21IO_L18N_T2_11_AG19IO_L18P_T2_11_AF19IO_L17N_T2_11_AJ19IO_L17P_T2_11_AH19IO_L16N_T2_11_AK18IO_L16P_T2_11_AK17

IO_L15N_T2_DQS_11_AK20IO_L15P_T2_DQS_11_AJ20IO_L14N_T2_SRCC_11_AG20IO_L14P_T2_SRCC_11_AF20IO_L13N_T2_MRCC_11_AH21IO_L13P_T2_MRCC_11_AG21IO_L12N_T1_MRCC_11_AF22IO_L12P_T1_MRCC_11_AE22IO_L11N_T1_SRCC_11_AE23IO_L11P_T1_SRCC_11_AD23

IO_L10N_T1_11_AE21IO_L10P_T1_11_AD21

IO_L9N_T1_DQS_11_AF24IO_L9P_T1_DQS_11_AF23

IO_L8N_T1_11_AG25IO_L8P_T1_11_AG24IO_L7N_T1_11_AD24IO_L7P_T1_11_AC24

IO_L6N_T0_VREF_11_AH22IO_L6P_T0_11_AG22IO_L5N_T0_11_AH24IO_L5P_T0_11_AH23IO_L4N_T0_11_AJ24IO_L4P_T0_11_AJ23

IO_L3N_T0_DQS_11_AK21IO_L3P_T0_DQS_11_AJ21

IO_L2N_T0_11_AK23IO_L2P_T0_11_AK22IO_L1N_T0_11_AK25IO_L1P_T0_11_AJ25

IO_0_11_W23

XC7Z045FF900BANK 11

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 10, 11

Zynq Bank 10, 11

04

2.0

4 58

2-14-2014_15:01

BF

FMC_HPC_LA03_N 25

FMC_HPC_LA03_P 25

FMC_HPC_LA02_P 26FMC_HPC_LA02_N 26

FMC_HPC_LA04_N 26

FMC_HPC_LA04_P 26

FMC_HPC_LA08_N 25

FMC_HPC_LA08_P 25

26FMC_HPC_LA07_N 26FMC_HPC_LA07_P

FMC_HPC_LA09_N 24

FMC_HPC_LA09_P 24

FMC_HPC_LA11_N 26

FMC_HPC_LA11_P 26

FMC_HPC_LA13_N 24

FMC_HPC_LA13_P 24

FMC_HPC_LA16_N 25

FMC_HPC_LA16_P 25

FMC_HPC_LA15_N 26

FMC_HPC_LA15_P 26

FMC_HPC_LA00_CC_N 25

FMC_HPC_LA00_CC_P 25

FMC_HPC_LA01_CC_N 2424FMC_HPC_LA01_CC_P

FMC_HPC_LA06_N 2424FMC_HPC_LA06_P

FMC_HPC_LA05_N 24

FMC_HPC_LA05_P 24

FMC_HPC_CLK0_M2C_N 26

FMC_HPC_CLK0_M2C_P 26

FMC_HPC_LA10_N 24

FMC_HPC_LA10_P 24

FMC_HPC_LA12_N 25

FMC_HPC_LA12_P 25

FMC_HPC_LA14_N 24

FMC_HPC_LA14_P 2428FMC_LPC_LA02_N 28FMC_LPC_LA02_P

28FMC_LPC_LA03_N 28FMC_LPC_LA03_P

28FMC_LPC_LA09_N 28FMC_LPC_LA09_P

28FMC_LPC_LA06_NFMC_LPC_LA06_P 28

28FMC_LPC_LA10_N 28FMC_LPC_LA10_P

28FMC_LPC_LA15_N 28FMC_LPC_LA15_P

28FMC_LPC_LA12_N 28FMC_LPC_LA12_P

28FMC_LPC_LA11_N 28FMC_LPC_LA11_P

28FMC_LPC_LA13_N 28FMC_LPC_LA13_P

28FMC_LPC_LA16_N 28FMC_LPC_LA16_P

28FMC_LPC_LA14_N 28FMC_LPC_LA14_P

28FMC_LPC_LA04_N 28FMC_LPC_LA04_P

FMC_LPC_LA01_CC_N 2828FMC_LPC_LA01_CC_P

28FMC_LPC_LA00_CC_N 28FMC_LPC_LA00_CC_P

28FMC_LPC_LA05_N 28FMC_LPC_LA05_P

28FMC_LPC_LA08_N 28FMC_LPC_LA08_P

FMC_LPC_LA07_N 28

FMC_LPC_LA07_P 28

W22AK19AJ22AH25AF21AE24AB23

AC21AC23AC22AA23AA22AB24AA24Y23Y22Y21W21AB22AB21AG19AF19AJ19AH19AK18AK17AK20AJ20AG20AF20AH21AG21AF22AE22AE23AD23AE21AD21AF24AF23AG25AG24AD24AC24AH22AG22AH24AH23AJ24AJ23AK21AJ21AK23AK22AK25AJ25W23

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

AJ12AH15AG18AE14AD17AB13AA16

AA17AB16AB17AC16AC17AB14AB15AC12AB12AA14AA15AC13AC14AD15AD16AE17AE18AE15AE16AF17AF18AG15AF15AG16AG17AG14AF14AF13AE13AH12AG12AD13AD14AH13AH14AF12AE12AH16AH17AK15AJ15AK16AJ16AJ13AJ14AJ18AH18AK12AK13AA13

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

GPIO_SW_LEFT 38

47SI5324_INT_ALM_LSSI5324_RST_LS 47

47PCIE_WAKE_B_LSPCIE_PERST_LS 47

HDMI_INT 32

HDMI_R_D35 33

39PMOD1_2_LS

VADJ_FPGAVADJ_FPGA

38GPIO_DIP_SW2

38GPIO_DIP_SW1

GPIO_DIP_SW3 38

GPIO_LED_LEFT 3838GPIO_LED_RIGHT

USRCLK_N 34

21R154

22

1/10W

1%

39PL_PJTAG_TCK

PL_PJTAG_TDI 39

PL_PJTAG_TMS 39

IIC_SDA_MAIN_LS 36IIC_SCL_MAIN_LS 36

39PL_PJTAG_TDO

USRCLK_P 34

38GPIO_DIP_SW0

39PMOD1_3_LSIIC_RTC_IRQ_1_B 37

PL_PJTAG_TDO_R

39PMOD1_0_LSPMOD1_1_LS 39

38HDMI_SPDIF_OUT_LS

HDMI_R_SPDIF 33

FMC_LPC_CLK0_M2C_N 28

FMC_LPC_CLK0_M2C_P 28

Page 5: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_13_V25VCCO_13_U28VCCO_13_T21VCCO_13_R24VCCO_13_P27VCCO_13_N30

IO_25_13_V21IO_L24N_T3_13_W24IO_L24P_T3_13_V23IO_L23N_T3_13_V24IO_L23P_T3_13_U24IO_L22N_T3_13_V22IO_L22P_T3_13_U22

IO_L21N_T3_DQS_13_R23IO_L21P_T3_DQS_13_R22

IO_L20N_T3_13_T23IO_L20P_T3_13_T22

IO_L19N_T3_VREF_13_R21IO_L19P_T3_13_P21IO_L18N_T2_13_P24IO_L18P_T2_13_P23IO_L17N_T2_13_T25IO_L17P_T2_13_T24IO_L16N_T2_13_P26IO_L16P_T2_13_P25

IO_L15N_T2_DQS_13_N27IO_L15P_T2_DQS_13_N26

IO_L14N_T2_SRCC_13_T27IO_L14P_T2_SRCC_13_R27IO_L13N_T2_MRCC_13_R26IO_L13P_T2_MRCC_13_R25IO_L12N_T1_MRCC_13_U27IO_L12P_T1_MRCC_13_U26IO_L11N_T1_SRCC_13_V26IO_L11P_T1_SRCC_13_U25

IO_L10N_T1_13_W26IO_L10P_T1_13_W25

IO_L9N_T1_DQS_13_W28IO_L9P_T1_DQS_13_V27

IO_L8N_T1_13_W30IO_L8P_T1_13_W29IO_L7N_T1_13_V29IO_L7P_T1_13_V28

IO_L6N_T0_VREF_13_T28IO_L6P_T0_13_R28IO_L5N_T0_13_U29IO_L5P_T0_13_T29IO_L4N_T0_13_P29IO_L4P_T0_13_N29

IO_L3N_T0_DQS_13_P28IO_L3P_T0_DQS_13_N28

IO_L2N_T0_13_U30IO_L2P_T0_13_T30IO_L1N_T0_13_R30IO_L1P_T0_13_P30

IO_0_13_U21

XC7Z045FF900BANK 13

VCCO_12_Y29VCCO_12_AK29VCCO_12_AG28VCCO_12_AD27VCCO_12_AC30VCCO_12_AA26

IO_25_12_AA25IO_L24N_T3_12_AK26IO_L24P_T3_12_AJ26IO_L23N_T3_12_AH27IO_L23P_T3_12_AH26IO_L22N_T3_12_AK28IO_L22P_T3_12_AK27

IO_L21N_T3_DQS_12_AJ29IO_L21P_T3_DQS_12_AJ28

IO_L20N_T3_12_AK30IO_L20P_T3_12_AJ30

IO_L19N_T3_VREF_12_AH29IO_L19P_T3_12_AH28IO_L18N_T2_12_AF25IO_L18P_T2_12_AE25IO_L17N_T2_12_AG27IO_L17P_T2_12_AG26IO_L16N_T2_12_AG30IO_L16P_T2_12_AF30

IO_L15N_T2_DQS_12_AG29IO_L15P_T2_DQS_12_AF29IO_L14N_T2_SRCC_12_AF27IO_L14P_T2_SRCC_12_AE27IO_L13N_T2_MRCC_12_AF28IO_L13P_T2_MRCC_12_AE28IO_L12N_T1_MRCC_12_AD28IO_L12P_T1_MRCC_12_AC28IO_L11N_T1_SRCC_12_AC27IO_L11P_T1_SRCC_12_AB27

IO_L10N_T1_12_AE26IO_L10P_T1_12_AD25

IO_L9N_T1_DQS_12_AD29IO_L9P_T1_DQS_12_AC29

IO_L8N_T1_12_AE30IO_L8P_T1_12_AD30IO_L7N_T1_12_AD26IO_L7P_T1_12_AC26

IO_L6N_T0_VREF_12_AB26IO_L6P_T0_12_AB25IO_L5N_T0_12_AA28IO_L5P_T0_12_AA27IO_L4N_T0_12_AA29IO_L4P_T0_12_Y28

IO_L3N_T0_DQS_12_Y27IO_L3P_T0_DQS_12_Y26

IO_L2N_T0_12_AB30IO_L2P_T0_12_AB29IO_L1N_T0_12_AA30IO_L1P_T0_12_Y30

IO_0_12_Y25

XC7Z045FF900BANK 12

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 12, 13

Zynq Bank 12, 13

BF

2-14-2014_15:01

585

2.0

04

28FMC_LPC_CLK1_M2C_N 28FMC_LPC_CLK1_M2C_P

FMC_HPC_LA29_N 25

FMC_HPC_LA29_P 25

FMC_HPC_LA26_N 24

FMC_HPC_LA26_P 24

FMC_HPC_LA20_N 25

FMC_HPC_LA20_P 25

FMC_HPC_LA19_N 26

FMC_HPC_LA19_P 26

FMC_HPC_LA21_N 26

FMC_HPC_LA21_P 26

FMC_HPC_LA24_N 26

FMC_HPC_LA24_P 2626FMC_HPC_LA28_N

FMC_HPC_LA28_P 26

FMC_HPC_LA31_P 25FMC_HPC_LA31_N 25

FMC_HPC_LA33_N 25

FMC_HPC_LA33_P 25

FMC_HPC_LA30_N 26

FMC_HPC_LA30_P 26

FMC_HPC_LA32_N 26

FMC_HPC_LA32_P 26

FMC_HPC_LA17_CC_N 24

FMC_HPC_LA17_CC_P 24

FMC_HPC_LA18_CC_N 24

FMC_HPC_LA18_CC_P 24

FMC_HPC_LA23_N 24

FMC_HPC_LA23_P 24

FMC_HPC_LA22_P 25FMC_HPC_LA22_N 25

FMC_HPC_LA27_N 24

FMC_HPC_LA27_P 24

FMC_HPC_LA25_N 25

FMC_HPC_LA25_P 25

Y29AK29AG28AD27AC30AA26

AA25AK26AJ26AH27AH26AK28AK27AJ29AJ28AK30AJ30AH29AH28AF25AE25AG27AG26AG30AF30AG29AF29AF27AE27AF28AE28AD28AC28AC27AB27AE26AD25AD29AC29AE30AD30AD26AC26AB26AB25AA28AA27AA29Y28Y27Y26AB30AB29AA30Y30Y25

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

28FMC_LPC_LA23_N 28FMC_LPC_LA23_P

28FMC_LPC_LA20_P

28FMC_LPC_LA20_N

28FMC_LPC_LA19_N 28FMC_LPC_LA19_P 28FMC_LPC_LA22_N 28FMC_LPC_LA22_P 28FMC_LPC_LA27_N 28FMC_LPC_LA27_P 28FMC_LPC_LA26_N 28FMC_LPC_LA26_P

28FMC_LPC_LA21_P

28FMC_LPC_LA21_N

28FMC_LPC_LA25_P

28FMC_LPC_LA25_N

28FMC_LPC_LA24_P

28FMC_LPC_LA24_N

28FMC_LPC_LA28_PFMC_LPC_LA28_N 28

28FMC_LPC_LA31_N 28FMC_LPC_LA31_P

28FMC_LPC_LA30_P

28FMC_LPC_LA30_N

28FMC_LPC_LA33_N 28FMC_LPC_LA33_P

28FMC_LPC_LA18_CC_N 28FMC_LPC_LA18_CC_P

28FMC_LPC_LA32_N 28FMC_LPC_LA32_P

HDMI_R_HSYNC 33

HDMI_R_D32 33HDMI_R_D30 33

HDMI_R_D5 33

HDMI_R_D6 33

HDMI_R_D9 33

HDMI_R_D4 33

HDMI_R_D21 33

HDMI_R_D7 33

HDMI_R_D16 33

HDMI_R_D10 33HDMI_R_D17 33

HDMI_R_D8 33HDMI_R_D29 33

HDMI_R_D31 33HDMI_R_D18 33

HDMI_R_D28 33HDMI_R_D22 33

HDMI_R_D23 33HDMI_R_D20 33

V25U28T21R24P27N30

V21W24V23V24U24V22U22R23R22T23T22R21P21P24P23T25T24P26P25N27N26T27R27R26R25U27U26V26U25W26W25W28V27W30W29V29V28T28R28U29T29P29N29P28N28U30T30R30P30U21

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

HDMI_R_D19 33

VADJ_FPGA VADJ_FPGA

HDMI_R_VSYNC 33

HDMI_R_D33 33HDMI_R_CLK 33

HDMI_R_DE 33

HDMI_R_D34 33

28FMC_LPC_LA17_CC_N 28FMC_LPC_LA17_CC_P

28FMC_LPC_LA29_N 28FMC_LPC_LA29_P

FMC_HPC_CLK1_M2C_N 25

FMC_HPC_CLK1_M2C_P 25

33HDMI_R_D11GPIO_SW_RIGHT 38

Page 6: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_33_L6VCCO_33_J2VCCO_33_H5VCCO_33_F1VCCO_33_E4VCCO_33_B3

IO_25_VRP_33_L4IO_L24N_T3_33_A2IO_L24P_T3_33_A3IO_L23N_T3_33_B1IO_L23P_T3_33_B2IO_L22N_T3_33_C1IO_L22P_T3_33_C2

IO_L21N_T3_DQS_33_A4IO_L21P_T3_DQS_33_A5

IO_L20N_T3_33_B4IO_L20P_T3_33_B5

IO_L19N_T3_VREF_33_C3IO_L19P_T3_33_C4IO_L18N_T2_33_D1IO_L18P_T2_33_E1IO_L17N_T2_33_E2IO_L17P_T2_33_E3IO_L16N_T2_33_D3IO_L16P_T2_33_D4

IO_L15N_T2_DQS_33_D5IO_L15P_T2_DQS_33_E6

IO_L14N_T2_SRCC_33_F3IO_L14P_T2_SRCC_33_F4IO_L13N_T2_MRCC_33_E5IO_L13P_T2_MRCC_33_F5IO_L12N_T1_MRCC_33_G4IO_L12P_T1_MRCC_33_G5IO_L11N_T1_SRCC_33_H3IO_L11P_T1_SRCC_33_H4

IO_L10N_T1_33_G1IO_L10P_T1_33_H2

IO_L9N_T1_DQS_33_H1IO_L9P_T1_DQS_33_J1

IO_L8N_T1_33_G6IO_L8P_T1_33_H6IO_L7N_T1_33_F2IO_L7P_T1_33_G2

IO_L6N_T0_VREF_33_J6IO_L6P_T0_33_K6IO_L5N_T0_33_J5IO_L5P_T0_33_K5IO_L4N_T0_33_L2IO_L4P_T0_33_L3

IO_L3N_T0_DQS_33_K2IO_L3P_T0_DQS_33_K3

IO_L2N_T0_33_K1IO_L2P_T0_33_L1IO_L1N_T0_33_J3IO_L1P_T0_33_J4IO_0_VRN_33_L5

XC7Z045FF900BANK 33

VCCO_34_K9VCCO_34_J12VCCO_34_G8VCCO_34_F11VCCO_34_D7VCCO_34_C10VCCO_34_A6

IO_25_VRP_34_M10IO_L24N_T3_34_K12IO_L24P_T3_34_L12IO_L23N_T3_34_L9

IO_L23P_T3_34_L10IO_L22N_T3_34_K10IO_L22P_T3_34_K11

IO_L21N_T3_DQS_34_K8IO_L21P_T3_DQS_34_L8

IO_L20N_T3_34_J9IO_L20P_T3_34_J10

IO_L19N_T3_VREF_34_K7IO_L19P_T3_34_L7IO_L18N_T2_34_G7IO_L18P_T2_34_H7IO_L17N_T2_34_D6IO_L17P_T2_34_E7IO_L16N_T2_34_F7IO_L16P_T2_34_F8

IO_L15N_T2_DQS_34_H8IO_L15P_T2_DQS_34_J8

IO_L14N_T2_SRCC_34_E8IO_L14P_T2_SRCC_34_F9IO_L13N_T2_MRCC_34_G9IO_L13P_T2_MRCC_34_H9IO_L12N_T1_MRCC_34_D8IO_L12P_T1_MRCC_34_D9

IO_L11N_T1_SRCC_34_F10IO_L11P_T1_SRCC_34_G10

IO_L10N_T1_34_D10IO_L10P_T1_34_E10

IO_L9N_T1_DQS_34_G11IO_L9P_T1_DQS_34_H12

IO_L8N_T1_34_D11IO_L8P_T1_34_E11IO_L7N_T1_34_H11IO_L7P_T1_34_J11

IO_L6N_T0_VREF_34_C8IO_L6P_T0_34_C9IO_L5N_T0_34_B6IO_L5P_T0_34_C6IO_L4N_T0_34_B7IO_L4P_T0_34_C7

IO_L3N_T0_DQS_34_A7IO_L3P_T0_DQS_PUDC_B_34_A8

IO_L2N_T0_34_A9IO_L2P_T0_34_B9

IO_L1N_T0_34_A10IO_L1P_T0_34_B10IO_0_VRN_34_M12

XC7Z045FF900BANK 34

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 33, 34

Zynq Bank 33, 34

04

2.0

6 58

2-14-2014_15:01

BF

K9J12G8

F11D7

C10A6

M10K12L12L9L10K10K11K8L8J9J10K7L7G7H7D6E7F7F8H8J8E8F9G9H9D8D9F10G10D10E10G11H12D11E11H11J11C8C9B6C6B7C7A7A8A9B9A10B10M12

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

23PL_DDR3_D1523PL_DDR3_D1423PL_DDR3_D1123PL_DDR3_D9

23PL_DDR3_D8

23PL_DDR3_D1223PL_DDR3_D13

23PL_DDR3_D1023PL_DDR3_DM1

23PL_DDR3_D4

23PL_DDR3_DM0

23PL_DDR3_D7PL_DDR3_D6 23

23PL_DDR3_D2

23PL_DDR3_D3

23PL_DDR3_D1

23PL_DDR3_D0

23PL_DDR3_D5

PL_DDR3_D24 23

PL_DDR3_D31 23

PL_DDR3_D27 23PL_DDR3_D26 23

PL_DDR3_D28 23

PL_DDR3_D25 23PL_DDR3_D29 23

PL_DDR3_D30 23

23PL_DDR3_D16

23PL_DDR3_D23

23PL_DDR3_D20

23PL_DDR3_D21

23PL_DDR3_DM2

23PL_DDR3_D22

23PL_DDR3_D17

23PL_DDR3_D18

23PL_DDR3_D19

L6J2H5F1E4B3

L4A2A3B1B2C1C2A4A5B4B5C3C4D1E1E2E3D3D4D5E6F3F4E5F5G4G5H3H4G1H2H1J1G6H6F2G2J6K6J5K5L2L3K2K3K1L1J3J4L5

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

VRN_336

VRP_336

VTTVREF_SODIMM

VCC1V5_PL

1

2

C3260.01UF25VX7R

VCC1V5_PL

VCC1V5_PL

1

2 1%1/10W80.6R511

2

1 R51080.61/10W1%

NC

6VRN_33

23PL_DDR3_DQS0_P

23PL_DDR3_DQS0_N

23PL_DDR3_DQS1_P

23PL_DDR3_DQS1_N

23PL_DDR3_DQS2_P

23PL_DDR3_DQS2_N

PL_DDR3_DQS3_P 23PL_DDR3_DQS3_N 23

GPIO_LED_CENTER 38

6VRP_33

23PL_DDR3_DM3

PL_DDR3_A8 23PL_DDR3_A13 23PL_DDR3_A1 23PL_DDR3_A3 23PL_CPU_RESET 38PL_DDR3_BA2 23PL_DDR3_CKE1 23PL_DDR3_A11 23PL_DDR3_A15 23PL_DDR3_A5 23PL_DDR3_ODT1 23

PL_DDR3_S0_B 23PL_DDR3_RAS_B 23PL_DDR3_A2 23PL_DDR3_A4 23PL_DDR3_A12 23PL_DDR3_A14 23PL_DDR3_A0 23PL_DDR3_CKE0 23

23PL_DDR3_CLK0_PPL_DDR3_CLK0_N 23

23PL_DDR3_CLK1_P

23PL_DDR3_CLK1_N

34SYSCLK_P

34SYSCLK_NPL_DDR3_A6 23PL_DDR3_A7 23PL_DDR3_A9 23PL_DDR3_S1_B 23PL_DDR3_BA0 23PL_DDR3_WE_B 23PL_DDR3_CAS_B 23PL_DDR3_A10 23PL_DDR3_BA1 23

PL_DDR3_D39 23

PL_DDR3_D38 23PL_DDR3_D35 23PL_DDR3_DQS4_P 23PL_DDR3_DQS4_N 23PL_DDR3_D36 23PL_DDR3_D32 23PL_DDR3_D37 23PL_DDR3_D33 23PL_DDR3_DM4 23

PL_DDR3_TEMP_EVENT 23

NC

VTTVREF_SODIMM

1

2

C7130.01UF25VX7R

PL_DDR3_D34 23

PL_DDR3_ODT0 23

Page 7: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCO_35_L16VCCO_35_H15VCCO_35_E14VCCO_35_D17VCCO_35_B13VCCO_35_A16

IO_25_VRP_35_M16IO_L24N_T3_AD15N_35_A12IO_L24P_T3_AD15P_35_A13

IO_L23N_T3_35_A14IO_L23P_T3_35_B14

IO_L22N_T3_AD7N_35_B11IO_L22P_T3_AD7P_35_C11

IO_L21N_T3_DQS_AD14N_35_A15IO_L21P_T3_DQS_AD14P_35_B15

IO_L20N_T3_AD6N_35_B12IO_L20P_T3_AD6P_35_C12IO_L19N_T3_VREF_35_C13

IO_L19P_T3_35_C14IO_L18N_T2_AD13N_35_A17IO_L18P_T2_AD13P_35_B17IO_L17N_T2_AD5N_35_B16IO_L17P_T2_AD5P_35_C17

IO_L16N_T2_35_C16IO_L16P_T2_35_D16

IO_L15N_T2_DQS_AD12N_35_E17IO_L15P_T2_DQS_AD12P_35_F17IO_L14N_T2_AD4N_SRCC_35_D14IO_L14P_T2_AD4P_SRCC_35_D15

IO_L13N_T2_MRCC_35_E15IO_L13P_T2_MRCC_35_E16IO_L12N_T1_MRCC_35_F14IO_L12P_T1_MRCC_35_F15IO_L11N_T1_SRCC_35_D13IO_L11P_T1_SRCC_35_E13

IO_L10N_T1_AD11N_35_E12IO_L10P_T1_AD11P_35_F13

IO_L9N_T1_DQS_AD3N_35_F12IO_L9P_T1_DQS_AD3P_35_G12

IO_L8N_T1_AD10N_35_G14IO_L8P_T1_AD10P_35_G15IO_L7N_T1_AD2N_35_G16IO_L7P_T1_AD2P_35_G17IO_L6N_T0_VREF_35_H16

IO_L6P_T0_35_J16IO_L5N_T0_AD9N_35_J15IO_L5P_T0_AD9P_35_K15

IO_L4N_T0_35_H14IO_L4P_T0_35_J14

IO_L3N_T0_DQS_AD1N_35_K13IO_L3P_T0_DQS_AD1P_35_L13

IO_L2N_T0_AD8N_35_H13IO_L2P_T0_AD8P_35_J13IO_L1N_T0_AD0N_35_L14IO_L1P_T0_AD0P_35_L15

IO_0_VRN_35_K16

XC7Z045FF900BANK 35

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 35

Zynq Bank 35

BF

2-14-2014_15:01

587

2.0

04

GPIO_LED_0 38

XADC_GPIO_2 35

XADC_GPIO_1 35

GPIO_SW_CENTER 38

XADC_GPIO_0 35

XADC_GPIO_3 35

7VRN_35

7VRP_35L16H15E14D17B13A16

M16A12A13A14B14B11C11A15B15B12C12C13C14A17B17B16C17C16D16E17F17D14D15E15E16F14F15D13E13E12F13F12G12G14G15G16G17H16J16J15K15H14J14K13L13H13J13L14L15K16

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

VCC1V5_PL

1

2 1%1/10W80.6R105

2

1 R10480.61/10W1%

VCC1V5_PL

VRP_357

VRN_357

PL_DDR3_DQS5_N 23

PL_DDR3_DQS5_P 23

PL_DDR3_DQS6_N 23

PL_DDR3_DQS7_P 23PL_DDR3_DQS7_N 23

23PL_DDR3_DM7

PL_DDR3_DQS6_P 23

PL_DDR3_D62 23

PL_DDR3_D54 23

PL_DDR3_D49 23

PL_DDR3_D52 23PL_DDR3_D53 23

PL_DDR3_DM6 23

PL_DDR3_D50 23

PL_DDR3_D55 23

PL_DDR3_D47 23

PL_DDR3_D44 23PL_DDR3_DM5 23

PL_DDR3_D45 23

PL_DDR3_D41 23

PL_DDR3_D42 23

1

2

C3270.01UF25VX7R

VTTVREF_SODIMM

PL_DDR3_RESET_B 23PL_DDR3_D43 23

PL_DDR3_D46 23

PL_DDR3_D40 23

PL_DDR3_D48 23

PL_DDR3_D51 23

PL_DDR3_D57 23PL_DDR3_D56 23

PL_DDR3_D61 23PL_DDR3_D63 23

23PL_DDR3_D59PL_DDR3_D60 23PL_DDR3_D58 23

XADC_AD1_R_N 46

XADC_AD1_R_P 4635XADC_VAUX8N_R

XADC_VAUX8P_R 35

XADC_VAUX0N_R 35

XADC_VAUX0P_R 35

Page 8: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MGTREFCLK1N_111_W7MGTREFCLK1P_111_W8MGTREFCLK0N_111_U7MGTREFCLK0P_111_U8MGTXRXN3_111_AA3MGTXRXP3_111_AA4MGTXTXN3_111_V1MGTXTXP3_111_V2MGTXRXN2_111_Y5MGTXRXP2_111_Y6MGTXTXN2_111_W3MGTXTXP2_111_W4MGTXRXN1_111_AB5MGTXRXP1_111_AB6MGTXTXN1_111_Y1MGTXTXP1_111_Y2MGTXRXN0_111_AC3MGTXRXP0_111_AC4MGTXTXN0_111_AB1MGTXTXP0_111_AB2

XC7Z045FF900BANK 111

MGTREFCLK1N_109_AF9MGTREFCLK1P_109_AF10MGTREFCLK0N_109_AD9MGTREFCLK0P_109_AD10

MGTXRXN3_109_AE7MGTXRXP3_109_AE8MGTXTXN3_109_AK1MGTXTXP3_109_AK2MGTXRXN2_109_AG7MGTXRXP2_109_AG8MGTXTXN2_109_AJ3MGTXTXP2_109_AJ4MGTXRXN1_109_AJ7MGTXRXP1_109_AJ8MGTXTXN1_109_AK5MGTXTXP1_109_AK6MGTXRXN0_109_AH9MGTXRXP0_109_AH10MGTXTXN0_109_AK9MGTXTXP0_109_AK10

XC7Z045FF900BANK 109

MGTRREF_112_AB9MGTAVTTRCAL_112_AB10

MGTREFCLK1N_112_R7MGTREFCLK1P_112_R8MGTREFCLK0N_112_N7MGTREFCLK0P_112_N8

MGTXRXN3_112_P5MGTXRXP3_112_P6MGTXTXN3_112_N3MGTXTXP3_112_N4MGTXRXN2_112_T5MGTXRXP2_112_T6MGTXTXN2_112_P1MGTXTXP2_112_P2MGTXRXN1_112_U3MGTXRXP1_112_U4MGTXTXN1_112_R3MGTXTXP1_112_R4MGTXRXN0_112_V5MGTXRXP0_112_V6MGTXTXN0_112_T1MGTXTXP0_112_T2

XC7Z045FF900BANK 112

MGTREFCLK1N_110_AC7MGTREFCLK1P_110_AC8MGTREFCLK0N_110_AA7MGTREFCLK0P_110_AA8

MGTXRXN3_110_AD5MGTXRXP3_110_AD6MGTXTXN3_110_AD1MGTXTXP3_110_AD2MGTXRXN2_110_AF5MGTXRXP2_110_AF6MGTXTXN2_110_AE3MGTXTXP2_110_AE4MGTXRXN1_110_AG3MGTXRXP1_110_AG4MGTXTXN1_110_AF1MGTXTXP1_110_AF2MGTXRXN0_110_AH5MGTXRXP0_110_AH6MGTXTXN0_110_AH1MGTXTXP0_110_AH2

XC7Z045FF900BANK 110

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

Zynq MGT Banks

Zynq MGT Banks

BF

2-14-2014_15:01

588

2.0

04

AC7AC8AA7AA8AD5AD6AD1AD2AF5AF6AE3AE4AG3AG4AF1AF2AH5AH6AH1AH2

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

AB9AB10R7R8N7N8P5P6N3N4T5T6P1P2U3U4R3R4V5V6T1T2

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

AF9AF10AD9AD10AE7AE8AK1AK2AG7AG8AJ3AJ4AJ7AJ8AK5AK6AH9AH10AK9AK10

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

W7W8U7U8AA3AA4V1V2Y5Y6W3W4AB5AB6Y1Y2AC3AC4AB1AB2

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

NCNC

21

X5R

25V

0.1UF

C648

1 2

C647

0.1UF

25V

X5R

FMC_HPC_GBTCLK1_M2C_C_P 8

FMC_HPC_GBTCLK1_M2C_C_N 824 FMC_HPC_GBTCLK1_M2C_N

24 FMC_HPC_GBTCLK1_M2C_P

21

X5R

25V

0.1UF

C644

1 2

C643

0.1UF

25V

X5R

MGTAVTT

2

1

1%1/10W100R252

21

X5R

25V

0.1UF

C646

1 2

C645

0.1UF

25V

X5RFMC_HPC_GBTCLK0_M2C_P24

FMC_HPC_GBTCLK0_M2C_N24 8FMC_HPC_GBTCLK0_M2C_C_N

8FMC_HPC_GBTCLK0_M2C_C_P

8FMC_LPC_GBTCLK0_M2C_C_P

8FMC_LPC_GBTCLK0_M2C_C_NFMC_LPC_GBTCLK0_M2C_N28

FMC_LPC_GBTCLK0_M2C_P28

FMC_HPC_GBTCLK0_M2C_C_P8FMC_HPC_GBTCLK0_M2C_C_N8

FMC_HPC_DP0_C2M_P 24FMC_HPC_DP0_C2M_N 24

24FMC_HPC_DP0_M2C_P24FMC_HPC_DP0_M2C_N24FMC_HPC_DP1_C2M_P24FMC_HPC_DP1_C2M_N24FMC_HPC_DP1_M2C_P24FMC_HPC_DP1_M2C_N24FMC_HPC_DP2_C2M_P24FMC_HPC_DP2_C2M_N24FMC_HPC_DP2_M2C_P24FMC_HPC_DP2_M2C_N

FMC_HPC_DP3_C2M_P 24FMC_HPC_DP3_C2M_N 24

24FMC_HPC_DP3_M2C_P24FMC_HPC_DP3_M2C_N

SI5324_OUT_C_P 4343SI5324_OUT_C_N

8FMC_HPC_GBTCLK1_M2C_C_N8FMC_HPC_GBTCLK1_M2C_C_P

24FMC_HPC_DP4_C2M_P24FMC_HPC_DP4_C2M_N

FMC_HPC_DP4_M2C_P 24FMC_HPC_DP4_M2C_N 24FMC_HPC_DP5_C2M_P 24FMC_HPC_DP5_C2M_N 24FMC_HPC_DP5_M2C_P 24FMC_HPC_DP5_M2C_N 24

24FMC_HPC_DP6_C2M_P24FMC_HPC_DP6_C2M_N

FMC_HPC_DP6_M2C_P 24FMC_HPC_DP6_M2C_N 24FMC_HPC_DP7_C2M_P 24FMC_HPC_DP7_C2M_N 24

24FMC_HPC_DP7_M2C_P24FMC_HPC_DP7_M2C_N

2

1

X5R25V0.1UFC653

1

2

C6520.1UF25VX5R

8FMC_LPC_GBTCLK0_M2C_C_P

SFP_TX_P 41SFP_TX_N 41

41SFP_RX_NSFP_RX_P 41

44SMA_MGT_REFCLK_N 44SMA_MGT_REFCLK_P

44SMA_MGT_RX_N 44SMA_MGT_RX_PSMA_MGT_TX_N 44

SMA_MGT_TX_P 44

28FMC_LPC_DP0_C2M_P28FMC_LPC_DP0_C2M_N

FMC_LPC_DP0_M2C_P 28FMC_LPC_DP0_M2C_N 28

8FMC_LPC_GBTCLK0_M2C_C_N

PCIE_TX3_P 4242PCIE_TX3_N42PCIE_RX3_P

PCIE_RX3_N 4242PCIE_TX2_P42PCIE_TX2_N

PCIE_RX2_P 42PCIE_RX2_N 42PCIE_TX1_P 42PCIE_TX1_N 42

42PCIE_RX1_P42PCIE_RX1_N

PCIE_TX0_P 42PCIE_TX0_N 42

42PCIE_RX0_PPCIE_RX0_N 42

42PCIE_CLK_QO_P42PCIE_CLK_QO_N

NCNC

Page 9: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

VCCO_MIO0_500_F21VCCO_MIO0_500_E24VCCO_MIO0_500_B23

PS_MIO15_500_C22PS_MIO14_500_B22PS_MIO13_500_F22PS_MIO12_500_E21PS_MIO11_500_A23PS_MIO10_500_E22PS_MIO9_500_A24PS_MIO8_500_C21PS_MIO7_500_B24PS_MIO6_500_D24PS_MIO5_500_C24PS_MIO4_500_E23PS_MIO3_500_C23PS_MIO2_500_F23PS_MIO1_500_D23PS_MIO0_500_F24PS_CLK_500_A22

PS_POR_B_500_D21

XC7Z045FF900BANK 500

VCCO_MIO1_501_K19VCCO_MIO1_501_J22VCCO_MIO1_501_G18VCCO_MIO1_501_C20

PS_MIO_VREF_501_H19PS_SRST_B_501_B19PS_MIO16_501_L19PS_MIO17_501_K21PS_MIO18_501_K20PS_MIO19_501_J20PS_MIO20_501_M20PS_MIO21_501_J19PS_MIO22_501_L20PS_MIO23_501_J21PS_MIO24_501_M19PS_MIO25_501_G19PS_MIO26_501_M17PS_MIO27_501_G20PS_MIO28_501_L17PS_MIO29_501_H22PS_MIO30_501_L18PS_MIO31_501_H21PS_MIO32_501_K17PS_MIO33_501_G22PS_MIO34_501_K18PS_MIO35_501_G21PS_MIO36_501_H17PS_MIO37_501_B21PS_MIO38_501_A20PS_MIO39_501_F18PS_MIO40_501_B20PS_MIO41_501_J18PS_MIO42_501_D20PS_MIO43_501_E18PS_MIO44_501_E20PS_MIO45_501_H18PS_MIO46_501_F20PS_MIO47_501_A18PS_MIO48_501_C19PS_MIO49_501_D18PS_MIO50_501_A19PS_MIO51_501_F19PS_MIO52_501_D19PS_MIO53_501_C18

XC7Z045FF900BANK 501

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Banks 500, 501

Zynq Banks 500, 501

BF

2-14-2014_15:01

589

2.0

04

SDIO_CLK_LS_R

21R541

49.9

1/20W

1%

K19J22G18C20

H19B19L19K21K20J20M20J19L20J21M19G19M17G20L17H22L18H21K17G22K18G21H17B21A20F18B20J18D20E18E20H18F20A18C19D18A19F19D19C18

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

F21E24B23

C22B22F22E21A23E22A24C21B24D24C24E23C23F23D23F24A22D21

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

PS_MIO8 15

PHY_RESET_B_AND 29

SDIO_CD_DAT3_LS 2238IIC_MUX_RESET_B_LS

22SDIO_SDWP 22SDIO_SDDET

21QSPI1_CLK

QSPI0_CS_B 21

USB_STP 31

USB_NXT 31

QSPI1_IO3 21

15,21QSPI0_IO0

15,21QSPI0_IO1

USB_DATA4 31

USB_DIR 31

VCCP1V8

VCCP1V8

QSPI1_CS_B 21

QSPI1_IO0 2121QSPI1_IO1

QSPI1_IO2 21

15,21QSPI0_CLKQSPI0_IO3 15,21

QSPI0_IO2 15,21

2 1R352

1.00K

1/16W

1%

PS_CLK 34

PS_POR_B 15,29,312 1

1%

1/16W

1.00K

R353

1

2

C3280.01UF25VX7R

VCCP1V8

PHY_MDIO 29PHY_MDC 2936PS_SDA_MAIN

36PS_SCL_MAIN

40USB_UART_TX

40USB_UART_RX

SDIO_DAT2_LS 22SDIO_DAT1_LS 22SDIO_DAT0_LS 22SDIO_CMD_LS 22

USB_DATA7 31USB_DATA6 31USB_DATA5 31USB_CLKOUT 31USB_DATA3 31USB_DATA2 31USB_DATA1 31USB_DATA0 31

PHY_RX_CTRL 29PHY_RXD3 29PHY_RXD2 2929PHY_RXD1

PHY_RXD0 29PHY_RX_CLK 29PHY_TX_CTRL 29PHY_TXD3 29PHY_TXD2 29PHY_TXD1 29PHY_TXD0 29PHY_TX_CLK 2915PS_SRST_B

PS_MIO_VREF

15,31USB_RESET_B_AND

SDIO_CLK_LS 22

Page 10: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GNDofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PS_DDR_VREF1_502_L24PS_DDR_VREF0_502_L22

VCCO_DDR_502_M23VCCO_DDR_502_L26VCCO_DDR_502_K29VCCO_DDR_502_H25VCCO_DDR_502_G28VCCO_DDR_502_D27VCCO_DDR_502_C30VCCO_DDR_502_A26

PS_DDR_DQ31_502_M30PS_DDR_DQ30_502_L30PS_DDR_DQ29_502_M29PS_DDR_DQ28_502_K30

PS_DDR_DQS_N3_502_L29PS_DDR_DQS_P3_502_L28

PS_DDR_DM3_502_K28PS_DDR_DQ27_502_J28PS_DDR_DQ26_502_J30PS_DDR_DQ25_502_K27PS_DDR_DQ24_502_J29PS_DDR_DQ23_502_F30PS_DDR_DQ22_502_G30PS_DDR_DQ21_502_F28PS_DDR_DQ20_502_E30

PS_DDR_DQS_N2_502_F29PS_DDR_DQS_P2_502_G29

PS_DDR_DM2_502_H29PS_DDR_DQ19_502_E28PS_DDR_DQ18_502_H28PS_DDR_DQ17_502_G27PS_DDR_DQ16_502_H27

PS_DDR_RAS_B_502_N24PS_DDR_CAS_B_502_M24PS_DDR_WE_B_502_N23PS_DDR_CKE_502_M22

PS_DDR_CS_B_502_N22PS_DDR_ODT_502_L23PS_DDR_BA0_502_M27PS_DDR_BA1_502_M26PS_DDR_BA2_502_M25PS_DDR_A0_502_L25PS_DDR_A1_502_K26PS_DDR_A2_502_L27PS_DDR_CKN_502_J25PS_DDR_CKP_502_K25PS_DDR_VRN_502_N21PS_DDR_VRP_502_M21PS_DDR_A4_502_J26PS_DDR_A3_502_G25PS_DDR_A6_502_H26PS_DDR_A5_502_G24PS_DDR_A8_502_F27PS_DDR_A7_502_K22PS_DDR_A10_502_G26PS_DDR_A9_502_J23PS_DDR_A12_502_K23PS_DDR_A11_502_H24PS_DDR_A14_502_J24PS_DDR_A13_502_H23

PS_DDR_DQ14_502_D28PS_DDR_DQ15_502_D29PS_DDR_DQ12_502_C28PS_DDR_DQ13_502_D30

PS_DDR_DQS_P1_502_C29PS_DDR_DQS_N1_502_B29

PS_DDR_DM1_502_B30PS_DDR_DQ10_502_A30PS_DDR_DQ11_502_A28PS_DDR_DQ8_502_A29PS_DDR_DQ9_502_A27PS_DDR_DQ6_502_D26PS_DDR_DQ7_502_E27PS_DDR_DQ4_502_B25PS_DDR_DQ5_502_E26

PS_DDR_DQS_P0_502_C26PS_DDR_DQS_N0_502_B26

PS_DDR_DM0_502_C27PS_DDR_DQ2_502_B27PS_DDR_DQ3_502_D25PS_DDR_DQ0_502_A25PS_DDR_DQ1_502_E25

PS_DDR_DRST_B_502_F25

XC7Z045FF900BANK 502

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Bank 502

Zynq Bank 502

04

2.0

10 58

2-14-2014_15:01

BF

PS_DDR3_DQ27 20

20PS_DDR3_DQS3_PPS_DDR3_DM3 20

19PS_DDR3_DQ20 19PS_DDR3_DQS2_NPS_DDR3_DQS2_P 19

19PS_DDR3_DM2

PS_DDR3_RAS_B 17,18,19,2017,18,19,20PS_DDR3_CAS_B

PS_DDR3_WE_B 17,18,19,2017,18,19,20PS_DDR3_CKE

PS_DDR3_CS_B 17,18,19,20

PS_DDR3_ODT 17,18,19,20

PS_DDR3_BA0 17,18,19,20

17,18,19,20PS_DDR3_A2

PS_DDR3_DQS3_N 20

PS_DDR3_DQ25 20PS_DDR3_DQ26 20

19PS_DDR3_DQ19 19PS_DDR3_DQ18 19PS_DDR3_DQ17 19PS_DDR3_DQ16

17,18,19,20PS_DDR3_CLK_NPS_DDR3_CLK_P 17,18,19,20

PS_DDR3_A4 17,18,19,20

PS_DDR3_A3 17,18,19,20

PS_DDR3_A6 17,18,19,20

PS_DDR3_A5 17,18,19,20

PS_DDR3_A8 17,18,19,20

PS_DDR3_A7 17,18,19,20

PS_DDR3_A10 17,18,19,20

PS_DDR3_A9 17,18,19,20

PS_DDR3_A12 17,18,19,20

PS_DDR3_A11 17,18,19,20

PS_DDR3_A14 17,18,19,20

PS_DDR3_A13 17,18,19,2018PS_DDR3_DQ15

18PS_DDR3_DQ12PS_DDR3_DQS1_P 18

18PS_DDR3_DQS1_N 18PS_DDR3_DM1

18PS_DDR3_DQ9 18PS_DDR3_DQ10 18PS_DDR3_DQ8PS_DDR3_DQ4 17

PS_DDR3_DQ2 17

PS_DDR3_DQ5 17

PS_DDR3_DQ0 1717PS_DDR3_DQS0_P

PS_DDR3_DQS0_N 17

L24L22

M23L26K29H25G28D27C30A26

M30L30M29K30L29L28K28J28J30K27J29F30G30F28E30F29G29H29E28H28G27H27N24M24N23M22N22L23M27M26M25L25K26L27J25K25N21M21J26G25H26G24F27K22G26J23K23H24J24H23D28D29C28D30C29B29B30A30A28A29A27D26E27B25E26C26B26C27B27D25A25E25F25

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

18PS_DDR3_DQ13

10PS_VRP

10PS_VRN

PS_DDR3_DM0 17

PS_DDR3_DQ24 20

18PS_DDR3_DQ11

PS_DDR3_DQ7 17

PS_DDR3_DQ3 17

PS_DDR3_DQ6 17

VTTVREF_PS

VTTVREF_PS

1

2

C3300.01UF25VX7R

VCC1V5_PS

2

1 R10780.61/10W1%

2

1

X7R25V0.01UFC329

1

2 1%1/10W80.6R106

10PS_VRP 10PS_VRN

VCC1V5_PS

17,18,19,20PS_DDR3_RESET_B

PS_DDR3_DQ1 17

18PS_DDR3_DQ14

17,18,19,20PS_DDR3_A1

17,18,19,20PS_DDR3_A0PS_DDR3_BA2 17,18,19,20PS_DDR3_BA1 17,18,19,20

19PS_DDR3_DQ21

19PS_DDR3_DQ22

19PS_DDR3_DQ23

PS_DDR3_DQ28 20PS_DDR3_DQ29 20PS_DDR3_DQ30 20PS_DDR3_DQ31 20

Page 11: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCCAUX

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCAUX_M11VCCAUX_N10VCCAUX_R10VCCAUX_U10VCCAUX_W10VCCAUX_Y11

XC7Z045FF900BANK VCCAUX

VCCPINT_N16VCCPINT_P17VCCPINT_R18VCCPINT_T17VCCPINT_T19VCCPINT_U18

XC7Z045FF900BANK VCCPINT

MGTVCCAUX_T7MGTVCCAUX_V7

XC7Z045FF900BANK MGTVCCAUX

VCCAUX_IO_G0_P11VCCAUX_IO_G0_T11VCCAUX_IO_G0_V11

XC7Z045FF900BANK VCCAUX_IO_G0

VCCINT_M13VCCINT_M15VCCINT_N12VCCINT_N14VCCINT_P13VCCINT_R12VCCINT_R16VCCINT_T13VCCINT_U12VCCINT_U16VCCINT_V13VCCINT_V15VCCINT_W12VCCINT_W14VCCINT_W16VCCINT_Y17

XC7Z045FF900BANK VCCINT

VCCPAUX_N20VCCPAUX_P19VCCPAUX_R20VCCPAUX_U20

XC7Z045FF900BANK VCCPAUX

VCCBRAM_V17VCCBRAM_V19VCCBRAM_W18VCCBRAM_W20

XC7Z045FF900BANK VCCBRAM

MGTAVCC_AA6MGTAVCC_AB8

MGTAVCC_AC10MGTAVCC_AC6MGTAVCC_AD8

MGTAVCC_AE10MGTAVCC_AE6MGTAVCC_AF8

MGTAVCC_AG10MGTAVCC_AH8

MGTAVCC_AJ10MGTAVCC_N6MGTAVCC_P8MGTAVCC_R6MGTAVCC_U6MGTAVCC_W6MGTAVCC_Y8

XC7Z045FF900BANK MGTAVCC

GND

MGTAVTT_AA2MGTAVTT_AB4MGTAVTT_AC2MGTAVTT_AD4MGTAVTT_AE2MGTAVTT_AF4MGTAVTT_AG2MGTAVTT_AG6MGTAVTT_AH4MGTAVTT_AJ2MGTAVTT_AJ6MGTAVTT_AK4MGTAVTT_AK8MGTAVTT_N2MGTAVTT_P4MGTAVTT_R2MGTAVTT_T4MGTAVTT_U2MGTAVTT_V4MGTAVTT_W2MGTAVTT_Y4

XC7Z045FF900BANK MGTAVTT

VCCPLL_N18

XC7Z045FF900BANK VCCPLL

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq Power Pins

Zynq Power Pins

short connection to VCCPLL

Reduce the length of VCCPLL route as much as possible

*See Notes at bottom left of page

Increase width of VCCPLL route as wide as possible

Place C726 inside open space cross adjacent to N18 for

Place C725 inside VIA field for short connection to VCCPLL and GND

BF

2-14-2014_15:01

5811

2.0

04

VCCP1V8

N18

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

AA2AB4AC2AD4AE2AF4AG2AG6AH4AJ2AJ6AK4AK8N2P4R2T4U2V4W2Y4

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

AA6AB8AC10AC6AD8AE10AE6AF8AG10AH8AJ10N6P8R6U6W6Y8

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

V17V19W18W20

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

N20P19R20U20

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

M13M15N12N14P13R12R16T13U12U16V13V15W12W14W16Y17

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

P11T11V11

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

T7V7

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

N16P17R18T17T19U18

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

M11N10R10U10W10Y11

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

VCCP1V8

VCCINT

VCCINT

VCCAUX_IO

1

2

C26710UF4VX5R

1 2

L8

FERRITE-120

3A

VCCPINT

MGTVCCAUX

MGTAVTT MGTAVCC

1

2

C7250.47UF10VX5R

VCCPLL

Page 12: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GNDofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn ByGND

GND_A1GND_A11GND_A21GND_AA1

GND_AA10GND_AA11GND_AA21GND_AA5

GND_AB11GND_AB18GND_AB28GND_AB3GND_AB7GND_AC1

GND_AC11GND_AC15GND_AC25GND_AC5GND_AC9

GND_AD11GND_AD12GND_AD22GND_AD3GND_AD7GND_AE1

GND_AE11GND_AE19GND_AE29GND_AE5GND_AE9

GND_AF11GND_AF16GND_AF26GND_AF3GND_AF7GND_AG1

GND_AG11GND_AG13GND_AG23GND_AG5GND_AG9

GND_AH11GND_AH20GND_AH3

GND_AH30GND_AH7GND_AJ1

GND_AJ11GND_AJ17GND_AJ27GND_AJ5GND_AJ9

GND_AK11GND_AK14GND_AK24GND_AK3GND_AK7GND_B18GND_B28GND_B8GND_C15GND_C25GND_C5GND_D12GND_D2GND_D22GND_E19GND_E29GND_E9GND_F16GND_F26GND_F6GND_G13GND_G23GND_G3GND_H10GND_H20GND_H30GND_J17GND_J27

GND_J7GND_K14GND_K24GND_K4GND_L11GND_L21GND_M1GND_M14GND_M18GND_M2GND_M28GND_M3GND_M4GND_M5GND_M6GND_M7GND_M8GND_M9GND_N1GND_N11GND_N13GND_N15GND_N17GND_N19GND_N25GND_N5GND_N9GND_P12GND_P16GND_P18GND_P20GND_P22GND_P3GND_P7GND_R1GND_R11GND_R13GND_R17GND_R19GND_R29GND_R5GND_T10GND_T12GND_T16GND_T18GND_T20GND_T26GND_T3GND_T8GND_U1GND_U11GND_U13GND_U17GND_U19GND_U23GND_U5GND_V12GND_V14GND_V16GND_V18GND_V20GND_V3GND_V30GND_V8GND_W1GND_W11GND_W13GND_W15GND_W17GND_W19GND_W27GND_W5GND_Y14GND_Y16GND_Y18GND_Y24GND_Y3GND_Y7

XC7Z045FF900BANK GND

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Zynq GND

Zynq GND

BF

2-14-2014_15:01

5812

2.0

04

A1A11A21AA1AA10AA11AA21AA5AB11AB18AB28AB3AB7AC1AC11AC15AC25AC5AC9AD11AD12AD22AD3AD7AE1AE11AE19AE29AE5AE9AF11AF16AF26AF3AF7AG1AG11AG13AG23AG5AG9AH11AH20AH3AH30AH7AJ1AJ11AJ17AJ27AJ5AJ9AK11AK14AK24AK3AK7B18B28B8C15C25C5D12D2D22E19E29E9F16F26F6G13G23G3H10H20H30J17J27

J7K14K24K4L11L21M1M14M18M2M28M3M4M5M6M7M8M9N1N11N13N15N17N19N25N5N9P12P16P18P20P22P3P7R1R11R13R17R19R29R5T10T12T16T18T20T26T3T8U1U11U13U17U19U23U5V12V14V16V18V20V3V30V8W1W11W13W15W17W19W27W5Y14Y16Y18Y24Y3Y7

U1 SOC_IRONWOOD_FF900

SOC_Z7_FF900_IRONWOOD

Page 13: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND GND

GND

GND

GND

GND

VCCAUX

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

BYPASS CAPACITORS

VCCO P1 100uF (1), 4.7uF (2), 0.47uF (3)VCC0 PS 100uF (1), 4.7uF (1), 0.47uF (2)

VCCPAUX 100uF (1), 4.7uF (2), 0.47uF (3)

VCCINT 330uF (4)

VCCBRAM 100uF (2), 47uF (1), 4.7uF (6), 0.47uF (12)

VCCAUX_IO 47uF (1)VCCAUX 47uF (2)

VCCPINT 100uF (1), 4.7uF (3), 0.47uF (5)

VCC1V5_PS 100uF (2), 4.7uF (3), 0.47uF (7)Zynq Bypass Capacitors Page 1

Zynq Bypass Capacitors Page 1

as short as possible connection to VCCPAUX and GNDPlace C501, C503 directly underneath the FPGA

04

2.0

13 58

2-14-2014_15:01

BF

1

2

C59947UF25VX5R

1

2

C59647UF25VX5R

1

2

C59847UF25VX5R

1

2

C59747UF25VX5R

1

2

C6144.7UF25VX5R

2

1

X5R10V0.47UFC6311

2

C5100.47UF10VX5R

2

1

X5R10V0.47UFC6301

2

C6290.47UF10VX5R

2

1

X5R10V0.47UFC628

2

1

X5R25V4.7UFC6151

2X5R6.3100UFC601

2

1 C284100UF6.3X5R

1

2

C624330UF10VTANT

VCCP1V8

VCCINT

VCC1V5_PS

VCCP1V8 VCCP1V8

VCCPINT

1

2

C5260.47UF10VX5R

2

1

X5R10V0.47UFC525

2

1

X5R10V0.47UFC5291

2

C5280.47UF10VX5R

2

1

X5R10V0.47UFC527

2

1

X5R25V4.7UFC3991

2

C3984.7UF25VX5R

2

1 C290100UF6.3X5R

2

1

X5R25V4.7UFC397

1

2

C3844.7UF25VX5R

1

2X5R6.3100UFC281

2

1

X5R25V4.7UFC383 1

2

C5030.47UF10VX5R

1

2

C5020.47UF10VX5R

2

1

X5R10V0.47UFC501

1

2

C5060.47UF10VX5R

2

1

X5R10V0.47UFC505

2

1

X5R10V0.47UFC5041

2

C3864.7UF25VX5R

2

1 C282100UF6.3X5R

2

1

X5R25V4.7UFC3851

2

C3874.7UF25VX5R

1

2X5R6.3100UFC283 1

2

C5080.47UF10VX5R

2

1

X5R10V0.47UFC507

1

2X5R6.3100UFC286

2

1 C285100UF6.3X5R

1

2

C3914.7UF25VX5R

2

1

X5R25V4.7UFC3901

2

C3894.7UF25VX5R

1

2

C5170.47UF10VX5R

2

1

X5R10V0.47UFC5161

2

C5150.47UF10VX5R

2

1

X5R10V0.47UFC5141

2

C5130.47UF10VX5R

2

1

X5R10V0.47UFC5121

2

C5110.47UF10VX5R

VCCINT

2

1

TANT10V330UFC625

1

2

C626330UF10VTANT 2

1

TANT10V330UFC627

1

2

C6174.7UF25VX5R

2

1

X5R25V4.7UFC616

2

1

X5R25V4.7UFC6191

2

C6184.7UF25VX5R

1

2

C6340.47UF10VX5R

2

1

X5R10V0.47UFC633 1

2

C6320.47UF10VX5R

2

1

X5R10V0.47UFC6381

2

C6370.47UF10VX5R

2

1

X5R10V0.47UFC6361

2

C6350.47UF10VX5R

VCCAUX_IO

Page 14: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Bank 34 VCC1V5_PL 100uF (1)

Bank 35 VCC1V5_PL 100uF (1)Bank 13 VADJ_FPGA 100uF (1)

Bank 12 VADJ_FPGA 100uF (1)

Bank 11 VADJ_FPGA 100uF (1)

Bank 10 VADJ_FPGA 100uF (1)

Bank 9 VADJ_FPGA 100uF (1)

Bank 0 VCC3V3 100uF (1)

Bank 33 VCC1V5_PL 100uF (1)

MGTAVCC 4.7uF (1)

MGTAVTT 4.7uF (1)

MGTVCCAUX 4.7uF (1)

Zynq Bypass Capacitors Page 2

Zynq Bypass Capacitors Page 2

BF

2-14-2014_15:01

5814

2.0

04

1

2

C60047UF25VX5R

2

1

X5R25V4.7UFC650

MGTAVTT

MGTAVCC

1

2

C6494.7UF25VX5R

VCC3V3_FPGA

VCC1V5_PL

1

2X5R6.3100UFC602

VADJ_FPGA

2

1 C603100UF6.3X5R

VADJ_FPGA

VADJ_FPGA

1

2X5R6.3100UFC606

VADJ_FPGA

2

1 C605100UF6.3X5R

1

2X5R6.3100UFC604

VADJ_FPGA

2

1 C609100UF6.3X5R

1

2X5R6.3100UFC608

2

1 C607100UF6.3X5R

VCC1V5_PL

VCC1V5_PL

MGTVCCAUX

1

2

C6514.7UF25VX5R

Page 15: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

Y2A2

VCC

Y1A1

GND

GND

GND

VCC3V3

GND GND GNDGND

GND

GND

GND

GND

GNDGNDGND

GND

VCC3V3

GND

GND

Y2A2

VCC

Y1A1

EPAD

EN2

EN1

TH1

TH0

VCC

CRESET

CDLY2

CDLY1

RST_B

OUT2

OUT1IN1

IN2

GND

TOL

MR_B

GND

GND

Y2A2

VCC

Y1A1

GND

VCC3V3

1

2

4

3

5

6

8

7

9

11

13

12

14

15

16

17

18

19

20

10

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

XXX

PS_SRST_B

PS_POR_B

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

POR_B AND SRST_BPUSHBUTTON SWITCHES

Power Supervisor, Zynq Config Pins, Reset

Power Supervisor, Zynq Config Pins, Reset

ZC706 EVALUATION PLATFORM

MIO[8:2] SELECTION HEADERS

20.5K resistors must be placed near middle of QSPI traces

C8 = DNP, SRST delay = 35us

C6 = 3300pF, POR delay = 13.2ms

BF

2-14-2014_15:01

5815

2.0

04

1

2

C65600PF50VX7R

1

2

C8DNPDNP

21

R144

20.5K1/10W

MIO2_SELECT_J15 MIO2_SELECT

21

J70

1

2

J7

VCC3V3_PSVCC3V3_PS

15 MIO6_SELECT

MIO5_SELECT15

MIO4_SELECT15

15 MIO3_SELECT

15 MIO2_SELECT

QSPI0_CLK 9,21

VCCP1V8

VCCP1V8

VCCP1V8

VCCP1V8VCCP1V8

VCCP1V8

VCCP1V8

DIGILENT_GPIO216

1718

20

161514131211

4321

56789

10

19

SW11

SPDT_SW_DIP_5

NC

NC

NC

1 6

5

3 4

2 NC7WZ07

SC70_6

U35

VADJ

1

2 1%1/10W10.0KR259

VADJ

39 PL_PJTAG_PS_SRST_B

20PIN_JTAG_PS_SRST_B16

14PIN_JTAG_INIT16

PS_SRST_B 9,15

17

7

6

8

9

1

14

15

16

12

10

112

3

5

4

13

U8 TQFN_16

MAX16025

2

43

5

61

U34

SC70_6

NC7WZ07

PS_SRST_B 9,15

1

2 1%1/10W10.0KR257

2

1 R25810.0K1/10W1%

2

1 R26510.0K1/10W1%

USB_RESET_B_AND 9,31

QSPI0_IO3 9,21

QSPI0_IO2 9,21

9,21QSPI0_IO1

9,21QSPI0_IO0

2

1 R1768.06K1/10W1%

1 2

1/10W20.5K

R147

1 2

1/10W20.5K

R143

21

R142

20.5K1/10W

1

2 1%1/10W10.0KR256

PS_POR_B_SW 15

9,29,31PS_POR_BPS_SRST_B_SW 15

2

1 R26410.0K1/10W1%

2

1 R26610.0K1/10W1%

1

2

3

J43

HDR_1X3

1

2

3

J44

HDR_1X3

1

2

C70.1UF25VX5R

2

1 R26310.0K1/10W1%

21

DS1LED-RED-SMT2

1 R26210.0K1/10W1%2

1 R26110.0K1/10W1%

21

R149249

1/10W1%

21

SW3

EVQ-11L07K

21

SW2

EVQ-11L07K

PS_SRST_B_SW 15

PS_POR_B_SW 15

NC

1 2

1/10W20.5K

R146

21

R145

20.5K1/10W

21

R148

20.5K1/10W

1

2 1%1/10W8.06KR177

9PS_MIO8

2

1

X5R25V0.1UFC3

PS_SRST_B 9,15

1

2

C40.1UF25VX5R

1

2

C50.1UF25VX5R

1

2 1%1/10W10.0KR260

1 6

5

3 4

2 NC7WZ07

SC70_6

U36

9,15PS_SRST_B

21

J71

MIO3_SELECT15 MIO3_SELECT_J

21

J72

15 MIO4_SELECT MIO4_SELECT_J

21

J73

MIO5_SELECT15 MIO5_SELECT_J

21

J74

15 MIO6_SELECT MIO6_SELECT_J

Page 16: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

GND

GND

VCC3V3

VCC3V3

GND

VCC3V3

GND

VCC3V3

GND

GNDGND

GNDGND

OE1_N

A4A3A2A1

A5A6A7A8GND

VCCOE2_N

Y1Y2Y3Y4Y5Y6Y7Y8

GND

GND

VSENSE

VREF

VPRG

TCK

TMS

TDI

INIT

TDO

PGND

GND

GND

GND

GND

GND

A1

A2

B1

B2

DIR1

DIR2GND

OE_B

VCCA VCCB

VCC3V3

GND

GND

GND

VCC3V3

VCC3V3

VCC3V3

NO2IN2

NO0 V_P

IN1COM

GND

NO1

Control

Logic

VCC3V3

NO2IN2

NO0 V_P

IN1COM

GND

NO1

Control

Logic

NO2IN2

NO0 V_P

IN1COM

GND

NO1

Control

Logic

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GPIO2_SRST

GPIO0

GND1

GND2

TCK

TDI

VREF

TDO

TMS 3V3

GPIO1

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

JTAG Buffer, USB JTAG Module, JTAG Hdr

JTAG Buffer, USB JTAG Module, JTAG Hdr

ZC706 EVALUATION PLATFORM

04

2.0

BF16 58

2-14-2014_15:01

11

9

1

7

2

3

6

5

4 8

10

U30 DIGILENT_USB_JTAG2

DIGILENT_USB_JTAG2

21R324

0 1/10W

5%

1 25%

1/10W

0R325

NC

35

1 8

67

4

2

U47 TS5A3359

TS5A3359DCUR

35

1 8

67

4

2

U45 TS5A3359

TS5A3359DCUR

DIGILENT_TDO 16

DIGILENT_TMS16

DIGILENT_TDI16

DIGILENT_TCK16

JTAG_SEL_2 16

JTAG_SEL_1 16

JTAG_TCK 16

JTAG_SEL_2 16

JTAG_SEL_1 16

JTAG_TMS 16

16JTAG_SEL_1 16JTAG_TDI

16JTAG_SEL_2

2

4

76

81

53

TS5A3359DCUR

TS5A3359U46

14PIN_JTAG_INIT_R 1514PIN_JTAG_INIT

14PIN_JTAG_TDO 16

14PIN_JTAG_TDO 16

FMC_LPC_TCK_BUF 28

20PIN_JTAG_TCK16

DIGILENT_TCK1616 14PIN_JTAG_TCK

14PIN_JTAG_TDI16

20PIN_JTAG_TMS16

DIGILENT_TMS1616 14PIN_JTAG_TMS

20PIN_JTAG_TDI16

1614PIN_JTAG_TCK

1614PIN_JTAG_TMS

14PIN_JTAG_TDI16

15 20PIN_JTAG_PS_SRST_B

16 20PIN_JTAG_TDO

16 20PIN_JTAG_TMS

1

2 5%1/10W4.7KR22

NC

2

1 R144.7K1/10W5%

21

34

SW4

SDA02H1SBD

DED_DGBACK_UNUSED

DED_DBGRQ_UNUSED

7

2

6

4

8

1

3

5

9

11

13

15

17

19

10

12

14

16

18

20

J62

TST-110-01-G-D

1620PIN_JTAG_TDO 16DIGILENT_TDO3 JTAG_TDO

16 JTAG_TCK

16 JTAG_SEL_116 JTAG_SEL_2

2

1

X5R25V0.1UFC9

DIGILENT_TDI16

16 20PIN_JTAG_TDI

20PIN_JTAG_TCK16

1

2

C120.1UF25VX5R

DED_RTCK_UNUSED

DED_NTRST_UNUSED

24FMC_HPC_TMS_BUF

8

9

5

4

10

13

2

7 6

U10 QFN_RSW_10

SN74AVC2T245

16 JTAG_TMS

1

2

12

6

4

10

14

8

13

3

5

7

9

11

J3

87832-1420

11

23456789

1918171615141312

10

120

U23 TSSOP_20

SN74LV541APWR

JTAG_TDI16 24FMC_TDI_BUF

FMC_LPC_TMS_BUF 28

1

2

C140.1UF25VX5R

2

1

X5R25V0.1UFC13

16 JTAG_TMS

16 JTAG_TCK FPGA_TCK_BUF 3

FPGA_TMS_BUF 3

1

2

J81

2 5%1/10W4.7KR19

2

1 R184.7K1/10W5% 2

1 R174.7K1/10W5%

1

2 5%1/10W4.7KR161

2 5%1/10W4.7KR15

1

2 5%1/10W4.7KR13

2

1 R124.7K1/10W5%

1

2

C100.1UF25VX5R

2

1

X5R25V0.1UFC11

1

2 5%1/10W4.7KR21

2

1 R204.7K1/10W5%

FMC_HPC_TCK_BUF 24

2

1 R234.7K1/10W5%

1

2 5%1/10W4.7KR24

2

1 R254.7K1/10W5%

DIGILENT_GPIO215

NC

Page 17: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GNDGND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

GND

NC6NC5

A0A1

A10/APA11A12/BC_BA13A14

A2A3A4A5A6A7A8A9

BA0BA1BA2

CAS_B

CK

CKECK_B

CS_B

DM_TDQS

DQ0DQ1DQ2DQ3DQ4DQ5DQ6

DQSDQS_B

NC1NC2NC3NC4

NF_TDQS_B

ODT

RAS_B

RESET_B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

WE_B

ZQ

DQ7

PCB P/N: 1280681SCH P/N: 0381513ZC706 EVALUATION PLATFORM

SCHEM, ROHS COMPLIANTDDR3 PS Device 0

DDR3 PS Device 0

04

2.0

17 58

2-14-2014_15:01

BF

VTTDDR_PS

2

1

R536

40.2

1%

1

2

1%

40.2

R218

K3L7

H7M7K7N3N7

L3K2L8L2M8M2N8M3

J2K8J3

G3

F7

G9G7

H2

B7

B3C7C2C8E3E8D2E7

C3D3

A3F1F9H1H9J7

A7

G1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

L9

N1

N9

A8

B1

D8

F2

F8

J1

J9

L1

B2

B8

C9

D1

D9

H3

H8U2

FBGA_DDR3_78P

MT41J256M8HX_15E

PS_DDR3_CS_B10,18,19,20

10,18,19,20PS_DDR3_ODT

10,18,19,20 PS_DDR3_CAS_B10,18,19,20 PS_DDR3_RAS_B10,18,19,20 PS_DDR3_WE_B

PS_DDR3_BA210,18,19,20

PS_DDR3_BA110,18,19,20

PS_DDR3_BA010,18,19,20

10,18,19,20 PS_DDR3_A14PS_DDR3_A1310,18,19,20

10,18,19,20 PS_DDR3_A1210,18,19,20 PS_DDR3_A1110,18,19,20 PS_DDR3_A1010,18,19,20 PS_DDR3_A910,18,19,20 PS_DDR3_A810,18,19,20 PS_DDR3_A710,18,19,20 PS_DDR3_A610,18,19,20 PS_DDR3_A510,18,19,20 PS_DDR3_A410,18,19,20 PS_DDR3_A310,18,19,20 PS_DDR3_A210,18,19,20 PS_DDR3_A110,18,19,20 PS_DDR3_A0

1

2

1%

40.2

R231

2

1

R230

40.2

1%

VTTDDR_PS

2

1

R219

40.2

1%

PS_DDR3_RESET_B10,18,19,20

NC 10PS_DDR3_DM0

10PS_DDR3_DQ4

10PS_DDR3_DQ2

NC

NCNC

NC

NCNC

10PS_DDR3_DQ5

10PS_DDR3_DQ6

PS_DDR3_DQS0_P 1010PS_DDR3_DQS0_N

10PS_DDR3_DQ7

10PS_DDR3_DQ3

10PS_DDR3_DQ1 10PS_DDR3_DQ0

2

1 R3172401/10W1%

1

2X5R25V0.1UFC19 1

2X5R25V0.1UFC20 1

2X5R25V0.1UFC21 1

2X5R25V0.1UFC22 1

2X5R25V0.1UFC231

2

C4124.7UF25VX5R

1

2

C4134.7UF25VX5R

1

2

C4144.7UF25VX5R

1

2

C4530.068UF10VX5R

1

2

C4154.7UF25VX5R

1

2

C5500.47UF10VX5R

1

2

C5510.47UF10VX5R

1

2

C4540.068UF10VX5R

1

2

C4550.068UF10VX5R

1

2

C4164.7UF25VX5R

1

2

C5520.47UF10VX5R

1

2

C5530.47UF10VX5R

1

2

C4560.068UF10VX5R

2

1 R274.7K1/10W5%

2

1

R228

40.2

1%

1

2

1%

40.2

R227

2

1

R226

40.2

1%

1

2

1%

40.2

R225

1

2

1%

40.2

R224

2

1

R223

40.2

1%

1

2

1%

40.2

R222

2

1

R221

40.2

1%

1

2

1%

40.2

R220

2

1

R217

40.2

1%

2

1

R216

40.2

1%

1

2

1%

40.2

R215

2

1

R214

40.2

1%

1

2

1%

40.2

R213

1

2

1%

40.2

R212

2

1

R211

40.2

1%

2

1R210

40.2

1%

1

2

1%

40.2

R209

2 1R108

80.6

1/10W

1%

PS_DDR3_CLK_N10,18,19,2010,18,19,20 PS_DDR3_CLK_P

1

2

1%

40.2

R229

VCC1V5_PS VCC1V5_PS

VCC1V5_PS

VTTVREF_PS

1

2

C3310.01UF25VX7R

VTTDDR_PS

PS_DDR3_CKE10,18,19,20

Page 18: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

NC6NC5

A0A1

A10/APA11A12/BC_BA13A14

A2A3A4A5A6A7A8A9

BA0BA1BA2

CAS_B

CK

CKECK_B

CS_B

DM_TDQS

DQ0DQ1DQ2DQ3DQ4DQ5DQ6

DQSDQS_B

NC1NC2NC3NC4

NF_TDQS_B

ODT

RAS_B

RESET_B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

WE_B

ZQ

DQ7

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

DDR3 PS Device 1

DDR3 PS Device 1

BF

2-14-2014_15:01

5818

2.0

04

10PS_DDR3_DQ10

10PS_DDR3_DQ14 10PS_DDR3_DQ11

10PS_DDR3_DQ9

10PS_DDR3_DQ8K3L7

H7M7K7N3N7

L3K2L8L2M8M2N8M3

J2K8J3

G3

F7

G9G7

H2

B7

B3C7C2C8E3E8D2E7

C3D3

A3F1F9H1H9J7

A7

G1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

L9

N1

N9

A8

B1

D8

F2

F8

J1

J9

L1

B2

B8

C9

D1

D9

H3

H8U3

FBGA_DDR3_78P

MT41J256M8HX_15E

VTTDDR_PS

1

2

C4600.068UF10VX5R

1

2

C5570.47UF10VX5R

1

2

C5560.47UF10VX5R

1

2

C4214.7UF25VX5R

1

2

C4590.068UF10VX5R

1

2

C4580.068UF10VX5R

1

2

C5550.47UF10VX5R

1

2

C5540.47UF10VX5R

1

2

C4204.7UF25VX5R

1

2

C4570.068UF10VX5R

1

2

C4194.7UF25VX5R

1

2

C4184.7UF25VX5R

1

2

C4174.7UF25VX5R

1

2X5R25V0.1UFC281

2X5R25V0.1UFC271

2X5R25V0.1UFC261

2X5R25V0.1UFC251

2X5R25V0.1UFC24

2

1 R3182401/10W1%

PS_DDR3_ZQA

10,17,19,20 PS_DDR3_WE_B

PS_DDR3_RESET_B10,17,19,20

10,17,19,20 PS_DDR3_RAS_B

PS_DDR3_ODT10,17,19,20

NC

NCNCNCNC

10PS_DDR3_DQS1_NPS_DDR3_DQS1_P 10

10PS_DDR3_DQ15

10PS_DDR3_DQ13 10PS_DDR3_DQ12

10PS_DDR3_DM1

10,17,19,20PS_DDR3_CS_B

PS_DDR3_CLK_N10,17,19,20 PS_DDR3_CKE10,17,19,20

10,17,19,20 PS_DDR3_CLK_P

PS_DDR3_CAS_B10,17,19,20

10,17,19,20 PS_DDR3_BA210,17,19,20 PS_DDR3_BA110,17,19,20 PS_DDR3_BA0

10,17,19,20 PS_DDR3_A910,17,19,20 PS_DDR3_A810,17,19,20 PS_DDR3_A710,17,19,20 PS_DDR3_A610,17,19,20 PS_DDR3_A510,17,19,20 PS_DDR3_A410,17,19,20 PS_DDR3_A3

PS_DDR3_A210,17,19,20

10,17,19,20 PS_DDR3_A1410,17,19,20 PS_DDR3_A1310,17,19,20 PS_DDR3_A1210,17,19,20 PS_DDR3_A1110,17,19,20 PS_DDR3_A10

PS_DDR3_A110,17,19,20

PS_DDR3_A010,17,19,20

NCNC

VCC1V5_PS

VCC1V5_PS VCC1V5_PS

VTTVREF_PS

1

2

C3320.01UF25VX7R

Page 19: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

NC6NC5

A0A1

A10/APA11A12/BC_BA13A14

A2A3A4A5A6A7A8A9

BA0BA1BA2

CAS_B

CK

CKECK_B

CS_B

DM_TDQS

DQ0DQ1DQ2DQ3DQ4DQ5DQ6

DQSDQS_B

NC1NC2NC3NC4

NF_TDQS_B

ODT

RAS_B

RESET_B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

WE_B

ZQ

DQ7

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

DDR3 PS Device 2

DDR3 PS Device 2

04

2.0

19 58

2-14-2014_15:01

BF

K3L7

H7M7K7N3N7

L3K2L8L2M8M2N8M3

J2K8J3

G3

F7

G9G7

H2

B7

B3C7C2C8E3E8D2E7

C3D3

A3F1F9H1H9J7

A7

G1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

L9

N1

N9

A8

B1

D8

F2

F8

J1

J9

L1

B2

B8

C9

D1

D9

H3

H8U4

FBGA_DDR3_78P

MT41J256M8HX_15E

VTTDDR_PS

10,17,18,20 PS_DDR3_A13

1

2

C4640.068UF10VX5R

1

2

C5610.47UF10VX5R

1

2

C5600.47UF10VX5R

1

2

C4264.7UF25VX5R

1

2

C4630.068UF10VX5R

1

2

C4620.068UF10VX5R

1

2

C5590.47UF10VX5R

1

2

C5580.47UF10VX5R

1

2

C4254.7UF25VX5R

1

2

C4610.068UF10VX5R

1

2

C4244.7UF25VX5R

1

2

C4234.7UF25VX5R

1

2

C4224.7UF25VX5R

1

2X5R25V0.1UFC331

2X5R25V0.1UFC321

2X5R25V0.1UFC311

2X5R25V0.1UFC301

2X5R25V0.1UFC29

2

1 R3192401/10W1%

NC

NCNCNCNC

10PS_DDR3_DQS2_NPS_DDR3_DQS2_P 10

10PS_DDR3_DQ23 10PS_DDR3_DQ22 10PS_DDR3_DQ21 10PS_DDR3_DQ20 10PS_DDR3_DQ19 10PS_DDR3_DQ18 10PS_DDR3_DQ17 10PS_DDR3_DQ16

10PS_DDR3_DM2

10,17,18,20 PS_DDR3_A910,17,18,20 PS_DDR3_A810,17,18,20 PS_DDR3_A710,17,18,20 PS_DDR3_A610,17,18,20 PS_DDR3_A510,17,18,20 PS_DDR3_A410,17,18,20 PS_DDR3_A3

PS_DDR3_A210,17,18,20

10,17,18,20 PS_DDR3_A1210,17,18,20 PS_DDR3_A1110,17,18,20 PS_DDR3_A10

PS_DDR3_A110,17,18,20

PS_DDR3_A010,17,18,20

NCNC

10,17,18,20PS_DDR3_ODT

10,17,18,20 PS_DDR3_CLK_P

PS_DDR3_RESET_B10,17,18,20

10,17,18,20 PS_DDR3_WE_B

10,17,18,20 PS_DDR3_BA0

PS_DDR3_CS_B10,17,18,20

10,17,18,20 PS_DDR3_RAS_BPS_DDR3_CAS_B10,17,18,20

PS_DDR3_CKE10,17,18,20

PS_DDR3_CLK_N10,17,18,20

10,17,18,20 PS_DDR3_BA210,17,18,20 PS_DDR3_BA1

10,17,18,20 PS_DDR3_A14

VCC1V5_PS VCC1V5_PS

VCC1V5_PS

VTTVREF_PS

1

2

C3330.01UF25VX7R

Page 20: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

NC6NC5

A0A1

A10/APA11A12/BC_BA13A14

A2A3A4A5A6A7A8A9

BA0BA1BA2

CAS_B

CK

CKECK_B

CS_B

DM_TDQS

DQ0DQ1DQ2DQ3DQ4DQ5DQ6

DQSDQS_B

NC1NC2NC3NC4

NF_TDQS_B

ODT

RAS_B

RESET_B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

WE_B

ZQ

DQ7

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

DDR3 PS Device 3

DDR3 PS Device 3

04

2.0

20 58

2-14-2014_15:01

BF

K3L7

H7M7K7N3N7

L3K2L8L2M8M2N8M3

J2K8J3

G3

F7

G9G7

H2

B7

B3C7C2C8E3E8D2E7

C3D3

A3F1F9H1H9J7

A7

G1

F3

N2

A2

A9

D7

G2

G8

K1

K9

M1

M9

B9

C1

E2

E9

J8

E1

A1

L9

N1

N9

A8

B1

D8

F2

F8

J1

J9

L1

B2

B8

C9

D1

D9

H3

H8U5

FBGA_DDR3_78P

MT41J256M8HX_15E

VTTDDR_PS

VCC1V5_PS

1

2

C4680.068UF10VX5R

1

2

C5650.47UF10VX5R

1

2

C5640.47UF10VX5R

1

2

C4314.7UF25VX5R

1

2

C4670.068UF10VX5R

1

2

C4660.068UF10VX5R

1

2

C5630.47UF10VX5R

1

2

C5620.47UF10VX5R

1

2

C4304.7UF25VX5R

1

2

C4650.068UF10VX5R

1

2

C4294.7UF25VX5R

1

2

C4284.7UF25VX5R

1

2

C4274.7UF25VX5R

1

2X5R25V0.1UFC381

2X5R25V0.1UFC371

2X5R25V0.1UFC361

2X5R25V0.1UFC351

2X5R25V0.1UFC34

2

1 R3202401/10W1%

PS_DDR3_WE_B10,17,18,19

10,17,18,19PS_DDR3_RESET_B

PS_DDR3_RAS_B10,17,18,19

PS_DDR3_ODT10,17,18,19

NC

NCNCNCNC

10PS_DDR3_DQS3_NPS_DDR3_DQS3_P 10

10PS_DDR3_DQ31 10PS_DDR3_DQ30 10PS_DDR3_DQ29 10PS_DDR3_DQ28 10PS_DDR3_DQ27 10PS_DDR3_DQ26 10PS_DDR3_DQ25 10PS_DDR3_DQ24

10PS_DDR3_DM3

10,17,18,19PS_DDR3_CS_B

10,17,18,19 PS_DDR3_CLK_N

10,17,18,19 PS_DDR3_CKE

PS_DDR3_CLK_P10,17,18,19

10,17,18,19 PS_DDR3_CAS_B

PS_DDR3_BA210,17,18,19

PS_DDR3_BA110,17,18,19

PS_DDR3_BA010,17,18,19

PS_DDR3_A910,17,18,19

PS_DDR3_A810,17,18,19

PS_DDR3_A710,17,18,19

PS_DDR3_A610,17,18,19

PS_DDR3_A510,17,18,19

PS_DDR3_A410,17,18,19

PS_DDR3_A310,17,18,1910,17,18,19 PS_DDR3_A2

PS_DDR3_A1410,17,18,19

PS_DDR3_A1310,17,18,19

PS_DDR3_A1210,17,18,19

PS_DDR3_A1110,17,18,19

PS_DDR3_A1010,17,18,19

10,17,18,19 PS_DDR3_A110,17,18,19 PS_DDR3_A0

NCNC

VCC1V5_PSVCC1V5_PS

VTTVREF_PS

1

2

C3340.01UF25VX7R

Page 21: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

SCKSI_IO0

SO_IO1 WP_B_IO2

HOLD_B_IO3

RESET_BDNU0DNU1RFU DNU2

DNU3NC

VIO

CS_B

VCC

VSS

SCKSI_IO0

SO_IO1 WP_B_IO2

HOLD_B_IO3

RESET_BDNU0DNU1RFU DNU2

DNU3NC

VIO

CS_B

VCC

VSS

GND

GND

GND

ZC706 EVALUATION PLATFORMPCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

Dual Quad SPIs

Dual Quad SPIs

Dual Quad SPIs

04

2.0

21 58

2-14-2014_15:01

BF

2

1

X5R25V0.1UFC720

1

2

C7190.1UF25VX5R

2

1

X5R25V0.1UFC40

1

2 5%1/10W0R529

2

1 R53001/10W5%

1

2 DNPDNPDNPR531

2

1 R52801/10W5%

1

2 5%1/10W0R527

2

1 R532DNPDNPDNP

10

2

7

141312116

543

1

98

1516

S25FL128SAGMFIR01

SO16_50P300X413U58

1615

8 9

1

3456 11

121314

7

2

10

U59 SO16_50P300X413

S25FL128SAGMFIR01

VCCP1V8

VCCP1V8

1

2

C390.1UF25VX5R

9 QSPI1_IO3

NC NCNC

NCNC

9 QSPI0_CS_B

9QSPI1_IO2QSPI1_IO19

9QSPI1_IO0QSPI1_CLK 9

QSPI0_IO19,15

2

1 R2073301/10W5%

9,15QSPI0_IO2

QSPI0_IO0 9,159,15QSPI0_CLK9,15QSPI0_IO3

NC

NC

NCNC

NC

1

2 5%1/10W330R208

QSPI1_CS_B9

NCNCNC

NC

VCC3V3_PS

VCC3V3_PS

2

1

X5R25V0.1UFC714

1

2

C7150.1UF25VX5R

VCCP1V8

VCCP1V8

Page 22: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

IOGND2

GNDTAB1GNDTAB2GNDTAB3

CMDVSS1

CLKVSS2DAT0DAT1DAT2

CD_DAT3

DETECT

VDD

PROTECTDETECT_PROTECT

GNDTAB4IOGND1

VCCIO_VCC1IO_VCC2IO_VCC3IO_VCC4IO_VCC5CLK_VCC

IO_VL3IO_VL4IO_VL5

IO_VL1IO_VL2

CLK_VLCLK_RET EP

GND

VL

GND

ZC706 EVALUATION PLATFORMPCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

SD Card Connector

SD Card Connector

BF

2-14-2014_15:01

5822

2.0

04

2

1 R31DNPDNPDNP

VCCP1V8

2

1 R543DNPDNPDNP

1

2 DNPDNPDNPR542

1615567814

4910

13

1211 17

13

2

U11 TQFN_16

MAX13035E

2

1

1UF

C718

X5R25V

SDIO_CLK 2222SDIO_CMD 22SDIO_CD_DAT3 22SDIO_DAT2 22SDIO_DAT1 22SDIO_DAT0

SDIO_SDDET9SDIO_SDWP9

VCCP1V8 VCC3V3_PS

1

2 5%1/10W4.7KR29

2

1 R284.7K1/10W5%

18

131415

23

56789

1

10

4

1112

1617

J30

67840-8001

22 SDIO_CLK

1

2

C410.1UF25VX5R

SDIO_DAT222

SDIO_DAT02222 SDIO_DAT1

SDIO_CD_DAT32222 SDIO_CMD

9 SDIO_DAT0_LS9 SDIO_DAT1_LS9 SDIO_DAT2_LS9 SDIO_CD_DAT3_LS9 SDIO_CMD_LS

NC

1

2

C7160.1UF25VX5R

VCC3V3_PS

2

1

X5R25V0.1UFC717

VCCP1V8

9 SDIO_CLK_LS

Page 23: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

XXXXXXXXX

GND

GND

GND

GND

VCC3V3

GND

GND

GND

XXX

GND

TAB2

TAB1

SHLD1

SHLD18

SHLD16

SHLD17

SHLD14

SHLD15

SHLD12

SHLD13

SHLD10

SHLD11

SHLD8

SHLD9

SHLD6

SHLD7

SHLD4

SHLD5

SHLD3

VSS24

VSS52

VSS51

VSS50

VSS49

VSS48

VSS47

VSS46

VSS45

VSS44

VSS43

VSS42

VSS41

VSS40

VSS39

VSS38

VSS37

VSS36

VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

A0

A1

A10/AP

A11

A12_BC_N

A13

A14

A15

A2

A3

A4

A5

A6

A7

A8

A9

BA0

BA1

BA2

CAS_B

CK0_N

CK0_P

CK1_N

CK1_P

CKE0

CKE1

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DQ0

DQ1

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ2

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ3

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ5

DQ50

DQ51

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ6

DQ60

DQ61

DQ62

DQ63

DQ7

DQ8

DQ9

DQS0_N

DQS0_P

DQS1_N

DQS1_P

DQS2_N

DQS2_P

DQS3_N

DQS3_P

DQS4_N

DQS4_P

DQS5_N

DQS5_P

DQS6_N

DQS6_P

DQS7_N

DQS7_P

EVENT_B

NC1

NC2

ODT0

ODT1

RAS_B

RESET_B

S0_B

S1_B

SA0

SA1

SCL

SDA

TEST

VDD1

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VDDSPD

VREFCA

VREFDQ

VSS1

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS2

VSS20

VSS21

VSS22

VSS23

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VTT1

VTT2

WE_B

DQ49

DQ52

VSS25

SHLD2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

Silkscreen:

Place Near

"DDR3 SO-DIMM"

pin 1 of DIMM

Shielded DDR3 SO-DIMM

Shielded DDR3 SO-DIMM

2.0

04

23 58

2-14-2014_15:01

BF

36,37PORT_EXPANDER_DDR3_SDA

VCC1V5_PL

225

224

205

222

220

221

218

219

216

217

214

215

212

213

210

211

208

209

207

66

196

195

190

189

185

184

179

178

173

172

168

167

162

161

156

155

151

150

145

144

139

138

134

133

128

12772

98

97

107

84

83

119

80

78

96

95

92

91

90

86

89

85

109

108

79

115

103

101

104

102

73

74

11

28

46

63

136

153

170

187

5 7

33

35

2224

34

36

39

41

51

53

15

40

42

50

52

57

59

67

69

56

58

17

68

70

129

131

141

143

130

132

140

142

4

147

149

157

159

146

148

158

160

163

6

175

177

166

174

176

181

183

191

193

16

180

182

192

194

18

2123

1012

2729

4547

6264

135

137

152

154

169

171

186

188

198

77

122

116

120

110

30

114

121

197

201

202

200

125

75

100

105

106

111

112

117

118

123

124

76

81

82

87

88

93

94

99

199

126

1

2

263132373843444849543

556061658 91314192025

203

204

113

165

164

71

206

J1

DDR3_SO-DIMM_SHIELDED

DIMMCAGE1

SODIMM_CAGE

VTTVREF_SODIMM

VTTVREF_SODIMM

VTTDDR_SODIMM

VTTDDR_SODIMM

VTTDDR_SODIMM

VCC1V5_PL

VCC1V5_PLVCC1V5_PL

VCC1V5_PL

36,37PORT_EXPANDER_DDR3_SCL

2

1

DNPDNPC438

2

1

X5R10V0.1UFC1501

2

C1490.1UF10VX5R

1

2

C45110UF6.3VX5R

1

2

C1510.1UF10VX5R

1 2 3 4

5678CP9

0.1UF

10V

X5R

8 7 6 5

4321

X5R

10V

0.1UF

CP8

1 2 3 4

5678

CP7

0.1UF

10V

X5R

1

25%1/10W4.7KR93

2

1 R904.7K1/10W5%

8 7 6 5

4321

X5R

10V

0.1UF

CP6

1 2 3 4

5678

CP1

0.1UF

10V

X5R

VCC1V5_PL

PL_DDR3_CKE0

6

2

1 R914.7K1/10W5%

1

2

C1530.1UF10VX5R

1

2

C3510.01UF25VX7R

8 7 6 5

4321

X5R

10V

0.1UF

CP4

1

2

C1460.1UF10VX5R

1

2

C482330UF10VTANT

1

2

C45010UF6.3VX5R

1

2

C1480.1UF10VX5R

2

1

X5R10V0.1UFC147

PL_DDR3_TEMP_EVENT6

PL_DDR3_RESET_B

7

PL_DDR3_D6

6

PL_DDR3_DQS0_P

6PL_DDR3_DQS0_N

6PL_DDR3_DM0

6

PL_DDR3_D0

6PL_DDR3_D4

6

PL_DDR3_ODT0

6

PL_DDR3_D62

7PL_DDR3_D63

7

PL_DDR3_DM3

6

PL_DDR3_DM1

6PL_DDR3_DQS1_N

6PL_DDR3_DQS1_P

6

PL_DDR3_D11

6

PL_DDR3_DQS2_N

6PL_DDR3_DQS2_P

6PL_DDR3_DM2

6

PL_DDR3_DQS3_N

6PL_DDR3_DQS3_P

6PL_DDR3_DQS7_N

7PL_DDR3_DQS7_P

7

PL_DDR3_DQS6_P

7PL_DDR3_DM6

7

PL_DDR3_DM7

7

PL_DDR3_DQS6_N

7

PL_DDR3_DQS5_P

7PL_DDR3_DQS5_N

7PL_DDR3_DM5

7

PL_DDR3_DQS4_P

6PL_DDR3_DQS4_N

6PL_DDR3_DM4

6

PL_DDR3_BA2

6PL_DDR3_BA1

6PL_DDR3_BA0

6PL_DDR3_RAS_B

6PL_DDR3_WE_B

6PL_DDR3_CAS_B

6

PL_DDR3_ODT1

6

PL_DDR3_S1_B

6

PL_DDR3_CLK1_N

6PL_DDR3_CLK1_P

6

PL_DDR3_CLK0_N

6PL_DDR3_CLK0_P

6

PL_DDR3_A10

6

PL_DDR3_A5

6

PL_DDR3_A3

6

PL_DDR3_A11

6

PL_DDR3_A7

6PL_DDR3_A8

6

PL_DDR3_A15

6PL_DDR3_A14

6PL_DDR3_A13

6PL_DDR3_A12

6

PL_DDR3_A9

6

PL_DDR3_A6

6

PL_DDR3_A4

6

PL_DDR3_A2

6PL_DDR3_A1

6PL_DDR3_A0

6

NC

PL_DDR3_S0_B

6

PL_DDR3_D32

6PL_DDR3_D36

6PL_DDR3_D33

6PL_DDR3_D37

6

PL_DDR3_D38

6PL_DDR3_D34

6PL_DDR3_D39

6PL_DDR3_D35

6

PL_DDR3_D44

7PL_DDR3_D40

7PL_DDR3_D45

7PL_DDR3_D41

7

PL_DDR3_D42

7PL_DDR3_D46

7PL_DDR3_D43

7PL_DDR3_D47

7

PL_DDR3_D48

7PL_DDR3_D52

7PL_DDR3_D49

7PL_DDR3_D53

7

PL_DDR3_D50

7PL_DDR3_D54

7PL_DDR3_D51

7PL_DDR3_D55

7

PL_DDR3_D56

7PL_DDR3_D60

7PL_DDR3_D57

7PL_DDR3_D61

7

PL_DDR3_D58

7PL_DDR3_D59

7

PL_DDR3_D10

6

PL_DDR3_D31

6PL_DDR3_D27

6PL_DDR3_D30

6PL_DDR3_D26

6

PL_DDR3_D29

6PL_DDR3_D25

6PL_DDR3_D28

6PL_DDR3_D24

6

PL_DDR3_D23

6PL_DDR3_D19

6PL_DDR3_D22

6PL_DDR3_D18

6

PL_DDR3_D21

6PL_DDR3_D17

6PL_DDR3_D20

6PL_DDR3_D16

6

PL_DDR3_D15

6

PL_DDR3_D14

6

PL_DDR3_D9

6PL_DDR3_D8

6PL_DDR3_D13

6PL_DDR3_D12

6

PL_DDR3_D3

6PL_DDR3_D2

6PL_DDR3_D7

6

PL_DDR3_D1

6PL_DDR3_D5

6

2

1

X5R10V0.1UFC154

2

1

X5R10V0.1UFC152

2

1

X5R6.3V10UFC452

8 7 6 5

4321

X5R

10V

0.1UF

CP2

1 2 3 4

5678

CP3

0.1UF

10V

X5R

1 2 3 4

5678

CP5

0.1UF

10V

X5R

2

1R924.7K1/10W5%

PL_DDR3_CKE1

6

NCNC

1

2

C435DNPDNP 2

1

DNPDNPC4361

2

C437DNPDNP

Page 24: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

VCC3V3

DP5_C2M_N

DP5_C2M_P

DP4_C2M_N

DP4_C2M_P

DP3_C2M_N

DP3_C2M_P

DP2_C2M_N

DP2_C2M_P

DP1_C2M_N

DP1_C2M_P

DP5_M2C_N

DP5_M2C_P

DP4_M2C_N

DP4_M2C_P

DP3_M2C_N

DP3_M2C_P

DP2_M2C_N

DP2_M2C_P

DP1_M2C_N

DP1_M2C_P

3P3V_1

12P0V_2

12P0V_1

GA0

SDA

SCL

LA27_N

LA27_P

LA18_N_CC

LA18_P_CC

LA14_N

LA14_P

LA10_N

LA10_P

LA06_N

LA06_P

DP0_M2C_N

DP0_M2C_P

DP0_C2M_N

DP0_C2M_P

GND

VCC3V3

VCC12_P

GND

GND

VCC12_P

VCC3V3

VCC3V3

3P3V_4

GA1

TRST_L

TMS

3P3VAUX

TDO

TDI

TCK

LA26_N

LA26_P

LA23_N

LA17_N_CC

LA17_P_CC

LA13_N

LA13_P

LA09_N

LA09_P

LA05_N

LA05_P

LA01_N_CC

LA01_P_CC

GBTCLK0_M2C_N

GBTCLK0_M2C_P

PG_C2M

LA23_P

3P3V_2

3P3V_3

A

B

GND

OE

VCC

DP6_C2M_P

DP7_C2M_N

DP7_C2M_P

DP8_C2M_N

DP8_C2M_P

DP9_C2M_N

DP9_C2M_P

GBTCLK1_M2C_N

GBTCLK1_M2C_P

DP6_M2C_P

DP7_M2C_N

DP7_M2C_P

DP8_M2C_N

DP8_M2C_P

DP9_M2C_N

DP6_C2M_N

DP9_M2C_P

RES0

CLK_DIR

DP6_M2C_N

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

Switch is ClosedWhen OE = 1

SCHEM, ROHS COMPLIANT

ANSI/VITA 57.1 - Revised 2010FMC HPC Header, Rows A, B, C, D

FMC HPC Header, Rows A, B, C, D

ZC706 EVALUATION PLATFORM

2.0

BF

2-14-2014_15:01

582404

8FMC_HPC_DP4_M2C_N

8FMC_HPC_DP4_M2C_P

8FMC_HPC_DP5_M2C_P

8FMC_HPC_DP5_M2C_N

FMC_HPC_DP4_C2M_P 8

FMC_HPC_DP4_C2M_N 8

8FMC_HPC_DP5_C2M_P

8FMC_HPC_DP5_C2M_N

8FMC_HPC_DP7_M2C_P

8FMC_HPC_DP7_M2C_N

FMC_HPC_DP6_M2C_P 8

FMC_HPC_DP6_M2C_N 8

FMC_HPC_DP7_C2M_P 8

FMC_HPC_DP7_C2M_N 8

8FMC_HPC_DP6_C2M_P

8FMC_HPC_DP6_C2M_N

8FMC_HPC_DP2_M2C_N

8FMC_HPC_DP2_M2C_P

FMC_HPC_DP1_M2C_N 8

FMC_HPC_DP1_M2C_P 8

8FMC_HPC_GBTCLK0_M2C_N

8FMC_HPC_GBTCLK0_M2C_P

8FMC_HPC_GBTCLK1_M2C_N

8FMC_HPC_GBTCLK1_M2C_P

24,28FMC_HPC_TDO_FMC_LPC_TDI

24,28FMC_HPC_TDO_FMC_LPC_TDI

B36

B33

B32

B29

B28

B25

B24

B21

B20

B16

B13

B12

B9

B8

B5

B37

B4

B40

B1

B17

J37 ASP_134486_01

FMC_HPC_PRSNT_M2C_B26,37

FMC_HPC_TMS_BUF 16

16,24FMC_TDI_BUF

1

2

3

4

5

U32 SC70_5

NC7SZ66

16,24FMC_TDI_BUF

36FMC_HPC_IIC_SDA

36FMC_HPC_IIC_SCL

NC

D40

D35

D34

D33

D32

D31

D30

D29

D27

D26

D24

D21

D20

D18

D17

D15

D14

D12

D11

D9

D8

D5

D4

D1

D23

D36

D38

J37 ASP_134486_01

FMC_HPC_DP0_M2C_N 8

FMC_HPC_DP0_M2C_P 8

8FMC_HPC_DP0_C2M_N

8FMC_HPC_DP0_C2M_P

8FMC_HPC_DP1_C2M_P

2

1

X5R25V1UFC3221

2

C3211UF25VX5R

NC

5FMC_HPC_LA27_P

NC

8FMC_HPC_DP1_C2M_N

FMC_HPC_LA06_P 4

FMC_HPC_LA27_N 5

FMC_HPC_LA18_CC_N 5

FMC_HPC_LA14_P 4

FMC_HPC_LA10_P 4

FMC_HPC_DP3_M2C_N 8

FMC_HPC_DP3_M2C_P 8

FMC_HPC_LA18_CC_P 5

FMC_HPC_LA14_N 4

FMC_HPC_LA10_N 4

FMC_HPC_LA06_N 4

FMC_HPC_DP2_C2M_N 8

FMC_HPC_DP2_C2M_P 8

8FMC_HPC_DP3_C2M_N

8FMC_HPC_DP3_C2M_P

NC

NC

NC

NC

NC

NC

NC

1

2

C3231UF25VX5R

C39

C37

C35

C34

C31

C30

C27

C26

C23

C22

C19

C18

C15

C14

C11

C10

C7

C6

C3

C2

J37 ASP_134486_01

A39

A38

A35

A34

A31

A30

A27

A26

A23

A22

A19

A18

A15

A14

A11

A10

A7

A6

A3

A2

J37 ASP_134486_01

NC

VADJ

FMC_HPC_LA01_CC_N 4

FMC_HPC_LA05_P 4

FMC_HPC_LA09_P 4

FMC_HPC_LA09_N 4

FMC_HPC_LA13_P 4

FMC_HPC_LA13_N 4

FMC_HPC_LA23_P 5

FMC_HPC_LA23_N 5

FMC_HPC_LA26_P 5

FMC_HPC_LA26_N 5

FMC_HPC_LA05_N 4

FMC_HPC_TCK_BUF 16

FMC_HPC_LA17_CC_P 5

FMC_HPC_LA17_CC_N 5

FMC_HPC_LA01_CC_P 4

25,28,38,49PWRCTL1_FMC_PG_C2M

Page 25: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

VADJ_3

LA33_N

LA33_P

LA31_N

LA31_P

LA29_N

LA29_P

LA25_N

LA25_P

LA22_N

LA22_P

LA20_N

LA20_P

LA16_N

LA16_P

LA12_N

LA12_P

LA08_N

LA08_P

LA03_N

LA03_P

LA00_N_CC

LA00_P_CC

CLK1_M2C_N

CLK1_M2C_P

VADJ_2

HB20_N

HB20_P

HB16_N

HB16_P

HB12_N

HB12_P

HB08_N

HB08_P

HB04_N

HB04_P

HB02_N

HB02_P

HA19_N

HA19_P

HA15_N

HA15_P

HA12_N

HA12_P

HA08_N

HA08_P

HA04_N

HA04_P

HA00_N_CC

PG_M2C

HA00_P_CC

HA01_P_CC

HA01_N_CC

HA05_P

HA05_N

HA09_P

HA09_N

HA13_P

HA13_N

HA16_P

HA16_N

HA20_P

HA20_N

HB03_P

HB03_N

HB05_P

HB05_N

HB09_P

HB09_N

HB13_P

HB13_N

HB19_P

HB19_N

HB21_P

HB21_N

VADJ_1

GND

VCC3V3

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

FMC Power Good

ANSI/VITA 57.1 - Revised 2010

FMC HPC Header, Rows E, F, G

FMC HPC Header, Rows E, F, G

ZC706 EVALUATION PLATFORM

04

25 58

2-14-2014_15:01

BF

2.0

21

DS23

LED-GRN-SMT

NC

NC

24,28,38,49 PWRCTL1_FMC_PG_C2M

VADJ

5FMC_HPC_CLK1_M2C_N

5FMC_HPC_CLK1_M2C_P

NC

NC

FMC_HPC_PG_M2C 37

1

32

Q13

NDS331N460MW

2

1 R28010.0K1/10W1%

2

1 R1522491/10W1%

FMC_HPC_LA00_CC_P 4

FMC_HPC_LA00_CC_N 4

FMC_HPC_LA03_P 4

FMC_HPC_LA03_N 4

FMC_HPC_LA08_P 4

FMC_HPC_LA08_N 4

FMC_HPC_LA12_P 4

FMC_HPC_LA12_N 4

FMC_HPC_LA16_P 4

FMC_HPC_LA16_N 4

FMC_HPC_LA20_P 5

FMC_HPC_LA20_N 5

FMC_HPC_LA22_P 5

FMC_HPC_LA22_N 5

FMC_HPC_LA25_P 5

FMC_HPC_LA25_N 5

FMC_HPC_LA29_P 5

FMC_HPC_LA29_N 5

FMC_HPC_LA31_P 5

FMC_HPC_LA31_N 5

FMC_HPC_LA33_P 5

FMC_HPC_LA33_N 5NC

NC

1

2 1%1/10W10.0KR281

E2

E3

E6

E7

E9

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

J37 ASP_134486_01

F40

F38

F37

F35

F34

F32

F31

F29

F28

F26

F25

F23

F22

F20

F19

F17

F16

F14

F13

F11

F10

F8

F7

F5

F1

F4

J37 ASP_134486_01

G39

G37

G36

G34

G33

G31

G30

G28

G27

G25

G24

G22

G21

G19

G18

G16

G15

G13

G12

G10

G9

G7

G6

G3

G2

J37 ASP_134486_01

NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VADJVADJ

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 26: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

VIO_B_M2C_2

HB17_N_CC

HB17_P_CC

HB14_N

HB14_P

HB10_N

HB10_P

HB06_N_CC

HB06_P_CC

HB00_N_CC

HB00_P_CC

HA23_N

HA23_P

HA21_N

HA21_P

HA17_N_CC

HA17_P_CC

HA10_N

HA10_P

HA06_N

HA06_P

HA02_N

HA02_P

CLK2_BIDIR_N

CLK2_BIDIR_P

VREF_B_M2C

VADJ_4

LA32_N

LA32_P

LA30_N

LA30_P

LA28_N

LA28_P

LA24_N

LA24_P

LA21_N

LA21_P

LA19_N

LA19_P

LA15_N

LA15_P

LA11_N

LA11_P

LA07_N

LA07_P

LA04_N

LA04_P

LA02_N

LA02_P

CLK0_M2C_N

CLK0_M2C_P

PRSNT_M2C_L

VREF_A_M2C

VIO_B_M2C_1

HB18_N

HB18_P

HB15_N

HB15_P

HB11_N

HB11_P

HB07_N

HB07_P

HB01_N

HB01_P

HA22_N

HA22_P

HA18_N

HA18_P

HA14_N

HA14_P

HA11_N

HA11_P

HA07_N

HA07_P

HA03_N

HA03_P

CLK3_BIDIR_N

CLK3_BIDIR_P

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

ANSI/VITA 57.1 - Revised 2010FMC HPC Header, Rows H, J, K

FMC HPC Header, Rows H, J, K

ZC706 EVALUATION PLATFORM

2.0

04

26 58

2-14-2014_15:01

BF

NC

NC

NC

NC

NC

24,37FMC_HPC_PRSNT_M2C_B

2

1 R944.7K1/10W5%

VADJ

NC

NC

NC

NC

J39

J37

J36

J34

J33

J31

J30

J28

J27

J25

J24

J22

J21

J19

J18

J16

J15

J13

J12

J10

J9

J7

J6

J3

J2

J37 ASP_134486_01

FMC_HPC_CLK0_M2C_N 4

FMC_HPC_CLK0_M2C_P 4

NC

4FMC_HPC_LA02_N

4FMC_HPC_LA02_P

5FMC_HPC_LA32_N

5FMC_HPC_LA32_P

5FMC_HPC_LA30_N

5FMC_HPC_LA30_P

5FMC_HPC_LA28_N

5FMC_HPC_LA28_P

5FMC_HPC_LA24_N

5FMC_HPC_LA24_P

5FMC_HPC_LA21_N

5FMC_HPC_LA21_P

5FMC_HPC_LA19_N

5FMC_HPC_LA19_P

4FMC_HPC_LA15_N

4FMC_HPC_LA15_P

4FMC_HPC_LA11_N

4FMC_HPC_LA11_P

4FMC_HPC_LA07_N

4FMC_HPC_LA07_P

4FMC_HPC_LA04_N

4FMC_HPC_LA04_P

NC

H40

H38

H37

H35

H34

H32

H31

H29

H28

H26

H25

H23

H22

H20

H19

H17

H16

H14

H13

H11

H10

H8

H7

H5

H4

H2

H1

J37 ASP_134486_01

K40

K38

K37

K35

K34

K32

K31

K29

K28

K26

K25

K23

K22

K20

K19

K17

K16

K14

K13

K11

K10

K8

K7

K5

K4

K1

J37 ASP_134486_01

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Page 27: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND GND

GND

GND_1

GND_10

GND_100

GND_101

GND_102

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_11

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_12

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_13

GND_130

GND_131

GND_132

GND_133

GND_134

GND_135

GND_136

GND_137

GND_138

GND_139

GND_14

GND_140

GND_141

GND_142

GND_143

GND_144

GND_145

GND_146

GND_147

GND_148

GND_149

GND_15

GND_150

GND_151

GND_152

GND_153

GND_154

GND_155

GND_156

GND_157

GND_16

GND_17

GND_18

GND_19

GND_2

GND_20

GND_21

GND_22

GND_23

GND_24

GND_25

GND_26

GND_27

GND_28

GND_29

GND_3

GND_30

GND_31

GND_32

GND_33

GND_34

GND_35

GND_36

GND_37

GND_38

GND_39

GND_4

GND_40

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_5

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_6

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_7

GND_70

GND_71

GND_72

GND_73

GND_74

GND_75

GND_76

GND_77

GND_78

GND_79

GND_8

GND_80

GND_81

GND_82

GND_83

GND_84

GND_85

GND_86

GND_87

GND_88

GND_89

GND_9

GND_90

GND_91

GND_92

GND_93

GND_94

GND_95

GND_96

GND_97

GND_98

GND_99

GND_159

GND_158

GND_ST2

GND_ST1

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

ANSI/VITA 57.1 - Revised 2010FMC HPC Header, GND

FMC HPC Header, GND

ZC706 EVALUATION PLATFORM

2.0

04

27 58

2-14-2014_15:01

BF

1

2 DNPDNPDNPR315

2

1 R314DNPDNPDNP

2

1

NP0500V100PFC4881

2

C487100PF500VNP0

A1

A20

F33

F36

F39

G1

G4

G5

G8

G11

G14

G17

A21

G20

G23

G26

G29

G32

G35

G38

G40

H3

H6

A24

H9

H12

H15

H18

H21

H24

H27

H30

H33

H36

A25

H39

J1

J4

J5

J8

J11

J14

J17

J20

J23

A28

J26

J29

J32

J35

J38

J40

K2

K3

K6

K9

A29

K12

K15

K18

K21

K24

K27

K30

K33

A32

A33

A36

A37

A4

A40

B2

B3

B6

B7

B10

B11

B14

B15

B18

A5

B19

B22

B23

B26

B27

B30

B31

B34

B35

B38

A8

B39

C1

C4

C5

C8

C9

C12

C13

C16

C17

A9

C20

C21

C24

C25

C28

C29

C32

C33

C36

C38

A12

C40

D2

D3

D6

D7

D10

D13

D16

D19

D22

A13

D25

D28

D37

D39

E1

E4

E5

E8

E11

E14

A16

E17

E20

E23

E26

E29

E32

E35

E38

E40

F2

A17

F3

F6

F9

F12

F15

F18

F21

F24

F27

F30

K39

K36

ST1

ST2

J37ASP_134486_01

Page 28: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GNDGND

A

B

GND

OE

VCC

VCC12_P

VCC12_P

GND

GND

VCC3V3

GND

VCC3V3

3P3VAUX

3P3V_2

3P3V_3

3P3V_4

GA1

GBTCLK0_M2C_N

GBTCLK0_M2C_P

LA01_N_CC

LA01_P_CC

LA05_N

LA05_P

LA09_N

LA09_P

LA13_N

LA13_P

LA17_N_CC

LA17_P_CC

LA23_N

LA23_P

LA26_N

LA26_P

PG_C2M

TCK

TDI

TDO

TMS

TRST_L

CLK0_M2C_N

CLK0_M2C_P

LA02_N

LA02_P

LA04_N

LA04_P

LA07_N

LA07_P

LA11_N

LA11_P

LA15_N

LA15_P

LA19_N

LA19_P

LA21_N

LA21_P

LA24_N

LA24_P

LA28_N

LA28_P

LA30_N

LA30_P

LA32_N

LA32_P

PRSNT_M2C_L

VADJ_4

VREF_A_M2C

12P0V_1

12P0V_2

3P3V_1

DP0_C2M_N

DP0_C2M_P

DP0_M2C_N

DP0_M2C_P

GA0

LA06_N

LA06_P

LA10_N

LA10_P

LA14_N

LA14_P

LA18_N_CC

LA18_P_CC

LA27_N

LA27_P

SCL

SDA

VCC3V3

GND

GND

CLK1_M2C_N

CLK1_M2C_P

LA00_N_CC

LA00_P_CC

LA03_N

LA03_P

LA08_N

LA08_P

LA12_N

LA12_P

LA16_N

LA16_P

LA20_N

LA20_P

LA22_N

LA22_P

LA25_N

LA25_P

LA29_N

LA29_P

LA31_N

LA31_P

LA33_N

LA33_P

VADJ_3

GND

VCC3V3

VCC3V3

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_130

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_70

GND_71

GND_72

GND_73

GND_ST1

GND_ST2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

ANSI/VITA 57.1 - Revised 2010

ANSI/VITA 57.1 - Revised 2010

Switch is ClosedWhen OE = 1

FMC LPC Connector

ZC706 EVALUATION PLATFORMSCHEM, ROHS COMPLIANT

BF

2-14-2014_15:01

5828

2.0

04

24,25,38,49PWRCTL1_FMC_PG_C2M

1

2 DNPDNPDNPR304

FMC_LPC_GBTCLK0_M2C_N 8

FMC_LPC_GBTCLK0_M2C_P 8

FMC_LPC_DP0_C2M_P 8

FMC_LPC_DP0_C2M_N 8

8FMC_LPC_DP0_M2C_P

8FMC_LPC_DP0_M2C_N

2

1 R303DNPDNPDNP

NC

FMC_LPC_TDO_FPGA_TDI 3,28

24,28FMC_HPC_TDO_FMC_LPC_TDI

3,28FMC_LPC_TDO_FPGA_TDI

FMC_HPC_TDO_FMC_LPC_TDI 24,28

G1

G4

G5

G8

G11

G14

G17

G20

G23

G26

G29

G32

G35

G38

G40

H3

H6

H9

H12

H15

H18

H21

H24

H27

H30

H33

H36

H39

C1

C4

C5

C8

C9

C12

C13

C16

C17

C20

C21

C24

C25

C28

C29

C32

C33

C36

C38

C40

D2

D3

D6

D7

D10

D13

D16

D19

D22

D25

D28

D37

D39

ST1

ST2

J5

ASP_134603_01

G3

G2

G7

G6

G10

G9

G13

G12

G16

G15

G19

G18

G22

G21

G25

G24

G28

G27

G31

G30

G34

G33

G37

G36

G39

J5

ASP_134603_01

VADJ

C35

C37

C39

C3

C2

C7

C6

C34

C11

C10

C15

C14

C19

C18

C23

C22

C27

C26

C30

C31

J5

ASP_134603_01

H5

H4

H8

H7

H11

H10

H14

H13

H17

H16

H20

H19

H23

H22

H26

H25

H29

H28

H32

H31

H35

H34

H38

H37

H2

H40

H1

J5

ASP_134603_01

D32

D36

D38

D40

D35

D5

D4

D9

D8

D12

D11

D15

D14

D18

D17

D21

D20

D24

D23

D27

D26

D1

D29

D30

D31

D33

D34

J5

ASP_134603_01

1

2

C3141UF25VX5R

2

1

X5R25V1UFC3131

2

C3121UF25VX5R

VADJ

VADJ

1

2 5%1/10W4.7KR32

1

2

3

4

5

U31 SC70_5

NC7SZ66

16FMC_LPC_TMS_BUF

FMC_LPC_LA01_CC_P 4

5FMC_LPC_LA17_CC_N

5FMC_LPC_LA17_CC_P

FMC_LPC_TCK_BUF 16

36FMC_LPC_IIC_SDA

36FMC_LPC_IIC_SCL

FMC_LPC_LA28_N 5

FMC_LPC_LA06_P 4

5FMC_LPC_LA27_N

4FMC_LPC_LA05_N

5FMC_LPC_LA26_N

5FMC_LPC_LA26_P

5FMC_LPC_LA23_N

5FMC_LPC_LA23_P

4FMC_LPC_LA13_N

4FMC_LPC_LA13_P

4FMC_LPC_LA09_N

4FMC_LPC_LA09_P

4FMC_LPC_LA05_P

4FMC_LPC_LA01_CC_N

4FMC_LPC_LA06_N

4FMC_LPC_LA10_P

4FMC_LPC_LA10_N

4FMC_LPC_LA14_P

4FMC_LPC_LA14_N

5FMC_LPC_LA18_CC_P

5FMC_LPC_LA18_CC_N

5FMC_LPC_LA27_P

5FMC_LPC_CLK1_M2C_P

5FMC_LPC_CLK1_M2C_N

5FMC_LPC_LA33_P

5FMC_LPC_LA33_N

5FMC_LPC_LA31_P

5FMC_LPC_LA31_N

5FMC_LPC_LA29_P

5FMC_LPC_LA29_N

5FMC_LPC_LA25_P

5FMC_LPC_LA25_N

5FMC_LPC_LA22_P

5FMC_LPC_LA22_N

5FMC_LPC_LA20_P

5FMC_LPC_LA20_N

4FMC_LPC_LA16_P

4FMC_LPC_LA16_N

4FMC_LPC_LA12_P

4FMC_LPC_LA12_N

4FMC_LPC_LA08_P

4FMC_LPC_LA08_N

4FMC_LPC_LA03_P

4FMC_LPC_LA03_N

4FMC_LPC_LA00_CC_P

4FMC_LPC_LA00_CC_N

5FMC_LPC_LA30_P

5FMC_LPC_LA24_N

5FMC_LPC_LA24_P

5FMC_LPC_LA21_N

NC

5FMC_LPC_LA19_N

5FMC_LPC_LA21_P

4FMC_LPC_LA15_N

5FMC_LPC_LA19_P

4FMC_LPC_LA11_N

4FMC_LPC_LA15_P

4FMC_LPC_LA07_N

4FMC_LPC_LA11_P

4FMC_LPC_LA04_N

4FMC_LPC_LA07_P

4FMC_LPC_LA02_N

4FMC_LPC_LA04_P

4FMC_LPC_CLK0_M2C_N

4FMC_LPC_LA02_P

4FMC_LPC_CLK0_M2C_P

5FMC_LPC_LA30_N

5FMC_LPC_LA32_N

5FMC_LPC_LA32_P

5FMC_LPC_LA28_P

FMC_LPC_PRSNT_M2C_B 28,37

FMC_LPC_PRSNT_M2C_B28,37

1

2

C486100PF500VNP0

2

1

NP0500V100PFC485

28FMC_LPC_ST1

28FMC_LPC_ST2

28FMC_LPC_ST1 28FMC_LPC_ST2

Page 29: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

A

BYAND

GND

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

TD1_P

TD0_N

TD1_N

TD2_P

TD2_N

TD3_N

TD3_P

VCC

TD0_P

GND

SH2

SH1

10/100/1000

MAGNETICS

RJ45 AND

CONFIG0CONFIG1CONFIG2CONFIG3

CTRL18DIS_REG12

HSDAC_NHSDAC_P

LED0LED1LED2

MDC MDI0_NMDI0_P

MDI1_NMDI1_P

MDI2_NMDI2_P

MDI3_NMDI3_P

MDIO

RSET

RXD0RXD1RXD2RXD3

RX_CLKRX_CTRL

TCK

TDITDO

TMS

TRST_B

TSTPT

TXD0TXD1TXD2TXD3

TX_CLKTX_CTRL

XTAL_INXTAL_OUT

VREF

COMA_B

RESET_B

RGMII

MGMT

MDI

JTAG

TEST

ON HSDAC_P AND HSDAC_N.TEST PORT: IF USING THE TEST PORT INSTALL 49.9 OHM PULLDOWN RESITORS

SEE CONFIGURATION MAPPING TABLE FOR JUMPER SETTINGS

ENA_XC=0

EPHY_LED0

RGMII_RX=0

RGMII_TX=0

EPHY_LED1

EPHY_LED0

RGMII_TX=0 RGMII_RX=0

RGMII_RX=1

RGMII_TX=1

RGMII_TX=1 RGMII_RX=1

CONFIG3

ENA_XC=0

ENA_XC=1 PHYAD[4]=1

CONFIG2

GND

PHYAD[4]=1

CONFIG1

CONFIG0

PIN CONFIGURATION

CONFIGURATION MAPPING

PHYAD[3]=0

SETTING

PHYAD[1]=1 PHYAD[0]=1

PHYAD[2]=1

EPHY_LED0

GND PHYAD[4]=0

VCCO_MIO1

VCCO_MIO1

VCCO_MIO1

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

2 PLACES

2 PLACES

GEM / MDIO

GEM / MDIO

2-14-2014_15:01

5829

2.0

04

BF

21

DS28

LED-GRN-SINGLE-STACK

2

1

FERRITE-220

L37

GND

1

2

L9

FERRITE-220

VCC3V3_PSVCC3V3_PS

VCCP1V8

VCCP1V8

VCCP1V8

VCCP1V8

VCCP1V8

NC

NC

NC

NC

NC

GND

64123

1712

3536

689

48 3031

2526

2324

1920

45

33

50515455

5349

42

4344

41

11

32

58596162

6063

3839

57

4

10

U51 QFN_64

88E1116R

3

2

6

4

5

8

7

9

1

10

SH2

SH1

P3

RJ45

9 PHY_RESET_B_AND

PHY_LED1 29

29 PHY_LED0

29PHY_LED0

GND

2

1 R3561.00K1/16W

1

2

J20

DNP 1

PHY_MDI0_PPHY_MDI0_N

PHY_MDI1_PPHY_MDI1_N

PHY_MDI2_P

PHY_MDI3_P

PHY_MDI2_N

GND

9,15,31 PS_POR_BPHY_RESET_B 29

GND

GND

PHY_RESET_B29

PHY_RXD09

PHY_XTAL_IN 29

PHY_XTAL_OUT 29

PHY_XTAL_OUT29

PHY_XTAL_IN29

PHY_HSDAC_NPHY_HSDAC_P

PHY_LED0 29

PHY_MDI3_N

PHY_LED0 29

PHY_LED1 29

PHY_RXD19

PHY_RXD29

PHY_RX_CTRL9

PHY_RX_CLK9

PHY_TXD09

PHY_TXD19

PHY_TXD29

PHY_TXD39

PHY_TX_CTRL9

PHY_TX_CLK9

PHY_MDC9

2

1

R36DNP2

1 R35

2

1R344.7K

1/10W

2

1 R4084.99K1/10W

2

1 R3571.00K1/16W

GND

2

1 C49518PF50VNPO

2

1

C494

2

1R355DNP

3

2

4

1X1

25.00MHZ

50PPM

1

2

3

J47 GND

1

2

3

J46

1

2

3

J45

2

1 R3541.00K1/16W

2

1 R334.7K1/10W

PHY_LED2 29

PHY_RXD39

PHY_MDIO9

1

2

3

5

4

U29 SC70_5

SN74LVC1G08

2

1

25V0.1UFC45

GND

1

2

J9

1

21/16W1.00KR358

GND

2

1

2

GND

1

32

Q6

NDS331N460MW

2

1R388261

1/10W

GND

1

32

Q5

NDS331N460MW

2

1R387261

1/10W

VCC3V3_PS

GND

1

32

Q4

NDS331N460MW

2

1R386261

1/10W

PHY_LED229PHY_LED129PHY_LED029

VCCMIO_FILT

1

2

C460.1UF25V

1

2

C4701000PF50VX7R

GND

NC

NC

NC

12

LED-GRN-SINGLE-STACK

DS29

21

DS30

LED-GRN-SINGLE-STACK

Page 30: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VDDOR_52VDDOR_56

VDDO_46

AVDDR_15

AVDDC_34AVDDC_37

AVDD_29

AVDD_21AVDD_22AVDD_27

AVDDX_16

AVDDR_14

VDDO_7

DVDD_5DVDD_13DVDD_40DVDD_47

NC_28NC_18

EPAD

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

GEM / MDIO

GEM / MDIO

GEM / MDIO - POWER & DECOUPLING

AVDD

AVDDX, AVDDR, AVDDC

MAGNETICS / RJ45

VDDO, VDDOR

DVDD

2-14-2014_15:01

5830

2.0

04

BF

VCCP1V8

VCCP1V8

VCCP1V8

5256

46

15

3437

29

212227

16

14

7

5134047

2818

65

U51 QFN_64

88E1116R VCCMIO_FILT

VCCMIO_FILT

VCCMIO_FILT

VCCMIO_FILT

PHY_DVDD

VCCMIO_FILT

GND

PHY_DVDD

GND

1

2

C4934.7UF10V

1

2

C690.1UF25V

GND

1

2

C680.1UF25V

1

2

C670.1UF25V

1

2

C660.1UF25V

1 2

L10FERRITE-220

1

2

C650.1UF25V

1

2

C640.1UF25V

1

2

C630.1UF25V

GND

1

2

C620.1UF25V

1

2

C610.1UF25V

1

2

C600.1UF25V

1

2

C590.1UF25V

GND

1

2

C580.1UF25V

1

2

C570.1UF25V

1

2

C560.1UF25V

GND

1

2

C550.1UF25V

1

2

C540.1UF25V

1

2

C530.1UF25V

1

2

C520.1UF25V

1

2

C510.1UF25V

1

2

C500.1UF25V

1

2

C490.1UF25V

1

2

C480.1UF25V

1

2

C470.1UF25V

1

2

C4924.7UF10V

1

2

C4914.7UF10V

1

2

C4904.7UF10V

1

2

C4894.7UF10V

NCNC

Page 31: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

EN OUT2IN

GNDNC1

FLG

NC2OUT1

REFSEL2_14

DATA0_3

RBIAS_23

ID_23

VBUS_22

VBAT_21

VDD33_P

DM_19

DP_18

CPEN33_17

NC_12

REFSEL0_8

DATA4_7

DATA6_10

CLKOUT_1

NXT_2

DATA2_5

REFSEL1_11

VDDIO_32

DIR_31

DATA5_9

DATA7_13

DATA1_4

SPK_L_15

REFCLK_26

SPK_R_16

XO_25

VDD18_30

DATA3_6

STP_29

VDD18_28

RESETB_27

CTR_GND_33

SHLD5

SHLD6

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

C

AYB

GND

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

1-2 = DEVICE MODE OFF = DEVICE MODE2-3 = HOST OR OTG MODE

ON = HOST OR OTG MODE

USB HOST POWER

1-2 = A/B CABLE DETECT2-3 = ID NOT USED

3 PLACES

2 PLACES

CVBUS Select:1-2: OTG Mode2-3: Host Mode

USB 2.0 ULPI TRANSCEIVER AND CONNECTOR

USB ULPI

USB ULPI

BF

04

2.0

31 58

2-14-2014_15:01

VCC3V3_PS

VCCP1V8

VCCP1V8

VCCP1V8

VCCP1V8

6

1

2

5

43

U13 SC70_6

SN74LVC1G11

1 2

L11FERRITE-220

USB_D_P31

USB_D_N31

USB_RESET_B

31

USB_RESET_B_AND9,15 PS_POR_B9,15,29

USB_STP

9

USB_DIR

9

USB_DATA7

9

USB_DATA6

9

USB_DATA5

9

2

1

25V0.1UFC73

USB_DATA49

GND

1

2

C760.1UF25V

GND

31USB_D_N

1

21/10W10.0KR268

2

1R26710.0K1/10W

GND

1

2

J10

1

2

C3801UF16VX5R

10

11

5

9

1

2

3

6 7 8

4

J2

ZX62D_AB_5P8

GND

GND

1

2

C484120UF20VTANT

321

J50

GND

1

2

3

J49

USB_CLKOUT9

USB_NXT9

USB_DATA19

USB_DATA09

USB_DATA29

USB_DATA39

14

3

24

23

22

21

20

19

18

17

12

8

7

10

1

2

5

11

32

31

9

13

4

15

26

16

25

30

6

29

28

27

33

U12 USB3320_QFN32

USB3320_QFN32

GND

1

2

C711

2

C70

0.1UF25V

2

1C49618PF50VNPO

GND

GND

21

X2

24.000MHZ

GND

2

1 C2092.2UF6.3V

GND

GND

VCC5V0

GND

2

1

C335DNP

1 2 3

J48

USB_VBUS_SEL

VCC5V0

2

1C4475.6UF10V

1 2

L12FERRITE-220

GND

2 1

DS25

LED-RED-SMT

2

1R389261

1/10W

1 87

34

2

56

U22 SOP127P500X600_8

MIC2025_SOP8

2

1 R3591.00K1/16W

GND

1

2

C750.1UF25V

USB_VBUS_SEL

1 2 3

J51

1

2

C469150UF10VTANT

GND

2

1 C49718PF50VNPO

2

1R4031.0M

1/10W5%

1

2

C74

USB_ID 31

USB_VDD33 31

USB_ID 31

USB_D_P 31

NC

NC

NC

NC

NC

USB_VDD33 31

GND

21R178

8.06K

1/10W

1%

2

1

25V0.1UFC72

2

1

J11 GNDUSB_RESET_B 31

Page 32: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

VCC3V3

GND

GND

VCC3V3

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

OE

GNDOUT

VCC

DSD0

DSD1

DSD2

DSD3

DSD4

DSD5

DSD_CLK

I2S0

I2S2

I2S1

LRCLK

SCLK

I2S3

HEAC_P

HEAC_N

D31D32D33D34D35

D12D13D14D15

D29D30

D1

D4D5D6

D28D27D26D25D24D23D22D21D20

D0

D19

D3D2

D11D10D9D8D7

D16

GND10DE

CLK

D18D17

TX2_P

TX2_N

TX1_P

TX1_N

TX0_P

TX0_N

TXC_P

TXC_N

SPDIF

R_EXT

VSYNCHSYNC

SDASCL

DDCSDA

DDCSCL

CEC

CEC_CLK

SPDIF_OUT

INTPD

PVDD1PVDD2PVDD3

AVDD2AVDD3

AVDD1

GND1GND2

GND6

GND3GND4GND5

GND7GND8GND9

GND11

DVDD_3V

BGVDD

DVDD1DVDD2DVDD3DVDD4DVDD5

MCLK

HPD

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

To HDMI Connector

HDMI CODEC

HDMI CODEC

BF

04

2.0

32 58

2-14-2014_15:01

3 4 5 6 7 8 9

12

1413

171615

52

51

6160595857

84838281

6362

95

929190

646566676869707172

96

73

9394

8586878889

80

4497

79

7478

43

42

40

39

36

35

33

32

10

28

298

5655

54

53

48

50

46

4538

212425

3441

29

99100

23

182022

273137

75

47

26

767749191

11

30

U53LQFP100_14X14

ADV7511

1

23

4

U5012.00000MHZ

SIT8102

50PPM

33 HDMI_D2233 HDMI_D23

HDMI_D2133HDMI_D2033

33 HDMI_D16

HDMI_CEC_CLK

21

1%

1/10W

24.9

R172

HDMI_CEC_CLK_R

2

1 R1588871/10W1%

VADJ

1 2

L16

FERRITE-220

HDMI_AVDDHDMI_PLVDD

HDMI_PLVDD

HDMI_AVDD

HDMI_PLVDD

2

1

X5R25V

0.1UFC88

HDMI_DVDD

HDMI_DVDD_3V

2

1

1%1/10W2.43KR165

1

2

R1642.43K1/10W1%

2

1 C57210UF16VX5R

2

1 C57110UF16VX5R

2

1 C57010UF16VX5R

2

1 C56910UF16VX5R

VCC2V5

1

2

C870.1UF25VX5R

HDMI_DVDD

VCC1V8

21

FERRITE-220

L151

2

C3460.01UF25VX7R

2

1 R1632.43K1/10W1%

2

1

X5R25V0.1UFC86

2

1

X7R25V0.01UFC345 1 2

L14

FERRITE-220

21

FERRITE-220

L131

2

C3440.01UF25VX7R

1

2

C850.1UF25VX5R

VCC1V8

1

2

C3430.01UF25VX7R

1

2

C840.1UF25VX5R

2

1

X7R25V0.01UFC342

2

1

X5R25V0.1UFC831

2

C820.1UF25VX5R

1

2

C3410.01UF25VX7R

1

2

C810.1UF25VX5R

1

2

C3400.01UF25VX7R

2

1

X5R25V0.1UFC80

2

1

X7R25V0.01UFC339

1

2

C3380.01UF25VX7R

1

2

C790.1UF25VX5R

2

1

X7R25V0.01UFC337

2

1

X5R25V0.1UFC78

VCC1V8

2

1

X5R25V0.1UFC77

2

1

X7R25V0.01UFC336

HDMI_AVDD

HDMI_DVDD_3V

HDMI_HEAC_C_N33

HDMI_CLK33

HDMI_HSYNC3333 HDMI_VSYNC

4 HDMI_INT

36 IIC_SCL_HDMI

HDMI_SPDIF_OUT 3836 IIC_SDA_HDMI

33HDMI_CEC

HDMI_DDCSDA 33

HDMI_DE33

HDMI_D0_P 33

33HDMI_DDCSCL

33HDMI_HEAC_NHDMI_HEAC_P 33

HDMI_CLK_N 3333HDMI_CLK_P

HDMI_D2_N 3333HDMI_D2_P

HDMI_D1_N 3333HDMI_D1_P

HDMI_D0_N 33

HDMI_SPDIF33

33 HDMI_D5HDMI_D433

HDMI_D1033

33 HDMI_D833 HDMI_D9

HDMI_D1133

HDMI_D63333 HDMI_D7

HDMI_D193333 HDMI_D18

HDMI_D1733

HDMI_D293333 HDMI_D30

HDMI_D3133

33 HDMI_D28

HDMI_D3233HDMI_D3333

33 HDMI_D3533 HDMI_D34

Page 33: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND GND

GND

IN1

IN2

GND1

IN3IN4 OUT4

OUT3

GND2

OUT2

OUT1

IN1

IN2

GND1

IN3IN4 OUT4

OUT3

GND2

OUT2

OUT1

GND

GND

VCC3V3

GND4

CLK_PCLK_N

DATA1_PDATA1_N

DATA2_PDATA2_N

HEAC_N

TDMS_CLK_SHLDTDMS_SHLD0TDMS_SHLD1TDMS_SHLD2

HEAC_P

DDC_VCC5DATA0_NDATA0_P

CEC

GND2GND3

GND1

DDC_CEC_GND

DDC_CLKDDC_DATA

GNDGND

IN1

IN2

GND1

IN3IN4 OUT4

OUT3

GND2

OUT2

OUT1

IN1

IN2

GND1

IN3IN4 OUT4

OUT3

GND2

OUT2

OUT1

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

HDMI_HEAC_C_N

HDMI CONNECTOR

HDMI CONNECTOR

2-14-2014_15:01

5833

2.0

04

BF

1 25%

1/10W

0R507

21R506

0 1/10W

5%

1 25%

1/10W

0R505

21R504

0 1/10W

5%

21R503

0 1/10W

5%

5 HDMI_R_D28

5 HDMI_R_D29

5 HDMI_R_D30

5 HDMI_R_D31

5 HDMI_R_D32

5 HDMI_R_D33

5 HDMI_R_D34

4 HDMI_R_D35

5 HDMI_R_D16

5 HDMI_R_D17

5 HDMI_R_D18

5 HDMI_R_D19

5 HDMI_R_D20

5 HDMI_R_D21

5 HDMI_R_D22

5 HDMI_R_D23

1 21/10W

R134

30

1%21

1%

30R133

1/10W

21R132

301/10W

1%1 2

1%1/10W

30R131

21R130

301/10W

1%

1 21%

1/10W

30R125

21R124

301/10W

1%1 2

1%1/10W

30R123

21R122

301/10W

1% 1 2

1%1/10W

30R121

21R120

301/10W

1% 1 2

1%1/10W

30R119

21R118

301/10W

1%

VIDEO_GND

1

2 DNPDNPDNPR3052

1R3260

1/10W5%

21

D3

DFLS1150

820MV

10

9

8

7

65

4

3

2

1

15VRCLAMP0524P

DP4

1

2

3

4

5 6

7

8

9

10

DP3

RCLAMP0524P 15V

23

1012

46

13

19

11852

14

1897

13

2122

20

17

1516

P1

500254-1927

1 2

C316

1UF

25V

X5R

VCC5V0

2

1 R1672.43K1/10W1%

HDMI_DVDD

2

1 R15927.4K1/10W1%

2

1 R15649.91/20W1%

1

2

3

4

5 6

7

8

9

10

DP2

RCLAMP0524P 15V

VIDEO_GND

1 2

C347

0.01UF

25V

X7R

10

9

8

7

65

4

3

2

1

15VRCLAMP0524P

DP1

1

2 1%1/20W49.9R155

21

X5R

25V

1UF

C315

2

1 R26910.0K1/10W1%

VCC5V0

2

1

1%1/10W2.43KR166

VIDEO_GND

HDMI_D4 32

32HDMI_D5

HDMI_D6 32

5 HDMI_R_D4

5 HDMI_R_D5

5 HDMI_R_D6

32HDMI_SPDIF

HDMI_DE 32

32HDMI_HSYNC

32HDMI_CLK

HDMI_VSYNC 32

HDMI_R_SPDIF4

HDMI_R_DE5

HDMI_R_HSYNC5

HDMI_R_CLK5

HDMI_R_VSYNC5

HDMI_CEC

HDMI_DDC_CEC_GND

HDMI_CEC32NCNC

NCNC

HDMI_D1_NHDMI_D1_P

HDMI_D7 32

HDMI_D8 32

HDMI_D9 32

32HDMI_D10

32HDMI_D11

5 HDMI_R_D7

5 HDMI_R_D8

5 HDMI_R_D9

5 HDMI_R_D10

5 HDMI_R_D11

HDMI_CLK_PHDMI_CLK_N

HDMI_D2_PHDMI_D2_NHDMI_D2_N32

32 HDMI_D2_P

HDMI_CLK_N3232 HDMI_CLK_P

32 HDMI_DDCSDAHDMI_DDCSCL32

HDMI_HEAC_N32HDMI_HEAC_C_N32

32 HDMI_HEAC_P HDMI_HEAC_C_P HDMI_DDCSDA

HDMI_HEAC_C_NHDMI_HEAC_C_P

HDMI_DDCSCL

HDMI_D1_N3232 HDMI_D1_P

HDMI_D0_NHDMI_D0_P

32 HDMI_D0_N32 HDMI_D0_P

NCNC

HDMI_D23 32

HDMI_D22 32

32HDMI_D21

32HDMI_D20

32HDMI_D19

32HDMI_D18

HDMI_D17 32

32HDMI_D16

1 21%

1/10W

30R446

21R445

30

1/10W

1%

1 21%

1/10W

30R444

21R443

30

1/10W

1%

1 21%

1/10W

30R442

21R441

30

1/10W

1%

1 21%1/10W

30R440

21R439

301/10W

1%

HDMI_D35 32

HDMI_D34 32

32HDMI_D33

32HDMI_D32

32HDMI_D31

32HDMI_D30

HDMI_D29 32

32HDMI_D28

21R454

301/10W

1%

1 21%1/10W

30R453

21R452

301/10W

1%

1 21%1/10W

30R451

21R450

301/10W

1%

1 21%1/10W

30R449

21R448

301/10W

1%

1 21%

1/10W

30R447

Page 34: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

OE

GND OUT

VCC

VCC3V3

VCC3V3

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NCOEGND

SDA

OUTOUT_BVDD

SCL

NCGND

VCCOUT_B

OUT

OE

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Default: 156.25MHz

Clocks

SIT9102AI-243N25E200.0000

33.33333MHz

Clocks

2-14-2014_15:01

5834

2.0

04

BF

23

654

1

U64

200MHZ

SIT9102

USRCLK_SFP_SCL36,41

USRCLK_SFP_SDA36,41

8

654

7

321

50PPM

SI570

10MHZ-810MHZ

U37

VCCP1V8

VCCP1V8

2

1 R3221001/20W5%

USRCLK_P 4

USRCLK_N 4

21

1%1/10W

24.9

R173

PS_CLK_R

NC

2

1 R384.7K1/10W5%

1

2

C890.1UF10VX5R

NC

2

1

X7R25V0.01UFC348

1

2 5%1/10W4.7KR37

VCC2V5

1

2 3

4

U24

33.33333MHZ 50PPM

1

2

C3490.01UF25VX7R

PS_CLK 9

SYSCLK_P 66SYSCLK_N

1

2 5%1/20W100R323

Page 35: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

VIN

GND

EN ADJ

VOUT

GND

IN OUT

GND

REF3012

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

XADC Header and Reference

XADC Header and Reference

BF

2-14-2014_15:01

5835

2.0

04

VCC1V5_PL

2

1 R62.7K1/10W1%

1

2

C44910UF10VX5R

1

2

C44810UF10VX5R

XADC_VCC3,35

2 1

J14

12

J13

XADC_VCC3,35

1

2

3

J52

HDR_1X3

7 XADC_VAUX0N_R

7 XADC_VAUX0P_R

7 XADC_VAUX8N_R

7 XADC_VAUX8P_R

XADC_VN_R3

XADC_VP_R3

2

1

X7R50V1000PFC473

21R237

100

1/10W

1%

1 21%1/10W

100

R236

XADC_VCC5V0

XADC_VCC5V0

1

2

C4721000PF50VX7R

2

1

X7R50V1000PFC471

XADC_AGNDXADC_AGND

7

2

6

4

8

1

3

5

9

11

13

15

17

19

10

12

14

16

18

20

J63

TST-110-01-G-D

1 2

3U38

IC VOLT REF, 1.25V

SOT23_3

XADC_VCC5V0

3

2

1

HDR_1X3

J53

2

1 C57410UF16VX5R2

1 C57310UF16VX5R

VCC5V0

XADC_AGND

12

L3

FERRITE-600

XADC_AGND

XADC_AGND

2

1 R3601.00K1/16W1%

XADC_AGND

1

2

3 4

5

U14TSOT_5

ADP123

VCCAUX

2 1

FERRITE-600

L2

XADC_AGND21

R235

100

1/10W

1%

1 21%

1/10W

100

R234

21R233

100

1/10W

1%

1 21%

1/10W

100

R232

2 1

FERRITE-600

L1

XADC_VAUX0N 35

35XADC_VAUX0P

7XADC_GPIO_0

7XADC_GPIO_2

7 XADC_GPIO_1

7 XADC_GPIO_3

35XADC_VAUX0N

XADC_VAUX8P 3535 XADC_VAUX8N

XADC_VAUX8N 35

35XADC_VAUX8P

XADC_VREF 35

XADC_VREF35

XADC_VN 35

35XADC_VP

XADC_VREFP3

XADC_VCC_HEADER35

3XADC_DXN

XADC_VP 35

XADC_VCC_HEADER 35

XADC_VAUX0P35

XADC_VN35

XADC_DXP3

12 J12

3

2

1

HDR_1X3

J54

Page 36: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

SCLSDA

A0A1A2

WP

VCCGND

GND

GND GNDGND

GND

GND

VCCBVCCA

SCLA

SDAA SDAB

SCLB

GND OE

VCCBVCCA

SCLA

SDAA SDAB

SCLB

GND OE

THERMPAD

SD0SC0SD1SC1SD2SC2

SD7SC7

SD6SC6

SD5SC5

SD4SC4

SC3SD3

A1A0

A2

VCC

SCLSDA

RESET_B

GND

GND

GNDofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn ByGND

SCHEM, ROHS COMPLIANT PCB P/N: 1280681SCH P/N: 0381513ZC706 EVALUATION PLATFORM

IIC MUX, EEPROM

IIC MUX, EEPROM

04

2.0

BF36 58

2-14-2014_15:01

1

2 DNPDNPDNPR62

2

1 R61DNPDNPDNP

1

2 DNPDNPDNPR43

2

1 R42DNPDNPDNP

PORT_EXPANDER_DDR3_SDA23,37

USRCLK_SFP_SDA34,41USRCLK_SFP_SCL34,41

PORT_EXPANDER_DDR3_SCL23,37

1

2 5%1/10W4.7KR60

48,49 PMBUS_CLK48,49 PMBUS_DATA

IIC_SCL_HDMI32IIC_SDA_HDMI32

FMC_LPC_IIC_SDA2824 FMC_HPC_IIC_SCL24 FMC_HPC_IIC_SDA

VCC3V3_PS

VCC3V3_PSVCCP1V8

PS_SCL_MAIN9

VADJ

VCC3V3_PS

VCC3V3_PS

VCC3V3_PS

VCC3V3_PS

RTC_SI5324_SDA37,43

IIC_EEPROM_SCL361

2X5R10V

0.1UFC95

IIC_EEPROM_SCL36

1

2 DNPDNPDNPR309

1

25%1/10W

0R329

2

1C940.1UF10VX5R

IIC_EEPROM_SDA36

2 1R3280

1/10W

5% PS_SDA_MAIN9

25

123456

1617

1415

1213

1011

87

2322

18

21

1920

24

9

U65 QFN_24

PCA9548ARGER

2

1 C920.1UF10VX5R

36IIC_SDA_MAIN

36IIC_SCL_MAIN

54

7

63

2

1 8

PCA9517SOIC_8

U88

FPGA_DONE 3

2

1 R544.7K1/10W5%

1

2 5%1/10W4.7KR53

IIC_SCL_MAIN 3636IIC_SDA_MAIN

54

7

63

2

1 8

PCA9517SOIC_8

U87

2

1 C900.1UF10VX5R

FMC_LPC_IIC_SCL28

1

2 5%1/10W4.7KR39

IIC_MUX_RESET_B 38

1

2 5%1/10W4.7KR41

2

1 R444.7K1/10W5%

2

1 R308DNPDNPDNP

1

2 DNPDNPDNPR307 1

2 5%1/10W4.7KR49

2

1 R504.7K1/10W5%

1

2 5%1/10W4.7KR55

2

1 R564.7K1/10W5%

1

2 5%1/10W4.7KR57

2

1 R584.7K1/10W5% 2

1 R594.7K1/10W5%

1

2 5%1/10W4.7KR64

2

1 R634.7K1/10W5%

2

1 R404.7K1/10W5%

2

1 R306DNPDNPDNP

2

1R464.7K

1/10W5%

1

2X5R10V

0.1UFC91

1

25%1/10W4.7KR45

125%

1/10W 0

R327

1

25%1/10W4.7KR48

1

2X5R10V

0.1UFC93

2

1R474.7K1/10W

5%

4 IIC_SDA_MAIN_LS

4 IIC_SCL_MAIN_LS IIC_SCL_MAIN 36

IIC_SDA_MAIN 36

65

123

7

84

U9 TSSOP8_65P440X300MM

M24C08-WDW6TP

2

1 R524.7K1/10W5%

1

2 5%1/10W4.7KR51

37,43 RTC_SI5324_SCL

IIC_EEPROM_SDA36

Page 37: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GNDGND

GND

GND

P10

GND P17

P00P01P02P03P04P05P06P07

P11P12P13P14P15P16

VCCP

VCCISDASCLADDR

RESET_BINT_B

GND

SDASCL

VCC

CLKOUTCLKOE

INT

ZC706 EVALUATION PLATFORMPCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTIIC Real Time Clock, Port Expander

IIC Real Time Clock, Port Expander

BF37 58

2-14-2014_15:01

04

2.0

9

76

4

53

10

U26 RTC8564JE_VSOJ_20

RTC8564JE_VSOJ_20

13

12 20

4567891011

141516171819

24

2232221

31

U16 TCA6416APWR

TCA6416APWR

21R512

200

1/10W

1%

1 21%1/10W

200

R513

PL_PWR_ON 49

FMC_VADJ_ON_B 49

PL_PWR_ON_R

1

2 5%1/10W4.7KR501

1

2B3 ML621S_DN

ML621S_DN

VCC3V3_PS

VCC3V3_PS

VCC3V3_PS

VCC3V3_PS

VCC3V3_PS

XADC_MUX_ADDR0 46

XADC_MUX_ADDR2 46

XADC_MUX_ADDR1 46

FMC_HPC_PG_M2C 2524,26FMC_HPC_PRSNT_M2C_B 28FMC_LPC_PRSNT_M2C_B

2

1 R654.7K1/10W5%

2

1C960.1UF

10VX5R

NC

PORT_EXPANDER_DDR3_SDA23,3623,36 PORT_EXPANDER_DDR3_SCL

IIC_PMOD_7 37

IIC_PMOD_6 37

IIC_PMOD_4 37IIC_PMOD_037

37 IIC_PMOD_1

IIC_PMOD_237

37 IIC_PMOD_3

37IIC_PMOD_5

36,43 RTC_SI5324_SCL

1 2

3

5 6

7 8

9 10

4

1211

J57

HDR_2X6

1 2

400MW30VBAT54T1G

D6

2

1

X7R25V0.01UFC350

21D4

BAT54T1G30V

400MW

1J60

YELLOW

2

1 R27010.0K1/10W1%

4 IIC_RTC_IRQ_1_B

RTC_SI5324_SDA36,43

VADJ

2

1R3300

1/10W5%

2

1 R310DNPDNPDNP

37IIC_PMOD_7 37IIC_PMOD_6IIC_PMOD_5 37

37IIC_PMOD_4IIC_PMOD_3 37

37IIC_PMOD_2

37IIC_PMOD_0IIC_PMOD_1 37

1

2X5R10V

0.1UFC97

21

D5

BAT54T1G

30V

400MW

FMC_VADJ_ON_R_B

Page 38: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

VCC3V3

P3

P1

P4

P2

Pushbutton

GND

VCC3V3

GNDGND

VCC3V3

GND

VCC3V3

GND

VCC3V3

GND

GND

P3

P1

P4

P2

Pushbutton

GND

GNDGND

P3

P1

P4

P2

Pushbutton

GNDGND

GNDGND

SC70_6

DIR

VCCB

B

VCCA

GND

A

GND GND

P3

P1

P4

P2

Pushbutton

P3

P1

P4

P2

Pushbutton

GND

GNDVCC3V3

OE

VCCBB1B2

A1A2GND

VCCA

OE

VCCBB1B2

A1A2GND

VCCA

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

GPIO, Level Shifters

GPIO, Level Shifters

BF

2-14-2014_15:01

5838

2.0

04

7 GPIO_LED_0

2

1 R5161.00K1/16W1%

6 PL_CPU_RESET

VCC1V5_PL

VCC1V5_PL

VCC3V3_PS

NC

3

245

187

6

TXS0102

TBD13U89

6

781

542

3

U25 TBD13

TXS0102VCC3V3

VCCP1V8 GPIO_LED_LEFT4 GPIO_LED_CENTER6 GPIO_LED_RIGHT4

5 GPIO_SW_RIGHT7 GPIO_SW_CENTER4 GPIO_SW_LEFT

GPIO_DIP_SW044 GPIO_DIP_SW1

1234 5

678

SW12

SDA04H1SBD

NC 36IIC_MUX_RESET_BNC9 IIC_MUX_RESET_B_LS

VADJ

1

2 5%1/10W4.7KR68 2

1 R674.7K1/10W5%

VADJ

2

4

1

3

TL3301EF100QG

SW7

3

1

4

2TL3301EF100QG

SW10

HDMI_SPDIF_OUT_LS4 32HDMI_SPDIF_OUT

2

1 R734.7K1/10W5%

FPGA_PROG_B3

5

6

4

1

2

3

U57

SN74AVC1T45

1

2

C1010.1UF25VX5R

2

1

X5R25V0.1UFC100

VADJ

2

1 R664.7K1/10W5%

2

4

1

3

TL3301EF100QG

SW82

1 R694.7K1/10W5%

VADJ

2

1C1030.1UF

10VX5R

1

2X5R10V

0.1UFC102

1

2 5%1/10W4.7KR71

2

1 R704.7K1/10W5%

4 GPIO_DIP_SW24 GPIO_DIP_SW3

3

1

4

2

SW9

TL3301EF100QG

1

2 5%1/10W4.7KR72

1

32

Q7

NDS331N460MW

1

21%1/10W261

R390

12

LED-GRN-SMT

DS8

23

1

460MWNDS331N

Q8

2

1R391261

1/10W1%

21

DS9

LED-GRN-SMT

1

32

Q9

NDS331N460MW

1

21%1/10W261

R392

12

LED-GRN-SMT

DS10

VADJ

1

2X5R10V

0.1UFC99

2

1C980.1UF10VX5R

PWRCTL1_FMC_PG_C2M24,25,28,493 PWRCTL1_FMC_PG_C2M_LSNC

2

4

1

3

SW13

TL3301EF100QG

21

DS35

LED-GRN-SMT

2

1R544261

1/10W1%

23

1

460MWNDS331N

Q30

Page 39: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

VCC3V3

GND

GND

GNDVCC3V3GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCBB1B2B3B4

B6B7

GND

A3

A8OE

A4A5

A7A6

B5

A1A2

B8

VCCA

NC

NC

NC

ZC706 EVALUATION PLATFORMPCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

ARM PJTAG Header

ARM PJTAG Header, PMOD1

ARM PJTAG Header, PMOD1

NC

BF39 58

2-14-2014_15:01

04

2.0

PMOD1_339

39 PMOD1_2

PMOD1_139

39 PMOD1_0

PL_PJTAG_PS_SRST_R15 PL_PJTAG_PS_SRST_B

2

12

31

1578

65

109

4

11

1314

1617182019

TXS0108E

TSSOP_20U40

VADJ

VADJ

4 PL_PJTAG_TDO

4 PL_PJTAG_TCK

4 PL_PJTAG_TMS

4 PL_PJTAG_TDI

PL_RTCK_UNUSED

7

2

6

4

8

1

3

5

9

11

13

15

17

19

10

12

14

16

18

20

J64

TST-110-01-G-D

1

2

J15

PL_NTRST_UNUSED

1

2 5%1/10W4.7KR78

2

1 R774.7K1/10W5% 2

1 R754.7K1/10W5%

1

2 5%1/10W4.7KR741

2 5%1/10W4.7KR76

PL_DBGRQ_UNUSED

PL_DGBACK_UNUSED

2

1 R794.7K1/10W5%

1

2 5%1/10W4.7KR80

2

1 R814.7K1/10W5%

VADJ

1 2

3

5 6

7 8

9 10

4

1211

J58

HDR_2X6

2

1C1050.1UF

10VX5R

1

2X5R10V

0.1UFC104

VADJ

21R331

0 1/10W

5%

PMOD1_4 39

39PMOD1_5

PMOD1_6 39

39PMOD1_7

PMOD1_1_LS44 PMOD1_0_LS

4 PMOD1_2_LSPMOD1_3_LS4 PMOD1_3 39

39PMOD1_2PMOD1_1 39

39PMOD1_0

3 PMOD1_5_LSPMOD1_4_LS3

PMOD1_6_LS33 PMOD1_7_LS 39PMOD1_7

PMOD1_6 3939PMOD1_5

PMOD1_4 39

Page 40: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

GND

GND

GND

REGIN

CN

R_G

ND

RT

S_O

_B

DT

R_O

_B

DC

D_I

_B

NC

1

NC10

NC

2

NC

3

NC4

GPIO3

GPIO2

GPIO1

GPIO0

NC9

RS

T_B

RX

D_I

TX

D_O

SU

SP

EN

D

SU

SP

EN

D_B

DS

R_I

_B

VB

US

VDD

CT

R_G

ND

CT

S_I

_B

D+

D-

GND1

VIO

RI_I_B

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

USB Bus-Powered

USB UART

USB UART

1

04

2.0

40 58

2-14-2014_15:01

BF

2

1 R50801/10W5%

VCCP1V8

USB_UART_D_N

USB_UART_D_P

NC

NC

9USB_UART_TX

9USB_UART_RX

7

29

23

27

28

10

21

13

14

15

16

17

18

19

20

9

24

25

12

11

26

8

6

30

22

3

4

2

5

1

U52 QFN_28

CP2103GM_MLP-28

USB_UART_SHIELD

USB_UART_GND40

40

USB_UART_VBUS

1

2

C1080.1UF25VX5R

12

L4

FERRITE-600

2

1

1UF

C318

X5R25V

2

1

X5R25V1UF

C317

1

2

C1090.1UF25VX5R

12

L5

FERRITE-600

1

2

C1060.1UF25VX5R

5

9

1

2

3

678

4

J21

CONN_USB_MINI_B_TH

USB_UART_GND40

USB_UART_VBUS40

1

2 5%1/10W4.7KR82

1

2 3

4

X3

SP0503BAHTG

12V

200MW

1

2

C1070.1UF25VX5R

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

CP2103_VBUS

NC

NC

Page 41: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

VCC3V3

GND

GND

GND

VCC3V3

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND12

GND1GND2GND3GND4GND5GND6GND7GND8GND9GND10

TD_NTD_P

VCCTVCCR

RD_PRD_N

LOS

VEET_3VEET_2

VEER_3

VEER_1VEER_2

VEET_1

RS0RS1

MOD_ABS

SCLSDA

TX_DISABLETX_FAULT

GND11

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

2-3: LOW BW TX2-3: LOW BW RX1-2: FULL BW RX

SFP Enable

SFP+ Connector and Cage

1-2: FULL BW TX

SFP+ Connector and Cage

ZC706 EVALUATION PLATFORM

04

41 58

2-14-2014_15:01

BF

2.0

CG1

74754-0101

1 2

J17

32

21222324252627282930

1918

1615

1312

8

2017

14

1011

1

79

6

54

32

31

P2

74441-0010

34,36USRCLK_SFP_SCLUSRCLK_SFP_SDA34,36

3SFP_TX_DISABLE

8SFP_TX_N8SFP_TX_P

8SFP_RX_PSFP_RX_N 8

2

1 R884.7K1/10W5%

1

2 5%1/10W4.7KR87

1

2 5%1/10W4.7KR86

2

1 C19922UF25VX5R

2

1 C19822UF25VX5R

1 2

L7

4.7UH

3.0A

20%

21

20%

3.0A

4.7UHL6

1

2

C1350.1UF25VX5R

2

1

X5R25V0.1UFC134

23

1

460MWNDS331N

Q12

1

J25

HDR_1X1

3

2

1

HDR_1X3

J56

1

2

3

J55

HDR_1X3

2

1 R854.7K1/10W5%2

1 R844.7K1/10W5%

1

2 5%1/10W4.7KR83

1

HDR_1X1

J24

1

J23

HDR_1X1

SFP_RS1

SFP_VCCT

SFP_LOS

SFP_TX_FAULT

SFP_RS0

SFP_MOD_DETECT

SFP_VCCR

SFP_TX_DISABLE_TRANS

Page 42: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

GND

GND GND

RESERVED

RESERVED

GND

+3.3V

+3.3V

+12V

RESERVED

GND

GND

GND

+12V

SMCLK

SMDAT

+3.3Vaux

WAKE#

KEY

GND

GND

GND

GND

GND

GND

+12V

GND

PETp1

PETn1

PETp2

PETn2

PETp3

PETn3

PRSNT#2

PRSNT#1

+12V

GND

+12V

GND

JTAG1/TRST#

JTAG2/TCK

JTAG3/TDI

JTAG4/TDO

JTAG5/TMS+3.3V

PRSNT#2

PERST

KEY

REFCLK+

REFCLK-

GND

PETp0

PETn0

PERp0

PERn0

PERp1

PERn1

PERp2

PERn2

PERp3

PERn3

GND

GND

RESERVED

GND

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

PCIe x8 Card edge

PCIe x4 Card edge

BF

2-14-2014_15:01

5842

2.0

04

A1

A10

A11

A14

A15

A16

A17

A19

A2

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A3

A30

A31

A32

A4

A5

A6

A7

A8

A9

B10

B11

B15

B16

B17

B18

B19

B2

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B3

B30

B31

B32

B5

B6

B7

B8

B9

B1

B4

B14

A18

B12

B13

A12

A13

P4

PCIE_4LANE_EDGE

PCIE_PRSNT_B 421 2

3 4

J19

HDR_2X2

1 2DNP

DNP

DNP

R313 2

1 R312DNPDNPDNP

1

2 DNPDNPDNPR311

21

X7R

25V

0.01UF

C352

1 2

C439

0.22UF

16V

X5R

21R160

15

1/10W

1%

21

X5R

16V

0.22UF

C446

1 2

C445

0.22UF

16V

X5R

21

X5R

16V

0.22UF

C444

1 2

C443

0.22UF

16V

X5R

21

X5R

16V

0.22UF

C442

1 2

C441

0.22UF

16V

X5R

21

X5R

16V

0.22UF

C440

1 2

C353

0.01UF

25V

X7R

PCIE_PRSNT_X142

42 PCIE_PRSNT_X4

PCIE_WAKE_B_RPCIE_WAKE_B47

8PCIE_CLK_QO_N

8PCIE_CLK_QO_P

PCIE_CLK_QO_C_N

PCIE_TX0_C_N

PCIE_TX0_C_P

NC

PCIE_RX3_N8

8 PCIE_RX3_P

PCIE_RX2_N8

PCIE_RX2_P8

8 PCIE_RX1_N

8 PCIE_RX1_P

PCIE_RX0_N8

8 PCIE_RX0_P

47PCIE_PERST

PCIE_TX0_P 8

PCIE_TX0_N 8

PCIE_TX1_P 8

PCIE_TX1_N 8

8PCIE_TX2_P

8PCIE_TX2_N

PCIE_TX3_P 8

8PCIE_TX3_N

42 PCIE_PRSNT_X1

NC

42 PCIE_PRSNT_X4

NC

NC

PCIE_TX2_C_N

PCIE_TX2_C_P

PCIE_TX3_C_P

PCIE_TX3_C_N

PCIE_TX1_C_P

PCIE_TX1_C_N

42PCIE_PRSNT_B

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

PCIE_CLK_QO_C_P

Page 43: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

GND

GND

GND

XA XB

GND1 GND2

GNDGND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

A1A2_SS

CKOUT2_NCKOUT2_P

CMODE

CS_CAGND1GND2

GNDPAD

LOL

NC3NC4NC5

SCLSDA_SDO

VDD3

RST_B

NC1

INT_C1BC2B

VDD1

XAXB

NC2VDD2

RATE0

CKIN2_PCKIN2_N

RATE1

CKIN1_PCKIN1_N

GND3GND4

A0

SDI

CKOUT1_PCKOUT1_N

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANT

5324 Clock Recovery

5324 Clock Recovery

ZC706 EVALUATION PLATFORM

2.0

04

BF43 58

2-14-2014_15:01

2526

3435

36

21831

37

18

143033

2223

32

1

2

34

5

67

910

11

1213

15

1617

1920

24

27

2829

U60 QFN36_6X6MM

SI5324C-C-GM

SI5324_XTAL_XA

SI5324_INT_ALM47

8SI5324_OUT_C_P

SI5324_OUT_C_N 8

3 REC_CLOCK_C_N

REC_CLOCK_C_P3

1 2

C141

0.1UF

25V

X5R

2

1 C58510UF16VX5R

2

1

X5R25V0.1UFC1401

2

C1390.1UF25VX5R

21

X5R

25V

0.1UF

C138

2 4

1 3

X4

114.285MHZ

20PPM

1

2

C481330UF10VTANT

SI5324_VCC

1

2

C3201UF25VX5R

1 2

C137

0.1UF

25V

X5R

2

1 R2511001/10W1%

21

X5R

25V

0.1UF

C136

1 2

L21

FERRITE-220

SI5324_VCC

1

25%1/10W4.7KR89

SI5324_XTAL_XB

SI5324_RST47

RTC_SI5324_SCL 36,37

SI5324_OUT_NREC_CLOCK_NREC_CLOCK_P

RTC_SI5324_SDA 36,37

NCNCNCNCNC

NCNC

NC

SI5324_OUT_P

NCNC

NCNCNCNC

Page 44: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

GND

GND

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

SIG

GND1

GND4

GND3

GND2

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

Place near FMC connectors

SMA and Testpoints

SMA and Testpoints

04

2.0

44 58

2-14-2014_15:01

BF

USER_SMA_CLOCK_N3

USER_SMA_CLOCK_P3

VADJ

1

BLACK

J29

1J26

BLACK

1

BLACK

J27

1J28

BLACK

1J59

RED

1

2

5

4

3

J36

32K10K-400L5

1

2

5

4

3

J35

32K10K-400L5

3

4

5

2

1

32K10K-400L5

J34

3

4

5

2

1

32K10K-400L5

J33

1

2

5

4

3

J32

32K10K-400L5

3

4

5

2

1

32K10K-400L5

J31

21

X5R

25V

0.1UF

C145

1 2

C144

0.1UF

25V

X5R

21

X5R

25V

0.1UF

C143

1 2

C142

0.1UF

25V

X5R

8SMA_MGT_REFCLK_P

8SMA_MGT_REFCLK_N

SMA_MGT_REFCLK_C_P

8SMA_MGT_TX_N

8SMA_MGT_TX_P

8SMA_MGT_RX_P

SMA_MGT_REFCLK_C_N

SMA_MGT_RX_C_P

SMA_MGT_RX_C_N

8SMA_MGT_RX_N

1

2

5

4

3

J68

32K10K-400L5

3

4

5

2

1

32K10K-400L5

J67

Page 45: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND

GNDGND

GND

GND

GND

GND

GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

CHAN.1

CHAN.2

CHAN.3

CONTROLLER #1

RsenseIR drop

CHAN.4

SCHEM, ROHS COMPLIANT PCB P/N: 1280681SCH P/N: 0381513ZC706 EVALUATION PLATFORM

CHAN.5

XADC I/F Monitoring Page 1

XADC I/F Monitoring Page 1

XADC I/F MONITORING CIRCUIT PAGE 1VCCINT 0A-16A => CS = 0V - 0.8V G=10, Rg=11KVCCINT 0A-8A => CS = 0V - 0.8V G=20, Rg=5.23K

VCCAUX 0A-4A => CS = 0V - 1VG=50, Rg=2.05K

VCC1V5_PL 0A-2A => CS = 0V - 1VG=100, Rg=1.00K

VADJ_FPGA 0A-2A => CS = 0V - 1VG=100, Rg=1.00K

VCC3v3_FPGA 0A-2A => CS = 0V - 1VG=100, Rg=1.0K

2-14-2014_15:01

5845 BF

2.0

04

1 20.5%

1/16W

1.00K

R429

21R333

1.00K

1/16W

0.5%

1 20.5%

1/16W

1.00K

R332

21R334

2.05K

1/10W

1%

21R517

5.76K

1/10W

1%

21R411

5.23K

1/16W

1%

1

2

J69

1 8

72

3 6

54

U69 MSOP_8

INA333AIDGKR

54 VCC3V3_FPGA_XADC_SENSE_P

VADJ_FPGA_XADC_SENSE_N53

VCC5V0

53 VADJ_FPGA_XADC_SENSE_P

46VCC1V5_PL_XADC_CS_P

1 8

72

3 6

54

U68 MSOP_8

INA333AIDGKR

21R195

9.76K

1/10W

1%

1 21%

1/10W

9.76K

R196

21

1%

1/10W

100

R239

1 8

72

3 6

54

U70 MSOP_8

INA333AIDGKR

1

2

C1190.1UF25VX5R

1

2

C1180.1UF25VX5R

VCC5V0

VCC5V0

21

1%

1/10W

100

R241

VCC5V0

1

2

C1170.1UF25VX5R

1

2

C1160.1UF25VX5R

1 8

72

3 6

54

U67 MSOP_8

INA333AIDGKR

1

2

C1150.1UF25VX5R

1

2

C1140.1UF25VX5R

1

2

C1130.1UF25VX5R

21

1%

1/10W

100

R240

1

2

C1120.1UF25VX5R

21

1%1/10W

100

R238

46VADJ_FPGA_XADC_CS_P

46VCCAUX_XADC_CS_N

46VCCINT_XADC_CS_N

VCCAUX_XADC_CS_P 46

VCCINT_XADC_CS_P 46VCCINT_XADC_SENSE_P50

VCCINT_XADC_SENSE_N50

VCCAUX_XADC_SENSE_P51

VCCAUX_XADC_SENSE_N51

52 VCC1V5_PL_XADC_SENSE_N

52 VCC1V5_PL_XADC_SENSE_P

46VCC1V5_PL_XADC_CS_N

46VADJ_FPGA_XADC_CS_N

21R197

9.76K

1/10W

1%

1 21%1/10W

9.76K

R198

46VCC3V3_FPGA_XADC_CS_N

54 VCC3V3_FPGA_XADC_SENSE_N

2

1

X5R25V0.1UFC591

2

1

X5R25V0.1UFC590

4 5

63

2 7

81INA333AIDGKR

MSOP_8U97

1 2

R420

100

1/10W

1%

1 21%

1/10W

9.76K

R416

46VCC3V3_FPGA_XADC_CS_P

VCC5V0

Page 46: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

21

GND

1

2

GND

21

GND

GND

GND

VDDDBNC1S8BS7BS6BS5BS4BS3BS2BS1BGND

NC2NC3 A2

A1A0ENS1AS2AS3AS4AS5AS6A

DAVSSS8AS7A

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

TO XADC MUX

TO XADC MUX

TO XADC MUX

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

XADC I/F Monitoring Page 3

XADC I/F Monitoring Page 2

XADC I/F MONITORING CIRCUIT PAGE 2

VCC1V5_PL 1.50V SCALED TO 0.75V

VADJ_FPGA 2.5V SCALED TO 0.625V

VCC3V3 3.3V SCALED TO 0.825V

04

2.0

46 58

2-14-2014_15:01

BF

1

2

C47610PF50VNP0

1

2 1%1/10W3.01KR170

2

1 R33.01K1/10W1%

1

2 1%1/16W1.00KR373

2

1 R3651.00K1/16W1%

46 VADJ_FPGA_SENSE_N

46VCC3V3_FPGA_XADC_P

46 VCC1V5_PL_XADC_P

NC

37XADC_MUX_ADDR2 37XADC_MUX_ADDR1 37XADC_MUX_ADDR0

VCC3V3

XADC_AD1_R_N7

XADC_AD1_R_P7

XADC_MUX0_SENSE_N46

XADC_MUX0_SENSE_P 461234567891011121413 15

161718192021222324

28272625

U6TSSOP_28

ADG707BRUZ_TSSOP_28

1%

1/10W

100

R250

C1310.1UF25VX5R

R249

100

1/10W

1%

21Z12

0201_SHORT

2

1 R3641.00K1/16W1%

21Z11

0201_SHORT

2

1 R3631.00K1/16W1%

21Z10

0201_SHORT

VADJ_FPGA_SENSE_P53

VCC3V3_FPGA_SENSE_P54

VCC3V3_FPGA_SENSE_N46

46 VCC3V3_FPGA_XADC_P

46 VADJ_FPGA_XADC_P

46 VCC1V5_PL_SENSE_NNCNC

VCCAUX_XADC_CS_N45 VCCINT_XADC_CS_N45

VCCAUX_XADC_CS_P 45VCCINT_XADC_CS_P 45

49,52 VCC1V5_PL_SENSE_P

46XADC_MUX0_SENSE_P

46XADC_MUX0_SENSE_N

VCC3V3

46 VCC1V5_PL_SENSE_NVCC1V5_PL_XADC_CS_N45

VADJ_FPGA_SENSE_N46

VADJ_FPGA_XADC_CS_N45

VADJ_FPGA_XADC_CS_P 45VADJ_FPGA_XADC_P 46VCC1V5_PL_XADC_CS_P 4546VCC1V5_PL_XADC_P

46 VCC3V3_FPGA_SENSE_N45 VCC3V3_FPGA_XADC_CS_N 45VCC3V3_FPGA_XADC_CS_P

Page 47: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND GND

GND GND

VCC3V3

SN74AVC4T245

QFN-RSV-16

1A1

1A2

1B1

1B2

1DIR

2A1

2A2

2B1

2B2

2DIR

VCCA VCCB

1OE_B

2OE_B

GND GND

GND

GND

VCC3V3

GND

SC70_6

DIR

VCCB

B

VCCA

GND

A

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

Level Shifters

Level Shifters

04

2.0

47 58

2-14-2014_15:01

BF

4 SI5324_RST_LS

43SI5324_INT_ALM

4 PCIE_PERST_LS

PCIE_WAKE_B_LS4

SI5324_INT_ALM_LS4

5

6

4

1

2

3

U91

SN74AVC1T45

1

2

C5950.1UF25VX5R

2

1

X5R25V0.1UFC594

VADJ

VADJ

6

7

15

14

4

8

9

13

12

5

10 11

3 2

1

16

U90

2

1

X5R25V0.1UFC5931

2

C592

0.1UF25VX5R

PCIE_PERST 42

43SI5324_RST

PCIE_WAKE_B 42

NC NC

Page 48: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

B CB

CG3PSGCG2CG1

GND

GND

COM

N/C

12V

12V

N/C

COM

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Keyed Fan Header

Keyed PMBUS Conn.

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

Power Connectors

Power Connectors

04

2.0

48 58

2-14-2014_15:01

BF

12

D2

MM3Z2V7B

2.7V

460MW

V33D_CTL1

VADJ

1 2

3

5 6

7 8

9 10

4

J4

HDR_BOX_2X5

2

1 R3772.00K1/16W1%2

1

1%1/16W2.00KR3761

2 1%1/16W2.00KR375

2

1 R3742.00K1/16W1%

VCC12_P

2

1 R1712.15K1/10W1%

21

DS22

LED-GRN-SMT

1

4

3

6

2

5

J22

39-30-10601

2 1%1/10W10.0KR279

21R278

10.0K

1/10W

1%

1 8

5367

U18

50MOHM1

32

4

65

SW1

1201M2S3AQE2

1

2 1%1/16W1.00KR369

INPUT_GNDINPUT_GND

1

2

C3191UF25VX5R

1

3

42

Q1

NDT3055L1.3W

1

2

3

J61

22_11_2032

21

D1

DL4148

100V

460MW

2

1 R1904.75K1/10W1%

VCC12_P

1

2

C568330UF25VELEC

INPUT_GND

49PMBUS_ALERT

PMBUS_CLK36,49 36,49PMBUS_DATA

49 PMBUS_CTRL

NC

NC

NC

NC

NC

SM_FAN_PWM3

SM_FAN_TACH 3

VCC12_P_IN

NCNC

NC

NC

Page 49: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GNDGNDGND

GND

GND

GND

GND

AGND

GND

GND

GND

250MA

GND

VINEN

VOUT NR

GNDTAB

GNDofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

GND

GND

THERM_PAD

AVSS1

NC1

NC2

NC3

NC4

V33FB

PMBUS_ADDR1

PMBUS_ADDR0

MON10

MON11

MON12

MON13

MON7

MON8

MON9

PWM2_GPI2

GPIO15

GPIO14

GPIO13

FPWM7_GPIO11

FPWM6_GPIO10

FPWM5_GPIO9

FPWM4_GPIO8

FPWM3_GPIO7

FPWM2_GPIO6

BPCAP

AVSS2

V33A

V33D

V33DIO2

DVSS3

PWM3_GPI3

PWM4_GPI4

TMS_GPIO19

TDI_GPIO19

TDO_GPIO19

TCK_GPIO19

GPIO18

GPIO17

PMBUS_DATA

GPIO4

GPIO3

GPIO2

TRCK

DVSS1

V33DIO1

MON6

MON5

MON4

MON3

MON2

MON1

RESET_B

GPIO1

GPIO16

TRST_B

FPWM1_GPIO5

FPWM8_GPIO12

DVSS2

PMBUS_CLK

PMBUSALERT_B

PMBUS_CTRL

PWM1_GPI1

AVSS3

GND

GND GND

GND

GND

GND

GND

AGND

AGND

AGND

931 1%

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

close to the

SENSE_P pin

Tap into GND

close to the

SENSE_P pin

RAIL ENABLES

Tap into GND

MARGIN TRIM

VOLTAGE SENSE

CURRENT SENSE FILTERSVOLTAGE SENSE FILTERS

CURRENT SENSE

PLACE CLOSE TO PINS44,45

MARGIN C1's

MARGIN R4's

POWER CONTROLLER 1

POWER CONTROLLER 1

PCB P/N: 1280681SCH P/N: 0381513

PMBus Addr 101

BF

2-14-2014_15:01

5849

2.0

04

1 2

R168

21R182

2.43K

1/10W

1%

2

1

X7R50V2200PFC158

2

1

X7R50V2200PFC1591

2

C1663300PF25VX7R

1

2

C1653300PF25VX7R

21

R482

10.0K

21

R483

10.0K

2

1

R484

DNP

55VCC3V3_PS_EN_B

V33D_CTL1

55

VCC1V5_PS_EN_B

V33D_CTL1

V33D_CTL1

55VCCPAUX_EN_B

49,54 VCC3V3_FPGA_SCALED_P

VCC3V3_FPGA_SCALED_P49,54

VADJ_FPGA_SCALED_P49,53

49,53 VADJ_FPGA_SCALED_P

V33D_CTL1

1

2

0.01UF

C366

FMC_VADJ_ON_B 37,49

21R522

1.00K

1/16W

1%

1 21%

1/16W

1.00K

R521

1

2

C1572200PF50VX7R

54 VCC3V3_FPGA_TRIM

NC

53 VADJ_FPGA_TRIM

VCC1V5_PL_TRIM52

21R379

1.10K

1/10W

1% 21

R205

1.96K

1/10W

1%

VCCAUX_TRIM51

21R204

1.58K

1/10W

1%

65

49

51

53

55

57

58

60

61

50

52

54

56

59

62

63

32

30

29

25

23

22

21

20

19

18

47

48

46

45

44

43

42

41

39

38

37

36

35

34

16

14

13

12

10

8

7

6

5

4

3

2

1

9

11

33

40

17

24

26

15

27

28

31

64U48

VQFN_64

UCD90120ARGC_VQFN64

PL_PWR_ON

37,49

PL_PWR_ON37,49

37,49 FMC_VADJ_ON_B

1 2

J18

PMBUS_ALERT

48

48

PMBUS_CTRL

53

VADJ_FPGA_EN

VCC3V3_FPGA_EN

54

CTRL1_PWRGOOD

50LOW_PWR_SEL

VADJ_SEL1 53

53VADJ_SEL0

V33D_CTL1

1

2

10.0K

R481

VCCAUX_IO_EN

57

NC

2

1

R290

10.0K

VCCAUX_EN51

2

1

R284

10.0K

NC

NC

NC

50 VCCINT_TRIM

49,51 VCCAUX_SENSE_P

VCCAUX_SENSE_P49,51

1

2

10.0K

R289

321 4 5

6U20

SOT223_6TPS79433DCQR

VCC5V0

2

1 R28710.0K1/10W1%

1

2

C1550.1UF

25VX5R

2

1

C362

0.01UF

2

1

C357

0.01UF

VCC1V5_PL_SENSE_P46,49,52

VCCINT_SENSE_P49,50

2

1

C356

0.01UF

21R409

41.2K

1/10W

1%

1

2

C4781000PF50VX7R

2

1

C361

0.01UF

2

1

C360

0.01UF

2

1 C3590.01UF25VX7R

2

1

R288

10.0K

1

2

C1640.1UF25VX5R

1

2X5R25V1UFC324

V33D_CTL1

1

2

L22FERRITE-2202A

2

1 C3764.7UF6.3VX5R

1

2

C1630.1UF25VX5R

1

2

C1620.1UF25VX5R

1

2

C1610.1UF25VX5R

2

1 C3754.7UF6.3VX5R

1

2

C1600.1UF25VX5R

1

2

C3580.01UF25VX7R

1

2X5R6.3V4.7UFC374

2

1R28610.0K1/10W

1%

2

1

R285

10.0K

2

1

C355

0.01UF

2

1

C354

0.01UF

VCC3V3

1

2 1%1/10W10.0KR282

VCC3V3

2

1 R3932611/10W

1

32

Q14

NDS331N

21

DS24

LED-GRN-SMT

21R191

90.9K

1/10W

1%

V33A_CTL1

36,48 PMBUS_CLK

36,48 PMBUS_DATA

46,49,52 VCC1V5_PL_SENSE_P

49,50 VCCINT_SENSE_P

NC

NC

NC

52 VCC1V5_PL_EN

50 VCCINT_EN

V33D_CTL1

1

21%1/10W10.0K

R291

21R371

1.00K

1/16W1%

1

2

0.01UF

C3641

2

0.01UF

C365

NC

55 VCCPINT_EN_B

1

2

10.0K

R485

1 21%

1/16W

1.00K

R509

2

1R50210.0K1/10W

1% 21

J66

V33D_CTL1

NC

NC

NC

NC

21R520

1.00K

1/16W

1%

1 21%

1/16W

1.00K

R523

21R524

1.00K

1/16W

1%

52VCC1V5_PL_CS_PVCCAUX_CS_P 51

50VCCINT_CS_PVCC3V3_FPGA_CS_P 54VADJ_FPGA_CS_P 53

V33D_CTL1

PWRCTL1_FMC_PG_C2M

24,25,28,38

Page 50: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

5V

AGND1

FREQ_SEL

ILIM

INH

NC1NC2NC3NC4NC5

PGND1

PGND10PGND11PGND12PGND13PGND14PGND15PGND16PGND17PGND18PGND19

PGND2

PGND20PGND21PGND22PGND23

PGND3PGND4PGND5PGND6PGND7PGND8PGND9

PH1PH2PH3PH4PH5PH6PH7PH8PH9

PWRGD_PU

SENSE+

SS_SEL

VADJ

VIN1VIN2

VOUT1

VOUT10VOUT11

VOUT2VOUT3VOUT4VOUT5VOUT6VOUT7VOUT8VOUT9

LMZ31520RLG

RLG_R_PB4QFN_N72

PWRGD

DNC1DNC2DNC3DNC4DNC5DNC6DNC7

PVIN1PVIN2PVIN3PVIN4PVIN5

GND

GNDGND

GNDGND

GND GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND GND

GND

GND

R2R1

S1 S2

GND

NOCOMNC

VCC

GNDSEL

GND

GND

tuning0.9V Rset

See LMZ31520 datasheetpg. 20-21 for layout

See LMZ31520 datasheetpg. 20-21 for layoutguidelines for surrounding

LOW_PWR_SEL = HI = NO-TO-COM ON = 0.9V VCCINT

LOW_PWR_SEL = LOW = NC-TO-COM ON = 1.0V VCCINTPCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

TO CONTROLLER ONLY

VCCINT 1.0V

VCCINT 1.0V

(INTERNAL XADC FOR VCCINT)

VCCINT 1.0V 16A MAX

VCCINT 0A-16A => CS = 0V - 2.02VG=25.27, Rg=4.12K

CLOSE TO FPGA POWER PINREMOTE SENSE Z-SHORT PLACED

RON=12 OHMSLOW-POWER MODE SELECT

1.0V Rset

WIRE VCCINT_SENSE_P NET Z24=>U42.27 FIRST, THEN U42.27 TO CONTROLLER U48.1

(FCCM)

VCCINT ENABLEVCCINT_EN = LOW = VCCINT OFF

input/output capacitors

guidelines for PH copper island

1.0V Rset0.9V Rset tuning

-20% LIMIT

= 16A

VCCINT_VADJ

MARGIN R3

this short is internalrequired for LMZ31520 per TI power specialistNo external AGND-to-PGND short

BF

2-14-2014_15:01

5850

2.0

04

U42_AGND 50

21

R193

5.23K 1%

U42_ILIM

2

1 R342383K1/10W1%

49 VCCINT_SENSE_P

VCCINT_EN49

VCCINT_PWRGD50

VCCINT_PWRGD 50

1

2

C150.1UF25VX5R

49 LOW_PWR_SEL

143

5

26

U33SC70_6

TS5A63157

2

1 R2542.94K1/10W1% 2

1 R3162.21K1/10W1%

1

2

R964.7K

1/16W

VCCINT_VADJ

400KHZ_SELECTED

12

0201_SHORT

Z24

21

S1 S2R111

0.0053W1%

VCC12_P

VCCINT

U42_PH

21

R253

604 1%

PWRGD_R

2

1 R341499K1/10W1%

5V5

2

1

X5R10V0.47UFC566

1 2

FERRITE-78

L24

1

2

C20022UF25VX5R

1

2

C21047UF25VX5R

2

1

X5R25V47UFC2111

2

C21247UF25VX5R

1

2

C21447UF25VX5R

1

2

C21347UF25VX5R

2

1

X5R6.3V100UFC305

1 8

72

3 6

54

INA333U76

21R103

4.12K

1/10W

1%

VCCINT_R_SENSE_N

VCCINT_R_SENSE_P

45VCCINT_XADC_SENSE_P

45VCCINT_XADC_SENSE_N

49VCCINT_CS_P

VCC5V0

2

1 R3942611/10W

21

Z210201_SHORT

VCCINT

21

DS11

LED-GRN-SMT

1

2

C1670.1UF25V

1

2

C297100UF6.3VX5R

1

2

C298100UF6.3VX5R

1

2

C299100UF6.3VX5R

1

2

C300100UF6.3VX5R

1

2

C301100UF6.3VX5R

21

Z220201_SHORT

1

32

Q15

NDS331N

VCC3V3

2

1 R954.7K1/16W

21

D8

1N53

35B

RLG

3.9V

320M

A

2

1

X5R25V0.1UFC1681

2X5R25V10UFC269

2

1 C27010UF25VX5R

2

1 C20122UF25VX5R

1

2

C1690.1UF25VX5R

2

1

X5R6.3V100UFC306

2

1

X5R6.3V100UFC304

2

1

X5R6.3V100UFC303

2

1

X5R6.3V100UFC302

VCCINT_REG_OUT

12V_PWR_IN_LMZ_VCCINT

5V5

VCCF3V3

49 VCCINT_TRIM

61

9

7

6

16

2930313245

1

41464748495051626364

5

65677072

17333437383940

112223242526272871

18

14

3

13

215

10

6068

5253545556575859

19

481220213536

4243446669

U42

2

1 R11DNP1/10W1%2

1 R10DNP1/10W1%

U42_AGND 50

U42_NC7 NCU42_NC6 NC

NCU42_NC3

NCU42_NC2

NCU42_NC1

U42_NC5 NCU42_NC4 NC

Page 51: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

AGND1AGND2

ILIM

ISHARE

OCP_SEL

PGND1PGND2PGND3PGND4PGND5

PH1PH2PH3PH4PH5PH6PH7PH8PH9

PVIN1PVIN2PVIN3PVIN4PVIN5

RT_CLK

SENSE+

SS_TR

STSEL

SYNC_OUT

VADJ

VIN

VOUT1VOUT2VOUT3VOUT4VOUT5VOUT6

LMZ31710RVQ

RVQ_S_PB3QFN_N42

INH_UVLO

DNC1DNC2DNC3

PWRGD

GND2

1

GND GND

GND

R2R1

S1 S2

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND

(TR mode)

~= 7.0mSCss = 27nF

780ohm @ 25MHz

See LMZ31710 datasheet

placement close to packagebetween pins 26 and 23

Note 1:

Note 2:

See LMZ31710 datasheetpg. 26 for AGND connectionto PGND (GND)

pg. 26 for Vin and Vout CAP layoutsSee LMZ31710 datasheet

CLOSE TO FPGA POWER PINPLACE REMOTE SENSE Z-SHORT

MARGIN R3

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

VCC1V8/VCCAUX 1.8V

VCC1V8/VCCAUX 1.8V

VCCAUX 0A-4.2A => CS = 0V - 2.02VG=96.24, Rg=1.05K

TO CONTROLLER ONLY(INTERNAL XADC FOR VCCINT)

VCCAUX_EN = LOW = VCCAUX OFFVCCAUX ENABLE

See LMZ31710datasheet pg. 26 for PHcopper island layout

pg. 26 for Rset resistors

(limit=full)

(hiccup)

WIRE VCCAUX_SENSE_P NET Z47=>U98.27 FIRST, THEN U98.27 TO CONTROLLER U48.2

VCCAUX 1.8V SHARED 10A MAX

VCCAUX 1.8V SHARED 10A MAX

Note 3:

Note 4:

VCCAUX_VADJ

required for LMZ31710 per TI power specialistNo external AGND-to-PGND short

this short is internal

04

2.0

51 58

2-14-2014_15:01

BF

U98_AGND 51

U98_RT_CLK

VCCAUX_PWRGDU98_AGND 51

49 VCCAUX_SENSE_P

2

1 R4577151/10W1%

2

1 R438169K1/10W1%

VCCAUX_VADJ

1

2

C66010UF25VX5R

VCC12_P

21R456

3.16K

1/10W

1%

1

2

C65747UF25VX5R

4 5

63

2 7

81

INA333U102

21R455

1.05K

1/16W

1%

VCCAUX

VCCAUX

VCC5V0

VCC1V8

1

2

C6550.1UF25VX5R

21

Z460201_SHORT

21

Z450201_SHORT

1

2

C665100UF6.3VX5R

1

2

C664100UF6.3VX5R

1

2

C663100UF6.3VX5R

21

S1 S2R437

0.005

3W1%

1

2

C662100UF6.3VX5R

1

2

C661100UF6.3VX5R

45VCCAUX_XADC_SENSE_P45VCCAUX_XADC_SENSE_N

VCCAUX_TRIM49

VCCAUX_R_SENSE_P

VCCAUX_R_SENSE_N

49VCCAUX_CS_P

1

32

Q26

NDS331N

21

DS27

LED-GRN-SMT

1

2

R4354.7K1/16W

VCC3V3

2

1 R4602611/10W

R45827.4K1/10W

1%

VCC3V3

U98_PH

49 VCCAUX_EN

U98_CSS_22NF_7MS

2

1

X5R25V47UFC6591

2

C65847UF25VX5R

1

2

C6540.1UF25VX5R

1 2

L30

FERRITE-78

1

2

C65622UF25VX5R

12V_PWR_IN_LMZ_VCCAUX

U98_AGND51

21Z47

0201_SHORT

1

2

C6660.027UF10VX5R

223

5924

6

30

25

4

2021313233

101314151617181942

111123940

8

22

27

28

29

7

26

3

343536373841

U98

NCU98_NC8

NCU98_NC7

NCU98_NC6

NCU98_NC5_ISHARE

NCU98_NC4_ILIM

NCU98_NC3_OCP_SEL

NCU98_NC2_STSEL

NCU98_NC1_SYNC_OUT

Page 52: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

AGND

GND

GND GND

GND

AGND

GND

GND

GND GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

I2I1

V1 V2

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

BQFN_47

LMZ31506RUQAGND1

AGND2

AGND3

AG

ND

4

DNC1

DNC10

DNC11DNC12DNC13

DNC2DNC3

DNC4D

NC

5

DN

C6

DN

C7

DN

C8

DN

C9

INH_UVLO1INH_UVLO2

PGND1

PGND2

PG

ND

3

PH1PH2PH3PH4PH5

PH

6P

H7

PV

IN1

PV

IN2

PV

IN3

PWRGD

RT_CLK

SE

NS

E+

SS_TRSTSEL

VA

DJ

VIN

VO

UT

1

VOUT2VOUT3VOUT4VOUT5VOUT6VOUT7

VO

UT

8

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

MARGIN R3

XADC TAP

See TPS84621 datasheet

pg. 23 for PGND-AGND short

REMOTE SENSE Z-SHORT PLACED

CLOSE TO FPGA POWER PIN

VCC1V5_PL 1.50V 6A MAX

G=105.93, Rg=953VCC1V5_PL 0A-3.8A => CS = 0V - 2.01V

VCC1V5_PL 1.5V

VCC1V5_PL 1.5V

BF

2-14-2014_15:01

5852

2.0

04

1

2

34

45

3

23

303132

45

1516

18

19

20

22

89

36

37

38

1011121314

17

46

39

40

41

33

35

44

67

43

42

21

242526272829

47

U85

VCC1V5_PL

12V_PWR_IN_TPS84K_VCC1V5_PL

2

1

X5R25V47UFC2311

2

C23047UF25VX5R

1

2

C22947UF25VX5R

1

2

C22547UF25VX5R

2

1

X5R25V47UFC2271

2

C22647UF25VX5R

1

2

C22447UF25VX5R

2

1 R345200K1/10W1%RTCLK_VCC1V5_PL

VCC1V5_PL_REG_OUT

2

1

X5R25V0.1UFC176

I2I1

V1 V2

R136

0.0052W 1%

49 VCC1V5_PL_TRIM

21R184

3.74K

1/10W

1%

VCC1V5_PL_SENSE_P46,49

21R5

953

1/10W

1%

VCC1V5_PL

VCC1V5_PL_R_SENSE_P

VCC1V5_PL_PH_ISLAND

VCC1V5_PL_POWER_GOOD

4 5

63

2 7

81

INA333U78

1

2

C27210UF25VX5R

1

2

C20322UF25VX5R

21Z31

0201_SHORT

VCC1V5_PL

1

32

Q17

NDS331N

21

DS13

LED-GRN-SMT

VCC3V3

2

1 R29310.0K1/10W1%

21Z2

0603_SHORT

2

1 C1750.1UF25V

1

2

R984.7K1/16W

21

Z300201_SHORT

21

Z290201_SHORT

1 2

L26

FERRITE-781

2

C1740.1UF25VX5R

VCC12_P

VCC3V3

2

1 R3962611/10W

VCC5V0

VCC1V5_PL_CS_P 4945 VCC1V5_PL_XADC_SENSE_P

45 VCC1V5_PL_XADC_SENSE_N

49 VCC1V5_PL_EN

NC

NCNCNC

NC

NCNCNCNC

NC

NC

NC

NC

NC

VCC1V5_PL_R_SENSE_N

1

2X5R25V

C22847UF

2

1

1%1/10W953R4

Page 53: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

I0A

I1A

I2A

I2B

I1B

VCC

EB_B

S0

I3B

I0B

YB

EA_B

S1

I3A

YA

GND

GND

GND

GND

GND GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND

GND

GND

I2I1

V1 V2

GND

AGND

AGNDAGND GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

BQFN_47

LMZ31506RUQAGND1

AGND2

AGND3

AG

ND

4

DNC1

DNC10

DNC11DNC12DNC13

DNC2DNC3

DNC4D

NC

5

DN

C6

DN

C7

DN

C8

DN

C9

INH_UVLO1INH_UVLO2

PGND1

PGND2

PG

ND

3

PH1PH2PH3PH4PH5

PH

6P

H7

PV

IN1

PV

IN2

PV

IN3

PWRGD

RT_CLK

SE

NS

E+

SS_TRSTSEL

VA

DJ

VIN

VO

UT

1

VOUT2VOUT3VOUT4VOUT5VOUT6VOUT7

VO

UT

8

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

MARGIN R3

REMOTE SENSE Z-SHORT PLACED

CLOSE TO FPGA POWER PIN

XADC TAP

See TPS84621 datasheet

pg. 23 for PGND-AGND short

0 0 2.5V

0 1 1.8V

1 0 3.3V

1 1 NOT USED

VADJ 0A-1.1A => CS = 0V - 2.01VG=365.96, Rg=274

VADJ 2.5V SCALED TO 2.0V

FMC VADJ VOLTAGE SELECT

FMC_VADJ_SEL[ 1 0 ] ADJ (V)

TO CONTROLLER

VADJ (Default 2.5V)

VADJ (Default 2.5V)

VADJ_FPGA 2.50V @ Shared 6A MAX

SEE FMC VADJ VOLTAGE SELECT-->

VADJ 2.50V @ Shared 6A MAX

Place Scaling resistors near U48(SCALE FACTOR = 0.800)

04

2.0

53 58

2-14-2014_15:01

BF

1

2

34

45

3

23

303132

45

1516

18

19

20

22

89

36

37

38

1011121314

17

46

39

40

41

33

35

44

67

43

42

21

242526272829

47

U86

2

1 R1536491/10W1%

VADJ_FPGA_SENSE_P46

VADJ_FPGA_SCALED_P49

V33D_CTL1VADJ_FPGA

VADJ_FPGA

1

2

C24147UF25VX5R

2

1

X5R25V47UFC240

1

2

C24547UF25VX5R

1

2

C24647UF25VX5R

2

1

X5R25V47UFC247

1

2

C24347UF25VX5R

1

2

C24247UF25VX5R

2

1

X5R25V47UFC244

VADJ_FPGA

VADJ_FPGA_VADJ

12V_PWR_IN_TPS84K_VADJ

VADJ

RTCLK_VADJ

45 VADJ_FPGA_XADC_SENSE_P

21R2

2.21K

1/10W

1%

21R7

274

1/10W

1%

1

2

C27410UF25VX5R

2

1 R349200K1/10W1%

1

2

C1830.1UF25VX5R

2

1 R3982611/10W

21

DS15

LED-GRN-SMT

1

32

Q19

NDS331N1

2

R1004.7K1/16W

1

2

C1820.1UF25VX5R

VCC3V3

1

2

C1810.1UF25VX5R

I2I1

V1 V2

R138

0.0052W 1%

2

1 R29510.0K1/10W1%

21Z4

0603_SHORT

4 5

63

2 7

81

INA333U80

21

Z400201_SHORT

21

Z390201_SHORT

1 2

L28

FERRITE-781

2

C1800.1UF25VX5R

VCC12_P

VCC3V3

21Z38

0201_SHORT

VCC5V0

1

2 1%1/10W200KR348

2

1 R347200K1/10W1% 2

1 R4104531/10W1% 2

1 R1887151/10W1% 2

1 R13161/10W1%

1

2

C20522UF25VX5R

2

1 R3721.00K1/16W1%

VADJ_FPGA_POWER_GOOD

45 VADJ_FPGA_XADC_SENSE_N

VADJ_FPGA_R_SENSE_P VADJ_FPGA_CS_P 49

NC NC

VADJ_FPGA_TRIM49

49 VADJ_FPGA_EN

VADJ_PH_ISLAND

NCNCNC

NCNCNCNC

NC

NC

NC

NC

NC

VADJ_FPGA_R_SENSE_N

6

5

4

12

11

16

15

14

13

10

9

1

2

3

7

8

U66 IDTQS3VH253QG8

IDTQS3VH253QG8

NC

VADJ_SEL0 49NC49 VADJ_SEL1

Page 54: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

AGND1AGND2

ILIM

ISHARE

OCP_SEL

PGND1PGND2PGND3PGND4PGND5

PH1PH2PH3PH4PH5PH6PH7PH8PH9

PVIN1PVIN2PVIN3PVIN4PVIN5

RT_CLK

SENSE+

SS_TR

STSEL

SYNC_OUT

VADJ

VIN

VOUT1VOUT2VOUT3VOUT4VOUT5VOUT6

LMZ31710RVQ

RVQ_S_PB3QFN_N42

INH_UVLO

DNC1DNC2DNC3

PWRGD

GND

GND

GND2

1

R2R1

S1 S2

GND

GND

GND

GND

RG1 RG2

V_PVIN_N

VIN_P VOUT

REFV_N

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GND

required for LMZ31710 per TI power specialistNo external AGND-to-PGND short

this short is internal

(TR mode)

Css = 27nF~= 7.0mS

Note 4:

TO CONTROLLERVCC3V3 3.3V SCALED TO 2.0V

Place scaling resistors near U48(SCALE FACTOR = 0.606)

780ohm @ 25MHz

See LMZ31710 datasheet

placement close to packagebetween pins 26 and 23

Note 1:

Note 2:

See LMZ31710 datasheetpg. 26 for AGND connectionto PGND (GND)

pg. 26 for Vin and Vout CAP layoutsSee LMZ31710 datasheet

See LMZ31710datasheet pg. 26 for PHcopper island layout

pg. 26 for Rset resistors

(limit=full)

(hiccup)

PCB P/N: 1280681SCH P/N: 0381513

SCHEM, ROHS COMPLIANTZC706 EVALUATION PLATFORM

VCC3V3/VCC3V3_FPGA 3.3V

VCC3V3/VCC3V3_FPGA 3.3V

VCC3V3 3.3V SHARED 10A MAX

CLOSE TO FPGA POWER PINPLACE REMOTE SENSE Z-SHORT

VCC3V3 ENABLEVCC3V3_EN = LOW = VCC3V3 OFF

VCC3V3_FPGA 0A - 0.5A => CS = 0V - 2.02VG=807.45, Rg=124

VCC3V3_FPGA 3.3V SHARED 10A MAX

Note 3:

TO XADC SCALING NETWORK ONLY(INTERNAL XADC FOR VCC3V3)

WIRE VCC3V3_SENSE_P NET Z44=>U27.27 FIRST, THEN U15.27 TO TOP OF R525

VCC3V3_VADJ

MARGIN R3

BF

2-14-2014_15:01

5854

2.0

04

U15_AGND 54

21

R179

1.78K 1%

U15_RT_CLK

NCU15_NC8

NCU15_NC7

NCU15_NC6

NCU15_NC5_ISHARE

NCU15_NC4_ILIM

NCU15_NC3_OCP_SEL

NCU15_NC2_STSEL

NCU15_NC1_SYNC_OUT

VCC3V3_PWRGD

VCC3V3_VADJ

2

1 R1813161/10W1%

2

1 R11390.9K1/10W1%

46 VCC3V3_FPGA_SENSE_P

VCC3V3_FPGA_SCALED_P49

VCC3V3_FPGA_CS_P 49

VCC3V3_FPGA_EN49

21 Z440201_SHORT

VCC3V3_FPGA_XADC_SENSE_P 45

VCC3V3_FPGA_XADC_SENSE_N 45

VCC3V3

VCC5V0

21R432

124

1/10W

1%

VCC3V3_FPGA

1

2

C1850.1UF25VX5R

4 5

63

2 7

81

INA333U81

21

Z420201_SHORT

21

DS16

LED-GRN-SMT

21

Z410201_SHORT

2

1 R3992611/10W

1

2

C309100UF6.3VX5R

1

2

C308100UF6.3VX5R

1

2

C307100UF6.3VX5R

21

S1 S2R112

0.005

3W1%

VCC3V3_FPGA_R_SENSE_P

VCC3V3_FPGA_R_SENSE_N

R34327.4K1/10W

1%

VCC3V3

U15_PH

54 U15_AGND

1

2

C24847UF25VX5R

VCC3V3

1

2

C311100UF6.3VX5R

1

2

C310100UF6.3VX5R

VCC12_P

2

1

X5R25V47UFC2501

2

C24947UF25VX5R

1

2

C27510UF25VX5R

1

2

C1840.1UF25VX5R

1 2

L29

FERRITE-781

2

C20622UF25VX5R

12V_PWR_IN_LMZ_VCC3V3_FPGA

49 VCC3V3_FPGA_TRIM

2

1 R5256491/10W1%

2

1 R5261.00K1/16W1%

223

6

25

4

2021313233

101314151617181942

111123940

22

27

28

29

7

26

3

343536373841

30

5924

8

U15

U15_AGND 54

1

2

C5670.027UF10VX5R

U15_CSS_22NF_7MS

Page 55: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

XXX

XXX

GND

GND

XXX

GNDGND

GND GNDGND GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

FB2GNDBP

PGND2SW2

BOOT2

PVDD2

COMP1

EN2_BEN1_BPGND1SW1

PVDD1

COMP2GNDPAD

FB1

BOOT1

GND

FB2GNDBP

PGND2SW2

BOOT2

PVDD2

COMP1

EN2_BEN1_BPGND1SW1

PVDD1

COMP2GNDPAD

FB1

BOOT1

GND

XXX

GND

780ohm @ 25MHz

PCB P/N: 1280681SCH P/N: 0381513

ZC706 EVALUATION PLATFORMSCHEM, ROHS COMPLIANT

VCCPINT 1.0V @ 1.5A

VCC1V5_PS 1.5V @ 2.5A

VCC3V3_PS 3.3V @ 2.5A

VCCP1V8 1.8V @ 1.5A

780ohm @ 25MHz

Dual switching supplies

Dual switching supplies

2-14-2014_15:01

BF5855

2.0

04

1

2 DNPDNPDNPR546

1

2 5%1/10W0R552

2 1R551

01/10W

5%

VCC3V3_PS_EN_B49 55VCC3V3_PS_EN_B_R

55VCCPINT_EN_B_R

2 1R548

01/10W

5%

VCCPINT_EN_B49 55VCC1V5_PS_EN_B_RVCC1V5_PS_EN_B49

55VCCPAUX_EN_B_R

VCCPAUX_EN_B_R5555 VCC3V3_PS_EN_B_R

VCCPINT_EN_B_R55 VCC1V5_PS_EN_B_R55

VCC12_P_U104_FILT55

2

1 R545DNPDNPDNP

1

2

C721DNPDNP

VCC12_P_U104_FILT

VCC12_P_U105_FILT

101112131415

16

8

6543

1

9

17

7

2

U104 TPS54291

TPS54291_TSSOP_16

VCC3V3_PS

VCC3V3_PS VCC3V3_PS

VCCPINT

VCCPINT

VCC1V5_PS

VCC1V5_PS

VCCP1V8

VCCP1V8

VCC3V3_PS

2

7

17

9

1

3456

8

16

151413121110

TPS54291_TSSOP_16

TPS54291U105

1

2

C67047UF25VX5R

1

2

C66947UF25VX5R

21

20%

6A4.7UH

L33

1 2

L31

4.7UH 6A

20%

1

2

C7094PF50VC0H

1

2

C7001200PF50VX7R

2

1 R49740.2K1/10W1%

2

1 R4806.49K1/10W1%

1

2

C7108.2PF50VNP0

1

2

C71112PF50VNP0

2

1 R49420K1/10W1% 2

1 R49530.1K1/10W1%

1

2

C698820PF25VX7R

2

1 R46180.6K1/10W1%

1

2

C6784.7UF25VX5R

2

1

X7R50V1000PFC699

2

1 R47516.2K1/10W1%

21R486

20.5K

1/10W

1%

1 21%

1/10W

20.5K

R500

2

1

X5R25V22UFC708 1

2

C70722UF25VX5R

21 20%

3.25A8.2UH

L32

1 2

L34

8.2UH 3.25A

20%

1 2

L35

FERRITE-78

21R514

0 1/10W

5%

1 2

C673

0.047UF

10V

X5R

21

X5R

10V

0.047UF

C674

2

1 R46323.2K1/10W1%

1

2X7R50V1000PFC697

21R499

20.5K

1/10W

1%

1

2

C6792.2UF16VX5R 2

1

X5R16V2.2UFC680

2

1

X5R16V2.2UFC677

2

1

X7R25V470PFC704

21R469

20.5K

1/10W

1%

1

2

C6894.7UF25VX5R

1

2

C703470PF25VX7R

2

1 R465101/10W1%

VCC12_P

1

2 1%1/10W10R466

1

2

C706470PF25VX7R

2

1 R468101/10W1%

VCC12_P

21

FERRITE-78

L36

1

2 1%1/10W10R467

2

1

X7R25V470PFC705

21

X5R

10V

0.047UF

C676

1 2

C675

0.047UF

10V

X5R

2

1

X5R25V4.7UFC690

1 25%

1/10W

0R515

1

2 1%1/10W20KR496

1

2

C71215PF50VNP0

1

32

Q27

NDS331N

21

DS31

LED-GRN-SMT

1

2

R5334.7K1/16W

2

1 R5372611/10W

23

1

NDS331N

Q28

12

LED-GRN-SMT

DS32

2

1

1/16W4.7KR534

1

2 1/10W261R538

2

1 R5402611/10W

21

DS34

LED-GRN-SMT

1

2 1/10W261R539

2

1

1/16W4.7KR535

12

LED-GRN-SMT

DS33

23

1

NDS331N

Q29

VCC3V3_PS

125%

1/10W

0 R549

2

1

DNPDNPC722

VCC12_P_U104_FILT55

VCC12_P_U105_FILT55

1

2

C724DNPDNP

125%1/10W

0 R550

VCCPAUX_EN_B49

2

1

DNPDNPC723

1

2 DNPDNPDNPR547

VCC12_P_U105_FILT55

Page 56: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

2

1

GND

GND

GND GND

GND

PWRPAD

GNDPGOODVIN

ENREFOUTVOSNS

PGNDVOVLDOINREFIN

GND

GNDGND

PWRPAD

GNDPGOODVIN

ENREFOUTVOSNS

PGNDVOVLDOINREFIN

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

AGND1AGND2

ILIM

ISHARE

OCP_SEL

PGND1PGND2PGND3PGND4PGND5

PH1PH2PH3PH4PH5PH6PH7PH8PH9

PVIN1PVIN2PVIN3PVIN4PVIN5

RT_CLK

SENSE+

SS_TR

STSEL

SYNC_OUT

VADJ

VIN

VOUT1VOUT2VOUT3VOUT4VOUT5VOUT6

LMZ31704RVQ

RVQ_S_PB3QFN_N42

INH_UVLO

DNC1DNC2DNC3

PWRGD

GND

pg. 26 for Vin and Vout CAP layouts

Css = 27nF

datasheet pg. 26 for PHcopper island layout

SCHEM, ROHS COMPLIANTSCH P/N: 0381513PCB P/N: 1280681

ZC706 EVALUATION PLATFORM

Linear Power Supplies Page 1

Linear Power Supplies Page 1

Note 1: See LMZ31704 datasheet

See LMZ31704Note 3:

~= 7.0mS

5V @ 3A

(alwaysenabled)

(TR mode)

(hiccup)

(3A)

Note 2: No external AGND-to-PGND connectionrequired for LMZ31704 per TI 2-07-2014

04

2.0

56 58

2-14-2014_15:01

BF

56U44_AGND

U44_RT_CLK

223

6

25

4

2021313233

101314151617181942

111123940

22

27

28

29

7

26

3

343536373841

30

5924

8

U44

NCU44_NC8

NCU44_NC7

NCU44_NC6

NCU44_NC4_ISHARE

NCU44_NC4_OCP_SEL

NCU44_NC3_STSEL

NCU44_NC2_INH_UVLO

NCU44_NC1_SYNC_OUT

2

1 R1801961/10W1%2

1 R16963.4K1/10W1%

56U44_AGND

VCC5V0_VADJ54U44_AGND

VCC12_P

12

LED-GRN-SMT

DS20

21

DS21

LED-GRN-SMT

56 PS_DDR_LINEAR_PG

VCC3V3_PS

VCC3V3_PS

VCC1V5_PL

VCC3V3_PS

12345 6

7

1098

11

TPS51200DRCT

SON10_TPS51200U27

VTTDDR_PS

VTTVREF_PS

VTTDDR_SODIMM

VTTVREF_SODIMM

VCC1V5_PS

PS_DDR_LINEAR_PG 56

SODIMM_DDR_LINEAR_PG56

2 1

GND_SHORT

Z7

23

1

460MWNDS331N

Q10

1

2 1%1/10W249R150

1

2

R27310.0K1/10W1%

21R272

10.0K

1/10W

1%

1 21%

1/10W

10.0K

R271

2

1

X7R50V1000PFC474

2

1

X5R25V4.7UFC432

1

2X5R16V10UFC579 1

2X5R16V10UFC578 1

2X5R16V10UFC577 1

2X5R16V10UFC576

2

1

X5R25V0.1UFC110

1

2X5R16V10UFC575

VCC3V3

2

1 C58410UF16VX5R

1

2

C1110.1UF25VX5R

11

8910

765

4321

U28 SON10_TPS51200

TPS51200DRCT

2

1 C58310UF16VX5R

2

1 C58210UF16VX5R

2

1 C58110UF16VX5R

2

1 C58010UF16VX5R

1

2

C4334.7UF25VX5R

1

2

C4751000PF50VX7R

21R276

10.0K

1/10W

1%

1 21%

1/10W

10.0K

R275

2

1

1%1/10W10.0KR274

2

1 R1512491/10W1%

1

32

Q11

NDS331N460MW

12 Z8

GND_SHORT

VCC3V3

VCC3V3

SODIMM_DDR_LINEAR_PG 56

1

2

C26810UF25VX5R

U44_PH

2

1 C296100UF6.3X5R

VCC5V0

1

2

C2780.027UF10VX5R

U44_CSS_22NF_7MS

R32127.4K1/10W

1%

VCC3V3

VCC5V0_PWRGD

2

1

X5R10V0.022UFC279

U44_AGND56

Page 57: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

VCC3V3

VCC3V3

VCC3V3

GND

BIAS

ENFB

GND

IN1IN2IN3IN4

NC1NC2NC3NC4NC5NC6

OUT1OUT2OUT3OUT4

PG

SS

THERMPAD

GND

GND

GNDGND

GND GND

GND

GND

BIAS

ENFB

GND

IN1IN2IN3IN4

NC1NC2NC3NC4NC5NC6

OUT1OUT2OUT3OUT4

PG

SS

THERMPAD

BIAS

ENFB

GND

IN1IN2IN3IN4

NC1NC2NC3NC4NC5NC6

OUT1OUT2OUT3OUT4

PG

SS

THERMPAD

GND

GND

GNDGND

GND

GND

GND

IN OUT

GNDTAB

GND

SNS_ADJSHDN_B

GND

VCC3V3

VCC3V3

VCC3V3

GND

BIAS

ENFB

GND

IN1IN2IN3IN4

NC1NC2NC3NC4NC5NC6

OUT1OUT2OUT3OUT4

PG

SS

THERMPAD

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC3V3

VOUT = 0.8 (1 + R1/R2)

VOUT = 0.8 (1 + R1/R2)

VOUT = 0.8 (1 + R1/R2)

VCC2V5 2.5V 1.5A MAX

PCB P/N: 1280681SCH P/N: 0381513

Change 3.01K to 2.49K for 1.8V

VOUT = 2.004V

2.0V @ 3A

VOUT = 0.999V

1.0V @ 3A

1.2V @ 3A

VOUT = 1.199V1.8V @ 3A

VOUT = 0.8 (1 + R1/R2)

VOUT = 1.795V

ZC706 EVALUATION PLATFORMSCHEM, ROHS COMPLIANT

Linear Power Supplies Page 2

Linear Power Supplies Page 2

2-14-2014_15:01

BF5857

2.0

04

21

DS26

LED-GRN-SMT

21R370

2.15K

1/10W

1%

10

1116

12

5678

234131417

1181920

9

15

21

U92 QFN_20

TPS74901_20_VQFN57LINEAR_POWER_GOOD

49 VCCAUX_IO_EN

57 LINEAR_POWER_GOOD

1

2

C6101UF25VX5R

MGTVCCAUX

MGTAVTT

MGTAVCC

2

1 R4192.87K1/10W1%

2

1 R4344.99K1/10W1%

2

1 R4182.49K1/10W1%

VCC1V8

VCC1V8

2

1 R4121.13K1/10W1%

2

1 R4333.01K1/10W1%

VCC2V5

2

1 R3782.00K1/16W1%

2

1 C58710UF16VX5R2

1C58610UF16VX5R

2 4

63

51

U19 SOT223_6

TL1963ADCQR_SOT223

2

1 C63910UF16VX5R

VCCAUX_IO

2

1 R4312.00K1/16W1%

2

1

X5R25V4.7UFC620

NC

NC

NC

NCNCNCNC

NCNCNCNC

NC

NC

NC

LINEAR_POWER_GOOD 57

2

1

X5R25V1UFC611

1

2

C6214.7UF25VX5R

1

2X5R16V10UFC640

21

15

9

2019181

171413432

8765

12

1611

10

TPS74901_20_VQFN

QFN_20U93

10

1116

12

5678

234131417

1181920

9

15

21

U94 QFN_20

TPS74901_20_VQFN

2

1 C64110UF16VX5R

2

1

X5R25V4.7UFC622

1

2

C6121UF25VX5R

57LINEAR_POWER_GOOD

NC

NC

NC

NCNCNCNC

2

1 R4144.53K1/10W1%

NCNCNCNC

NC

NC

NC

57LINEAR_POWER_GOOD

2

1

X5R25V1UFC613

1

2

C6234.7UF25VX5R

1

2X5R16V10UFC642

21

15

9

2019181

171413432

8765

12

1611

10

TPS74901_20_VQFN

QFN_20U95

2

1 R4153.57K1/10W1%

2

1

1%1/10W10.0KR422

2

1 R4132491/10W1%

1

32

Q23

NDS331N460MW

2

1 R4364.7K1/10W5%

Page 58: ZC706 EVALUATION PLATFORM HW-Z7-ZC706 D (XC7Z045 …read.pudn.com/downloads724/doc/2898557/FPGA.pdf · Sheet of Date: Title: Ver: A B C D 4 3 2 1 D C B A 4 3 2 1 Sheet Size: B Rev:

GND

GND

GND

GND

GND

GND

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

USB A

USB Mini-B Cable

USB Mini-B

12v Power Brick

110V Prong

Power Cord

IEC320-C13

PCIE

POWER

USB A USB Mini-B

USB Micro-B Cable

PCIe Adapter Cable

4-Pin ATX Power6-Pin MolexMini-fit Jr.

12V Fan / Heatsink

SCHEM, ROHS COMPLIANT PCB P/N: 1280681SCH P/N: 0381513

Mechanical Components

ZC706 EVALUATION PLATFORM

Mechanical Components

and must be connected to MH4 and MH5to level the board properly

NOTE: These two standoffs are shorter

NOTE: No standoff foot on MH2

HS1

MANF=RADIANMANF_P/N=XLX002

2-20-2014_10:17

5858 BF

2.0

04

MS2

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MACHINE_SCREW_4-40#4-40 MACHINE SCREW 0.25"

MS3

MW1

WASHER_FLAT_4

WASHER_FLAT_4

MW3

MW4

WASHER_FLAT_4

WASHER_FLAT_4

MW5

MW6

WASHER_FLAT_4

STANDOFF_0P625

MSO3

MSO4

STANDOFF_0P500

STANDOFF_0P500

MSO5

STANDOFF_0P625

MSO6

MACHINE_SCREW_4-40#4-40 MACHINE SCREW 0.25"

MS5

CBL2

PCIE_ADAPTER_CABLEMJB22

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB21

JUMPER_BLOCK_2-PIN

MJB20MJB19

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB18MJB17

JUMPER_BLOCK_2-PIN

JUMPER_BLOCK_2-PIN

MJB16MJB15

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB14MJB13

JUMPER_BLOCK_2-PIN

MJB12

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB11MJB10

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB9

MJB8

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB7MJB6

JUMPER_BLOCK_2-PINJUMPER_BLOCK_2-PIN

MJB5

#4-40 MACHINE SCREW 0.25"

MS17

MACHINE_SCREW_4-40

MS6

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MS16

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MACHINE_SCREW_4-40#4-40 MACHINE SCREW 0.25"

MS15MS4

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MS14

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MACHINE_SCREW_4-40#4-40 MACHINE SCREW 0.25"

MS12MS1

#4-40 MACHINE SCREW 0.25"MACHINE_SCREW_4-40

MSO1

STANDOFF_0P625

MRB1

RUBBER_BUMPER

PL1

ZC706_PCIE_PLATECBL4

USB_MICRO_CABLE

MSTK1

PCIE_POWER_STICKER

MMD1

DDR3_SODIMM

CBL3

PC_POWER_CABLE

PB1

PWR_BRICK_12V

CBL1

USB_MINIB_CABLE 1MH_125_250

MH6

RUBBER_BUMPER

MRB6

JUMPER_BLOCK_2-PIN

MJB2MJB1

JUMPER_BLOCK_2-PIN

1

MH5

MH_125_250

1MH_125_250

MH4

1

MH3

MH_125_250

1MH_125_250

MH2

1

MH1

MH_125_250

MRB5

RUBBER_BUMPER

RUBBER_BUMPER

MRB4

MRB3

RUBBER_BUMPER

JUMPER_BLOCK_2-PIN

MJB4MJB3

JUMPER_BLOCK_2-PIN