Zarlink Performing Clock Recovery

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SEMICMF.020 1

AN5789 Issue 1 August 2002

Contents1.0 Circuit Emulation Services over a PacketNetwork

1.1 Leased Line Provision

1.2 Regenerating the Clock

2.0 Clock Recovery Techniques

2.1 Adaptive Clock Recovery

2.2 Differential Recovery

3.0 Implementation of Clock Recovery


3.2 Differential Clock Recovery

3.3 Using the RTCP protocol

4.0Proof of Concept using the MT90880

Evaluation Board

Related Documents

• "Unstructured Circuit Emulation Using the

MT90880", Zarlink Semiconductor Application

Note, MSAN-199, August 2002

• "MT90880 Data Sheet", Zarlink Semiconductor,

DS5568, Issue 1.3, June 2002

1.0 Circuit Emulation Services over aPacket Network

The MT90880 can be used to transport TDM linksacross the packet domain and transparentlyreconstruct the links at the far end. This is similar to

the circuit emulation services defined by the ATMForum, with the MT90880 providing the core of thecircuit emulation inter-working function.

1.1 Leased Line Provision

Circuit emulation is typically used to support the

provision of leased line services to customers usinglegacy TDM equipment. For example, Figure 1 below

shows a leased line TDM service being carriedacross a packet network. The advantages are that acarrier can upgrade to a packet switched network,while still maintaining their existing TDM business.

MSAN-198

Performing Clock Recovery for CircuitEmulation when using the MT90880

Application Note

Figure 1 - Leased Line services over a Circuit Emulated link

Carrier Network Customer

Premises

Customer

Premises

ExtractClock

C u s t o m e r d a t a

~ ~f service f regen

TDMPacket

Network TDM


TDM topacket

f regen

Provider EdgeInterworking

Function


Function

queue

TDM Leased Line Service



MSAN-198 Application Note

2 SEMICMF.020

1.2 Regenerating the Clock

One of the main issues with this type of application is that the clock used to drive the TDM link is not linked intothe central office clock, and hence may be any value within the tolerance defined for that service. The reverse

link is also independently timed, and may be operating at a slightly different frequency. In the plesiochronousdigital hierarchy the difference in clock frequencies between TDM links is compensated for using bit stuffing

techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.

With a packet network, that connection between the ingress and egress frequency is broken, since packets arediscontinuous in time. From Figure 1, the TDM service frequency f service at the customer premises must be

exactly reproduced at the egress of the packet network ( f regen). The consequence of a long-term mismatch infrequency is that the queue at the egress of the packet network will either fill up or empty, depending onwhether the regenerated clock is slower or faster than the original. This will cause loss of data and degradation

of the service.

This application note describes a means to achieve clock recovery when performing circuit emulation with anMT90880. A related application note (reference1) describes how to use the MT90880 to perform circuitemulation using unstructured data transfer (UDT).

2.0 Clock Recovery Techniques


For operation with a packet network, the clock rate can be inferred by averaging the arrival rate of the packetsover a period. This averaging period has to be sufficiently long to remove jitter effects, caused by variation inthe transit delay of packets across the network. The technique is known as adaptive clock recovery.

It is not necessary to use the actual data packet arrival rate, since it could be equally well performed on out of

band packets transmitted at a rate that is related to the same TDM service clock. This means that the firstprovider edge could transmit clock packets to the remote end at a regular rate, related to the TDM servicefrequency, f service (see Figure 2 below). The remote provider edge averages the arrival rate of these packets,and compares it to the rate of a local oscillator. The frequency of the local oscillator, f regen is adjusted to match

the TDM service frequency. The reverse link is independently timed, and has its own, separate adaptive timingcontrol.

Figure 2 - Adaptive Clock Recovery

Carrier Network Customer Premises

Customer Premises

ExtractClock


~

f service f regen

TDMPacket

Network TDM


TDM topacket

f regen


Function


Function

queue


ClockPacket

Com-pare ~



Application Note MSAN-198

SEMICMF.020 3

The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may

prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digitalhierarchy. The reason for this is that any variation in delay between clock packets will feed through as avariation in the frequency of the recovered clock, f regen. High frequency jitter can be filtered out, but any lowfrequency variation or wander is more difficult to remove without a very long time constant. This will in turn

affect the ability of the system to lock to the original clock within an acceptable time.

The extent of the wander is dependent on the characteristics of the carrier's packet network. If the loading onthe network is kept small, such as might be expected if it was dedicated to this type of service, then the wander on the clock frequency may never exceed the specified limits. The performance can be further improved bygiving the clock packets high priority, such that their delay through the network (and hence the delay variation)

is reduced.

This may not be an issue if the system is as drawn in Figure 2, with the regenerated circuit going direct to acustomer site. However, if the regenerated circuit has to connect into the existing plesiochronous hierarchy,then excessive wander will cause interruptions in service. Therefore the PSTN operator may require that an

alternative technique capable of meeting the wander requirements be used.

2.2 Differential Recovery

A second means of regenerating the service clock is to relate it to a known clock that is available at each end of

the packet network (e.g. a primary reference clock, if one is available). For example, the difference between theTDM service frequency and the primary reference frequency could be measured and transmitted across thenetwork. The service frequency can then be easily regenerated by adding back in the reference frequency (seeFigure 3).

Figure 3 - Primary Reference Clocking

The advantage of this technique is that it is unaffected by the variation in transit time between clock packets.

Therefore it is possible to meet the required jitter and wander specification for the regenerated clock regardlessof the loading or congestion on the packet network. Differential techniques (such as the SRTS scheme definedin the ATM AAL1 specification) are acceptable for TDM links that need to be connected back into the PSTN.

Carrier Network Customer Premises

Customer Premises

ExtractClock


~f service f regen

TDMPacket

NetworkTDM


TDM topacket

f regen


Function


Function

queue


Differ-ence

add ~

~Primary Reference Source,

f reference




4 SEMICMF.020

The main disadvantage is that the technique requires a common clock at each end of the packet network.

Where the packet network runs between central offices, it may be that there is a primary reference sourceavailable in each central office, traceable back to the same high quality reference. However, often one edge of the packet network is on a remote site, without an accessible reference clock. In these situations the adaptive

clock recovery technique must be used.

One possible alternative is to use a GPS (global positioning by satellite) unit at each end of the network. Theseunits take reference time from a satellite, avoiding the need to distribute the clock by conventional means. GPSunits are small and relatively inexpensive, but still capable of generating a reference clock with a highly stableand accurate frequency.

3.0 Implementation of Clock Recovery


At the first provider edge, where the TDM service is originally turned into packets, a means of generating clockpackets at regular intervals needs to be provided. This could be as simple as dividing down the TDM serviceclock frequency by a fixed amount, and using the result to generate a regular interrupt of the host processor.

On interrupt, the host processor then needs to send a clock packet across the network to the packet egressnode (Figure 4).

Figure 4 - Source Provider Edge Node

On receiving the packets, the receiver host processes averages the arrival rate and uses the result to control aDCO. The output of the DCO is used to clock the TDM data out of the MT90880, and onto the TDM circuit. For adaptive control, a feedback loop is included to compare the recovered clock against the incoming packet

arrival rate. The Host CPU implements the filtering algorithm required to reduce jitter and wander to acceptablelevels.

Figure 5 - Receiving Provider Edge Node

MT90880LIU

÷ n

HostCPU

Clock

Data

Clock packets

TDM in

MT90880

HostCPU

Clock packets

LIUClock

Data

TDM out

~

DCO

÷ n

feedback




SEMICMF.020 5

3.2 Differential Clock Recovery

This method is similar to the first, except that the interrupt is generated from a division of the reference clockfrequency. At regular intervals according to the reference clock, a counter driven by the TDM service clock isread, and the result used to generate a clock packet relating the service clock to the reference clock (Figure 6).

Figure 6 - Source Provider Edge Node

On receiving the packets, the receiver host compares the relationship between the reference clock and the

service clock, and adjusts a DCO to achieve the same relationship against its own reference clock. The outputof the DCO is used to clock the TDM data out of the MT90880, and onto the TDM circuit.

Figure 7 - Receiving Provider Edge Node

3.3 Using the RTCP protocol

RTCP is a standard protocol used for maintenance of real time links over a packet network. It is normallyassociated with RTP (Real Time Protocol), which is a protocol for the transport of real time data across a packetnetwork. However, in this case, RTCP could be used as a standalone protocol for communicating the frequency

of a clock.

The RTCP protocol transmits packets at a rate of approximately one every few seconds across the packetnetwork. These packets contain largely statistical information about the data packets received using RTP.However, each packet also contains two timestamps: Wall clock time, a standard reference clock; and the RTP

timestamp, relative to the real time clock being used (in this case, the TDM service clock).

Wallclock time is defined as the number of seconds since 00.00 hours UTC on the 1st January 1900. It containstwo parts: a 32-bit integer and 32-bit fractional part. Provided the wallclock time at each end of the network isaccurately aligned, this could be used to represent a primary reference clock. Usually wallclock time ismaintained by using NTP, but this may not be accurate enough for the purpose. Alternatively, wallclock time

could be related to a telecom clock or GPS clock at each provider edge.

MT90880LIU

counter

Clock

Data

Clock packets

TDM in

HostCPU

÷ nReference clock

read

MT90880

HostCPU

Clock packets

LIUClock

Data

TDM out

~

DCO

counter

read

÷ nReference clock




6 SEMICMF.020

The RTP timestamp is defined as the value of a service clock counter at the same instant that wall clock time

was read. The counter increment can be defined in a profile; for example, it could be defined as a count of thenumber of bit periods since the last packet was sent.

Hence, an RTCP packet can be used as a standards-based means of transporting timing information across

the network for use with both adaptive and differential clock recovery methods. Where there is no commonclock, the wallclock times can be ignored, and the RTP timestamp used to implement an adaptive clockrecovery scheme. Where there is a sufficiently accurate clock at either end of the network, this can be used todrive wallclock time. The RTCP packet then can be used to indicate the relationship between the reference(wallclock time) and the service clock (RTP timestamp).

4.0 Proof of Concept using the MT90880 Evaluation Board

The evaluation board for the MT90880 contains some additional hardware to allow schemes based on the

ideas outlined in this application note to be evaluated (see Figure 8). Using this hardware it is possible toimplement both adaptive and differential clock recovery techniques, and assess the viability for use in aparticular type of system.

The hardware includes a stable, digitally controlled oscillator, a DPLL (Zarlink MT9045) to generate the TDM

service clock and frame pulse from the variable oscillator, an external clock input and a divider to produce a lowfrequency interrupt from the service clock. The TDM service clock and frame pulses are used to control a TDMswitch (Zarlink MT90869). This contains internal bit error rate test sequence logic, which can be used togenerate test data for converting into packets in the MT90880 device.

Figure 8 - MT90880 Evaluation Board - Clock Recovery Hardware

MT90880

TDM-IPProcessor

ST-bus

DCO16.384 MHz

± 100 ppm

MPC8260 CPU

Frequencycontrol

DPLL

MT9045

clockframepulse

TDMSwitch

MT90869

÷1024

interrupt

Externalclock

~

Timer

Packetinterface

Setup and clock packets

interrupt




SEMICMF.020 7

4.1 Adaptive Clock Recovery with the MT90880 Evaluation Board

The following diagram (Figure 9) shows how the evaluation board can be used to trial an adaptive clockrecovery scheme.

Figure 9 - Adaptive Clock Recovery with the MT90880 Evaluation Board

On the source board, the TDM service clock is generated by the DCO. This allows the clock to be set to anygiven frequency within a range. Furthermore, the CPU is able to inject controlled jitter and wander into the DCO

output, to test the ability of the receiving end to track the input. The clock and frame pulse output from the DPLLis used to clock a TDM stream out of the TDM switch and into the MT90880. The content of this stream isarbitrary, and it is used to simulate a real stream running at a given rate. For instance, the bit error ratecapability of the MT90869 could be used to generate a pseudo-random bit-stream, allowing the integrity of the

data stream to be checked at the receiver node.

The frame pulse is divided down by up to 1024, and this is used to generate an interrupt to the CPU. Oninterrupt, the CPU generates a clock packet to be sent to across the network to the receiving node containingthe timestamp. This can be either in RTCP format, or using a proprietary packet type. If the appropriateequipment is available, then the packets through the LAN could be delayed by varying amounts to simulate

heavy traffic loading and congestion on the network. Alternatively, the board could be connected to a real LAN.

At the receiver, the clock packets are routed to the CPU. The recovered clock is again generated using theDCO, and is periodically adjusted dependent on the arrival rate of the clock packets. The clock signal from theDPLL is routed to the CPU's timer/counter block to allow comparison of the recovered clock frequency againstthe timestamps received from the source.

The recovered TDM clock is used to clock the data out of the MT90880 and into the TDM switch. If the bit error rate test capability of the MT90869 has been used to generate the data, the integrity of the received data can

be checked. The internal queues can also be monitored to check for underflow and overflow. This can be anindication that the clock may not be as accurate as required.

Source Board

MT90880

TDM-IPST-bus

Frequencycontrol

clock

DCO

DPLL

framepulse

÷ 1024

~

MPC8260 CPU

TDMSwitchinterrupt

Timer

Receiving Board

MT90880

TDM-IPST-bus

Frequencycontrol

clock

DCO

DPLL

framepulse

÷ 1024

~

MPC8260 CPU

TDMSwitchinterrupt

Timer

LAN

Setup and clock packetsExternalclock

Externalclock


interrupt

interrupt




8 SEMICMF.020

4.2 Differential Clock Recovery with the MT90880 Evaluation Board

The next diagram (Figure 10) shows how the evaluation board can be used to trial a differential clock recoveryscheme.

Figure 10 - Differential Clock Recovery with the MT90880 Evaluation Board

On the source board, the external clock input is used to bring in a low frequency primary reference clock of some type (e.g. GPS clock or a stable test clock). The TDM service clock is generated by the DCO, allowingthe actual frequency to be controlled within a given range.

The external reference clock is routed into the CPU's interrupt input, causing a periodic interrupt, while theTDM service clock is routed into a timer/counter channel on the CPU, allowing the number of clock periods

between reference clock interrupts to be counted. A clock packet can then be constructed, relating thefrequencies of the two either using RTCP, or a private protocol encoding the relationship. As with the adaptivescheme, the clock and frame pulse output from the DPLL is used to clock a TDM stream out of the TDM switchand into the MT90880.

At the receiver, the clock packets are routed to the CPU. The TDM service clock is again generated using the

DCO, and as with the source board, both the service and reference clocks are routed into channels on the

CPU's timer/counter. The relationship between the service clock and the common reference is adjusted tomatch that specified in the incoming clock packets.

The recovered TDM clock is used to clock the data out of the MT90880 and into the TDM switch. If the bit error

rate test capability of the MT90869 has been used to generate the data, the integrity of the received data canbe checked. The internal queues can also be monitored to check for underflow and overflow.

Source Board

MT90880

TDM-IPST-bus

Frequencycontrol

clock

DCO

DPLL

framepulse

÷ 1024

~

MPC8260 CPU

TDMSwitchinterrupt

Timer

Receiving Board

MT90880

TDM-IPST-bus

Frequencycontrol

clock

DCO

DPLL

framepulse

÷ 1024

~

MPC8260 CPU

TDMSwitchinterrupt

Timer

LAN



interrupt

interrupt

~

PrimaryReference

Clock



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