YSS920B APPLICATION MANUAL - pudn.comread.pudn.com/downloads154/sourcecode/asm/682421... · 70 RAMA2 O Address output pin for external memory 2 71 RAMA4 O Address output pin for external

YSS920B APPLICATION MANUALCATALOG No.: LSI-6SS920B22

2006.7

YSS920B APPLICATION MANUAL

EVE 32-bit DSP Engine for Various sound Effects

Contents - 3 -

Contents

Chapter 1 Outline................................................................................ 4

1.1 Features ................................................................................................................................................... 4 1.2 Application.............................................................................................................................................. 4 1.3 Difference between YSS920B and YSS920 ........................................................................................... 4 1.4 Block Diagram ........................................................................................................................................ 5

Chapter 2 Pin Function....................................................................... 6

2.1 Pin Configuration.................................................................................................................................... 6 2.2 Pin Function ............................................................................................................................................ 7 2.3 Pin Description........................................................................................................................................ 9

Chapter 3 Function Description....................................................... 13

3.1 Register Map......................................................................................................................................... 13 3.2 Register Details ..................................................................................................................................... 15 3.3 Serial Data Interface Format ................................................................................................................. 37 3.4 Microprocessor Interface Format .......................................................................................................... 39 3.5 Program Download ............................................................................................................................... 41

Chapter 4 Basic Design Example ..................................................... 45

4.1 Peripheral Circuits (When One YSS920B Is Used).............................................................................. 45 4.2 Peripheral Circuits (When Multiple YSS920Bs Are Used) .................................................................. 46 4.3 Clock Connection for High fs ............................................................................................................... 47

Chapter 5 Electrical Characteristics ............................................... 48

5.1 Absolute Maximum Ratings ................................................................................................................. 48 5.2 Recommended Operating Conditions ................................................................................................... 48 5.3 DC Characteristics ................................................................................................................................ 48 5.4 AC Characteristics ................................................................................................................................ 49

Chapter 6 Package Dimensions........................................................ 55

APPLICATION NOTES .................................................................. 56

- 4 - Chapter 1 Outline

Chapter 1 Outline YSS920B is a 32-bit digital signal processor exclusively designed for sound field processing. As a

post-processing DSP after surround sound decoding, YSS920B can process various sound fields such as various simulation surround and virtual surround through user programs, which can provide wide variation of sound field effects on audio equipments.

1.1 Features

• Basic compatibility with the SubDSP section of YSS922/932 for DSP program • High precision processing by 32-bit floating-point operation • Capability to process various sound effects by downloading external programs to the built-in RAM • 16 channels processing capability (input: 16ch, output: 16ch) • Zero data detecting function on each channel • 32-bit data transmission ability between multiple YSS920Bs • Connectability to most types of ADC, DAC and DIR through control register setting • Built-in delay memory with 32 bits × 1024 words (Max. 21.3 ms at fs = 48 kHz) • Ability to execute up to 2.73 seconds delay (at fs = 48 kHz) when connected with an external

DRAM or SRAM • Support for sampling frequencies from 32 kHz to 192 kHz • DSP section specifications

Internal operating frequency: 30.72 to 50.00 MHz Data bus width: 32 bits MAC: 32 bits (floating-point) × 16 bits (fixed-point) + 49 bits → 49 bits Program RAM: 50 bits × 1024 words Coefficient RAM: 16 bits × 1024 words

• Ability to use up to 20 general-purpose input/output terminals • Power supply voltage: 2.5 V (for internal and PLL circuits), 3.3 V (for I/O) • Si-gate CMOS process • Lead-free 100-pin SQFP package (YSS920B-SZ)

1.2 Application

Sound field processing for AV amplifiers and audio mixers such as: 1) Simulation surrounds for Hall, Theater, Church, Stadium, Disco, Jazz, and Live 2) Virtual Surround 3) Bass Management 4) Filtering process for LPF, HPF, equalizer, etc. 5) Fader and Level Meter 6) Generating white noise, pink noise, sine waves, etc.

1.3 Difference between YSS920B and YSS920

The principal differences are as follows. Please sufficiently check that no problem occurs in your product when you replace YSS920 by YSS920B. Item YSS920B YSS920 １ Internal operating frequency 30.72 to 50.00MHz 30.72 to 40.96MHz ２ Power consumption (VDD1) 45mW (typ) / 65mW (max) 30mW (typ) / 45mW(max) ３ Power consumption (VDD2/AVDD) 120mW (typ) / 145mW (max) 80mW (typ) / 115mW (max)４ Power supply start-up order Defined (see 5.4-2 Power-on) Undefined

Chapter 1 Outline - 5 -

1.4 Block Diagram

SDI7

PLL

Inte

rfac

e fo

r ext

ern

al

mem

ories

SDO

7

Pro

gram

RA

M50

bits×

102

4 w

ord

s

Contr

ol si

gnal

Contr

ol re

sist

er

Mic

rocom

put

er

inte

rfac

e

SDI6

SDI5

SDI4

SDI3

SDI2

SDI1

SDI0

SDW

CK

SDB

CK

Coef

fici

ent

RA

M16 b

its×

102

4 w

ord

s

SDO

6

SDO

5

SDO

4

SDO

3

SDO

2

SDO

1

SDO

0

Add

ress

set

ting

RA

M

for

ext

ern

al

mem

ories

17 b

its×

256 w

ord

s

- 6 - Chapter 2 Pin Function

Chapter 2 Pin Function 2.1 Pin Configuration

< 100-pin SQFP top view >

32

SDO0

VDD2

RAMD0RAMD1RAMD2

VSS

VD

D1

RA

MD

10R

AM

D11

RA

MD

12

RA

MD

13R

AM

D14

RA

MD

15C

ASN

RA

MW

ENR

AM

OEN

RA

SNR

AM

A8

RA

MA

7R

AM

A0

RA

MA

6R

AM

A1

RA

MA

5R

AM

A2

RA

MA

9

RA

MA

4R

AM

A3

XI

XO

IOPO

RT0

IOPO

RT1

IOPO

RT2

IOPO

RT3

IOPO

RT4

AV

SSC

POA

VD

D

VD

D2

RAMA11RAMA12RAMA13RAMA14RAMA15RAMA16RAMA17

VSS

/CSSOSI

SCK/IC

VDD2 26

51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

76

VSS2728293031

33343536373839

42

4041

4344454647484950

525354555657585960616263646566676869707172737475

7778798081828384858687888990919293949596979899100

VSS

IOPO

RT5

IOPO

RT6

IOPO

RT7

IOPO

RT8

IOPO

RT9

IOPO

RT1

0IO

POR

T11

IOPO

RT1

2IO

POR

T13

IOPO

RT1

4IO

POR

T15

SDO1SDO2SDO3SDO4SDO5SDO6SDO7

SDI0SDI1SDI2SDI3SDI4SDI5SDI6SDI7

IOPORT16IOPORT17IOPORT18IOPORT19

VD

D2

(NC

)V

DD

1

SDBCKSDWCK

VDD1

RA

MA

10

VDD1

RAMD3RAMD4RAMD5RAMD6RAMD7RAMD8RAMD9

VD

D1

Chapter 2 Pin Function - 7 -

2.2 Pin Function

No. Name I/O Function 1 VSS - Digital ground pin 2 XO O Crystal oscillator connecting pin 3 XI I Crystal oscillator connecting pin (12.288 to 15.000 MHz) 4 IOPORT0 I+/O General-purpose input/output pin / SDO 0 Lch zero-flag output pin / Program branch condition

input/output pin 5 IOPORT1 I+/O General-purpose input/output pin / SDO 0 Rch zero-flag output pin / Program branch condition

input/output pin 6 IOPORT2 I+/O General-purpose input/output pin / SDO 1 Lch zero-flag output pin / Program branch condition






input/output pin 12 AVSS - Analog ground pin (for PLL) 13 CPO A PLL filter connection pin 14 AVDD - +2.5 V analog power supply pin (for PLL) 15 VDD1 - +3.3 V digital power supply pin (for input/output pin) 16 (NC) - (No connection) 17 IOPORT8 I+/O General-purpose input/output pin / SDO 4 Lch zero-flag output pin 18 IOPORT9 I+/O General-purpose input/output pin / SDO 4 Rch zero-flag output pin 19 IOPORT10 I+/O General-purpose input/output pin / SDO 5 Lch zero-flag output pin 20 IOPORT11 I+/O General-purpose input/output pin / SDO 5 Rch zero-flag output pin 21 IOPORT12 I+/O General-purpose input/output pin / SDO 6 Lch zero-flag output pin / Chip address setting input pin 0 22 IOPORT13 I+/O General-purpose input/output pin / SDO 6 Rch zero-flag output pin / Chip address setting input pin 1 23 IOPORT14 I+/O General-purpose input/output pin / SDO 7 Lch zero-flag output pin / Chip address setting input pin 2 24 IOPORT15 I+/O General-purpose input/output pin / SDO 7 Rch zero-flag output pin / Chip address setting input pin 3 25 VDD2 - +2.5 V digital power supply pin (for internal circuits) 26 VSS - Digital ground pin 27 SDO0 O PCM output pin 28 SDO1 O PCM output pin 29 SDO2 O PCM output pin 30 SDO3 O PCM output pin 31 SDO4 O PCM output pin 32 SDO5 O PCM output pin 33 SDO6 O PCM output pin 34 SDO7 O PCM output pin 35 IOPORT16 I+/O General-purpose input/output pin / Overflow detection output pin 36 IOPORT17 I+/O General-purpose input/output pin / Program end detection output pin 37 IOPORT18 I+/O General-purpose input/output pin / 64fs clock output pin 38 IOPORT19 I+/O General-purpose input/output pin / fs clock output pin 39 VDD1 - +3.3 V digital power supply pin (for input/output pin) 40 RAMD0 I+/O Data input/output pin for external memory 0 41 RAMD1 I+/O Data input/output pin for external memory 1 42 RAMD2 I+/O Data input/output pin for external memory 2 43 RAMD3 I+/O Data input/output pin for external memory 3 44 RAMD4 I+/O Data input/output pin for external memory 4 45 RAMD5 I+/O Data input/output pin for external memory 5 46 RAMD6 I+/O Data input/output pin for external memory 6 47 RAMD7 I+/O Data input/output pin for external memory 7 48 RAMD8 I+/O Data input/output pin for external memory 8 49 RAMD9 I+/O Data input/output pin for external memory 9


No. Name I/O Function 50 VDD2 - +2.5 V digital power supply pin (for internal circuits) 51 VSS - Digital ground pin 52 RAMD10 I+/O Data input/output pin for external memory 10 53 RAMD11 I+/O Data input/output pin for external memory 11 54 RAMD12 I+/O Data input/output pin for external memory 12 55 VDD1 - +3.3 V digital power supply pin (for input/output pin) 56 RAMD13 I+/O Data input/output pin for external memory 13 57 RAMD14 I+/O Data input/output pin for external memory 14 58 RAMD15 I+/O Data input/output pin for external memory 15 59 CASN O Column-address strobe output pin for external DRAM 60 RAMWEN O Write enable output pin for external memory 61 RAMOEN O Output-enable output pin for external memory 62 RASN O Row address strobe output pin for external DRAM 63 RAMA8 O Address output pin for external memory 8 64 RAMA7 O Address output pin for external memory 7 65 RAMA0 O Address output pin for external memory 0 66 RAMA6 O Address output pin for external memory 6 67 RAMA1 O Address output pin for external memory 1 68 VDD1 - +3.3 V digital power supply pin (for input/output pin) 69 RAMA5 O Address output pin for external memory 5 70 RAMA2 O Address output pin for external memory 2 71 RAMA4 O Address output pin for external memory 4 72 RAMA3 O Address output pin for external memory 3 73 RAMA9 O Address output pin for external memory 9 74 RAMA10 O Address output pin for external memory 10 75 VDD2 - +2.5 V digital power supply pin (for internal circuits) 76 VSS - Digital ground pin 77 RAMA11 O Address output pin for external memory 11 78 RAMA12 O Address output pin for external memory 12 79 RAMA13 O Address output pin for external memory 13 80 RAMA14 O Address output pin for external memory 14 81 RAMA15 O Address output pin for external memory 15 82 RAMA16 O Address output pin for external memory 16 83 RAMA17 O Address output pin for external memory 17 84 VDD1 - +3.3 V digital power supply pin (for input/output pin) 85 /CS Is Microprocessor interface Chip select input pin 86 SO Ot Microprocessor interface Data output pin 87 SI Is Microprocessor interface Data input pin 88 SCK Is Microprocessor interface Clock input pin 89 /IC Is Initial clear input pin 90 SDWCK I Word clock (fs) input pin for SDI/SDO interface 91 SDBCK Is Bit clock (64fs) input pin for SDI/SDO interface 92 SDI7 I PCM input pin 93 SDI6 I PCM input pin 94 SDI5 I PCM input pin 95 SDI4 I PCM input pin 96 SDI3 I PCM input pin 97 SDI2 I PCM input pin 98 SDI1 I PCM input pin 99 SDI0 I PCM input pin

100 VDD2 - +2.5 V digital power supply pin (for internal circuits)

I : Input terminal Is: Schmitt trigger input terminal I+: Input terminal with pull-up circuit (*) O: Digital output terminal Ot: 3-state digital output terminal A : Analog terminal


* Built in pull-up circuit cannot be used for Hi-level output of the LSI, because of this ability is only keep Hi-level for input pin when it is open. Depending on a circuit, please use pull-up resistance.

2.3 Pin Description 2.3-1 Serial Data Interface • SDI7-0

PCM data input pins for the YSS920B . Up to 16 channels of PCM data can be input. Connect unused pins to VSS. Select the input format by setting the SDI register.

• SDO7-0 Output pins for the PCM signal processed by the DSP. Up to 16 channels of PCM data can be output. Select the output format by setting the SDO register.

• SDBCK and SDWCK Clock input pins for SDI input and SDO output. Input clock signals at 64fs to SDBCK and fs to SDWCK. See section 3.3, “Serial Data Interface Format” for the serial data format.

2.3-2 External Memory Interface • RAMA17-0, RAMD15-0, RAMWEN, RAMOEN, CASN, and RASN

Pins for connecting the external memory for data delay. See section 5.4-5, “RAM Interface” for the access timing.

2.3-3 Microprocessor Interface • /CS, SCK, SI, and SO

Four-line serial interfaces for reading/writing of the control register and for program downloading. See section 3.4, “Microprocessor Interface Format” for the interface format.

2.3-4 General-Purpose Input/Output Pins • IOPORT19-0

IOPORT0 to IOPORT19 can be used as general-purpose input/output ports. Select whether to use the pins as input pins (IPORT) or output pins (OPORT) by setting the IOSEL 19-0 bits of the IOSEL registers (IOSEL_H, IOSEL_M, and IOSEL_L). If configured as an output pin (OPORT), you can select whether to output the value set to registers (OPORT_H, OPORT_M, and OPORT_L) or output various status signals by setting the OPSEL 19-0 bits of registers (OPSEL_H, OPSEL_M, and OPSEL_L). Functions of the IOPORT pins can be set as follows:


Note 1) Pins for chip address setting (IOPORT 15-12)

These pins are also used as chip address setting pins: IOPORT12----- chip address 0 (CA0) IOPORT13----- chip address 1 (CA1) IOPORT14----- chip address 2 (CA2) IOPORT15----- chip address 3 (CA3)

Note 2) ZEROF output pins (IOPORT 15-0) By setting the IOSEL and the OPSEL, IOPORT 15-0 operate as digital zero detection pins for SDO output signal. If the SD0 output signal remains at digital zero consecutively for the number of samples specified by the ZEROB register, the flag output pin of the corresponding channel is set to high. This flag output pin can be used for analog mute after DAC. The channels correspond to the pins as follows:

IOPORT0 ----- ZEROF0L (SDO0 Lch) IOPORT1 ----- ZEROF0R (SDO0 Rch) IOPORT2 ----- ZEROF1L (SDO1 Lch) IOPORT3 ----- ZEROF1R (SDO1 Rch) IOPORT4 ----- ZEROF2L (SDO2 Lch) IOPORT5 ----- ZEROF2R (SDO2 Rch) IOPORT6 ----- ZEROF3L (SDO3 Lch) IOPORT7 ----- ZEROF3R (SDO3 Rch) IOPORT8 ----- ZEROF4L (SDO4 Lch) IOPORT9 ----- ZEROF4R (SDO4 Rch) IOPORT10----- ZEROF5L (SDO5 Lch) IOPORT11----- ZEROF5R (SDO5 Rch) IOPORT12----- ZEROF6L (SDO6 Lch) IOPORT13----- ZEROF6R (SDO6 Rch) IOPORT14----- ZEROF7L (SDO7 Lch) IOPORT15----- ZEROF7R (SDO7 Rch)

Bit position IOSEL settingOPSEL setting

IOPORT function Remarks

11-0 0 -- General input (IPORT)IOPORT7-0 can be used for the conditional branching of DSP programs. See Note 4).

15-12 0 -- General input (IPORT)Combined use with chip address setting terminal.See Note 1).

19-16 0 -- General input (IPORT)

1 0 General output(OPORT)

IOPORT7-0 can be used for the conditional branching of DSP programs. See Note 4).

1 1 Zero detection output See Note 2)


1 1 Zero detection output See Note 2)


1 1 Status output See Note 3)

11-0

15-12

19-16


Note 3) Various status signal output pins By setting the IOSEL and the OPSEL, the following status signals will be output from each pin:

IOPORT16----- OVF IOPORT17----- END IOPORT18----- SDBCKO (64fs clock) IOPORT19----- SDWCKO (fs clock)

OVF If overflow occurs in the operation result of the DSP, OVF is set to high. The high interval is from the occurrence of the overflow to the output start of the next PCM sample from the SDO interface. When the next PCM sample output starts, OVF is reset to low. This pin is used for DSP programming and debugging.

END END is set to high when the DSP program counter is active. It is set to low when all processes have been finished and the program counter stops. When the program is operating correctly, the pin is always set to low once per sample. If it is not, this indicates that the program has not finished correctly to the end. This pin is used for DSP programming and debugging.

SDBCKO This pin outputs 64fs clock synchronized to the SDO output signal. This clock can be used as a 64fs clock for the devices in subsequent stages. The polarity of the SDBCKO clock can be selected by setting BCKOP of the SDO register.

SDWCKO This pin outputs fs clock synchronized to the SDO output signal. This clock can be used as an fs clock for the devices in subsequent stages. The polarity of the SDWCKO clock can be selected by setting WCKOP of the SDO register.

The structure of the LSI for each pin of IOPORT 19-0 is shown below:

IOPORT

IOSEL

Structure of the LSI

OPORT

or status signal

IPORT

Zero detection

pull-up circuit

OPSEL

Note 4) Branch condition setup When the pins are set to input mode, set a branch condition directly to each pin. When the pins are set to output mode, IOPORT output can be used as the branch condition.


2.3-5 Clock • XI and XO

Pins for connecting a crystal oscillator (12.288 to 15.000 MHz). Use a crystal oscillator with a fundamental wave. If an external clock is used, connect it to XI. Internal operation clock (ck) is set with the oscillating frequency of this crystal oscillator and the setting of the CKUP bit of the ERAM register.

• CPO, AVDD, and AVSS Pins for connecting external elements for the PLL used to generate a clock pulse in the DSP section. Connect a resistor and capacitors near the CPO as shown below. Connect decoupling capacitors near the pin between AVDD and AVSS.

CPO

4700 pF

1 kΩ

470 pF

AV

DD

AV

SS

+

10 µF 0.1 µF

+2.5 V

CKUP=0 CKUP=1 XI=12.288 MHz CK=30.72 MHz CK=40.96 MHz

: : : XI=14.000 MHz CK=35.00 MHz CK=46.66MHz

: : －

XI=15.000 MHz CK=37.50 MHz CK=50.00MHz

Chapter 3 Function Description - 13 -

Chapter 3 Function Description 3.1 Register Map

The YSS920B is controlled by reading/writing the registers below through the microprocessor interface (/CS, SCK, SI, and SO). See section 3.4, “Microprocessor Interface Format” for the microprocessor interface format. All the registers except addresses 0x13 and 0x14 are reset to 0 when initial clear (/IC=L) is executed. The initial values of addresses 0x13 and 0x14 are undefined.

Address Name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 CHIP ADR CAE CA3-0 0x01 SDI NOEXP SDIFMT1-0 SDIBIT1-0 SDWP SDBP 0x02 SDO SDOFMT1-0 SDOBIT1-0 WCKOP BCKOP0x03 ERAM CKUP RASREF ERAMMOD ERAMSEL1-0 0x04 IOSEL_H IOSEL19-16 0x05 IOSEL_M IOSEL15-8 0x06 IOSEL_L IOSEL7-0 0x07 OPSEL_H OPSEL19-16 0x08 OPSEL_M OPSEL15-8 0x09 OPSEL_L OPSEL7-0 0x0A OPORT_H OPORT19-16 0x0B OPORT_M OPORT15-8 0x0C OPORT_L OPORT7-0 0x0D IPORT_H IPORT19-16 0x0E IPORT_M IPORT15-8 0x0F IPORT_L IPORT7-0 0x10 MPCNT_H MPLOAD MPCLEARN DSPMUTEN MPCNT11-8 0x11 MPCNT_L MPCNT7-0 0x12 ZEROB ZEROB7-0 0x13 ZEROF_H ZEROF7R ZEROF7L ZEROF6R ZEROF6L ZEROF5R ZEROF5L ZEROF4R ZEROF4L0x14 ZEROF_L ZEROF3R ZEROF3L ZEROF2R ZEROF2L ZEROF1R ZEROF1L ZEROF0R ZEROF0L0x15 MI STATE MI7S MI6S MI5S MI4S MI3S MI2S MI1S MI0S 0x16 TEST 0x17 TEST 0x18

: Invalid Output of SO pin is set to high impedance. 0x1F 0x20 MI00 MI0REG31-24 0x21 MI01 MI0REG23-16 0x22 MI02 MI0REG15-8 0x23 MI03 MI0REG7-0 0x24 MI10 MI1REG31-24 0x25 MI11 MI1REG23-16 0x26 MI12 MI1REG15-8 0x27 MI13 MI1REG7-0 0x28 MI20 MI2REG31-24 0x29 MI21 MI2REG23-16 0x2A MI22 MI2REG15-8 0x2B MI23 MI2REG7-0 0x2C MI30 MI3REG31-24 0x2D MI31 MI3REG23-16 0x2E MI32 MI3REG15-8 0x2F MI33 MI3REG7-0 0x30 MI40 MI4REG31-24 0x31 MI41 MI4REG23-16

- 14 - Chapter 3 Function Description

Address Name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x32 MI42 MI4REG15-8 0x33 MI43 MI4REG7-0 0x34 MI50 MI5REG31-24 0x35 MI51 MI5REG23-16 0x36 MI52 MI5REG15-8 0x37 MI53 MI5REG7-0 0x38 MI60 MI6REG31-24 0x39 MI61 MI6REG23-16 0x3A MI62 MI6REG15-8 0x3B MI63 MI6REG7-0 0x3C MI70 MI7REG31-24 0x3D MI71 MI7REG23-16 0x3E MI72 MI7REG15-8 0x3F MI73 MI7REG7-0 0x40

: Invalid Output of SO pin is set to high impedance. 0x7E 0x7F DEVICE ID 0 0 0 0 0 0 1 0

Note

i) Do not write ‘1’ in the shaded area in the above table, because test bits are allocated. ii) Do not access addresses 0x16 and 0x17 because they are test registers.


3.2 Register Details

0x00 CHIP ADR Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

CAE CA3 CA2 CA1 CA0

This register can be written only immediately after the falling edge of /CS. Reading is valid only when CAE = 0 or CAE = 1 and IOPORT15-12 = CA3-0. When CAE = 1 and IOPORT15-12 ≠ CA3-0, the read data is set to high impedance.

• bit7: CAE This bit specifies whether to make the CA3-0 settings valid. This bit can be written only immediately after the falling edge of /CS. This bit is cleared (set to 0) when /CS is set high. 0: The CA3-0 settings are invalid. Reading and writing are possible on all registers of the YSS920B .

If only one device is used, set this bit to 0. 1: CA3-0 settings are valid. Reading and writing of the register are possible only when the values of

IOPORT15-12 pins and the CA3-0 settings of the register are the same. If multiple YSS920B s are used, setting this bit to 1 and setting the chip address of each device to IOPORT15-12 and CA3-0 allow /CS to be shared (no need to prepare /CS for each device). (When /CS is shared, the controlled device is switched by changing the CA3-0 settings. See section 4.2, “Peripheral Circuits (When Multiple YSS920Bs Are Used)”.) In this case, set IOSEL15-12=0 to set the IOPORT15-12 pins to input pins (IPORT). When CAE = 1, fix the values of the IOPORT15-12 pins.

When multiple devices are used and /CS is shared, be sure to set CAE = 1 immediately after the falling edge of /CS. If you read the register without setting CAE = 1, the SO pin output of each device will be shorted (because CAE = 0).

• bit3-0: CA3-0 Chip address setting bits that specify the access rights to the register at address 0x01 and following registers. This bit is valid only when CAE = 1 and can be written only immediately after the falling edge of /CS. • When the values of IOPORT15-12 pins and the CA3-0 settings are equal Reading and writing to the register at address 0x01 and following registers are possible. • When the values of IOPORT15-12 pins and the CA3-0 settings are not equal

Reading and writing to the register at address 0x01 and following registers are invalid and the output from the SO pin is set to high impedance.


0x01 SDI Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

NOEXP SDIFMT1 SDIFMT0 SDIBIT1 SDIBIT0 SDWP SDBP

• bit7: NOEXP This bit specifies whether the 4-bit exponent section of the 32-bit floating-point data input through the SDI interface is discarded and handled as 0.

0: Exponent is valid. The input data is a 32-bit floating-point data. 1: Exponent is invalid. The input data is a fixed-point data.

If the output data of the device that is connected to the SDI interface is of fixed-point format and the LSB bit and following bits are not 0s, set this bit to 1. If the output data of the device that is connected to the SDI interface is of fixed-point format and the LSB bit and following bits are 0s, set this bit to 0 or 1 (does not matter). If multiple YSS920B s are used and the data sent between the devices is of floating-point format, set this bit to 0.

• bit5-4: SDIFMT1-0 These bits specify the input format of the PCM input signal.

00: No delay format (left justified). 01: EIAJ format (right justified). 10: 1-bit delay format (left justified with 1-bit delay). 11: Invalid.

• bit3-2: SDIBIT1-0 These bits specify the data position when SDIFMT1-0 is 01 (right justified).

00: 16-bit mode. 01: 18-bit mode. 10: 20-bit mode. 11: 24-bit mode.

• bit1: SDWP This bit specifies the polarity of the SDI/SDO interface word clock (SDWCK).

0: SDI is Lch and Rch when the word clock is high and low, respectively. 1: SDI is Lch and Rch when the word clock is low and high, respectively.

• bit0: SDBP This bit specifies the polarity of the SDI/SDO interface bit clock (SDBCK).

0: The bit clock rises at the front of the input/output signal. 1: The bit clock rises in the middle of the input/output signal.

* See section 3.3, “Serial Data Interface Format” for a description of the SDI interface format.


0x02 SDO Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SDOFMT1 SDOFMT0 SDOBIT1 SDOBIT0 WCKOP BCKOP

• bit5-4: SDOFMT1-0 These bits specify the output format of the PCM output signal. The format and register bit assignment are the same as SDIFMT1-0.

00: No delay format (left justified). 01: EIAJ format (right justified). 10: 1-bit delay format (left justified with 1-bit delay). 11: Invalid.

• bit3-2: SDOBIT1-0 These bits specify the data position when SDOFMT1-0 is 01 (right justified). The format and register bit assignment are the same as SDIBIT1-0.

00: 16-bit mode. 01: 18-bit mode. 10: 20-bit mode. 11: 24-bit mode.

• bit1: WCKOP This bit specifies the polarity of SDWCKO clock (fs).

0: The polarity of SDWCKO is the same as that of SDWCK. 1: The polarity of SDWCKO is opposite to that of SDWCK.

The SDWCKO clock is output from the IOPORT19 pin by setting IOSEL19 =1 and OPSEL19 = 1. See “AC Characteristics” for details on the output timing.

• bit0: BCKOP This bit specifies the polarity of the SDBCKO clock (64fs).

0: The polarity of SDBCKO is the same as that of SDBCK. 1: The polarity of SDBCKO is opposite to that of SDBCK.

The SDBCKO clock is output from the IOPORT18 pin by setting IOSEL18 =1 and OPSEL18 = 1. See “AC Characteristics” for details on the output timing.


0x03 ERAM Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

CKUP RASREF ERAMMOD ERAMSEL1 ERAMSEL0

• bit7: CKUP This bit controls the DSP’s internal operating clock. The DSP’s internal operating clock can be changed by setting the XI pin input clock and this bit. 0: Normal mode

XI can be changed in the range of 12.288 MHz to 15.000 MHz. In this case, the DSP’s internal operating clock CK is related to XI as follows:

CK = XI*5/2 [MHz] 1: Clock up mode

XI can be changed in the range of 12.288 MHz to 15.000MHz. In this case, the DSP’s internal operating clock CK is 4/3rds of normal mode.

CK = (XI*5/2)*4/3 = XI*10/3 [MHz] The DSP’s internal operating clock can be varied in the range of 30.72 MHz to 50.00 MHz according to the CKUP setting and XI frequency.

XI Frequency CKUP Register CK External Memory 12.288MHz 0 30.72MHz DRAM/SRAM enable

: 0 XI*5/2 Only SRAM enable 15.000MHz 0 37.50MHz Only SRAM enable 12.288MHz 1 40.96MHz Only SRAM enable

: 1 XI*10/3 Only SRAM enable 14.000MHz 1 46.66MHz Only SRAM enable 15.000MHz 1 50.00MHz Only SRAM enable

The maximum number of steps that can be executed per sample time, maxSTEP, is expressed as follows: maxSTEP = CK/fs*1000-10

where fs is the sampling frequency in kHz and CK is the internal clock CK in MHz. And, the processing performance increases as the DSP’s internal operating clock is made faster. However, faster access time is also required of the memory. See the section of ERAMSEL1-0 (ERAM Register bit1-0) for details.

• bit3: RASREF Combined with DSPMUTEN, this bit forcibly performs “/RAS only refresh” on the external DRAM. “/RAS only refresh” is activated by setting DSPMUTEN = 0 and RASREF = 1. One cycle of “/RAS only refresh” is approximately 200 ns. Set RASREF = 0 when not performing “/RAS only refresh.”

[Note] Some DRAMs require a “/RAS only refresh” cycle as an initial cycle after power on. If so, carry out the following procedure. 1) Power on. 2) Set RASREF = 1 by setting DSPMUTEN = 0 and ERAMSEL = 00. 3) Set RASREF = 0 after waiting for the required cycles.


• bit2: ERAMMOD This bit specifies the data storage mode of the external RAM. This bit is valid for all modes, DRAM/SRAM/fast SRAM, regardless of the ERAMSEL setting.

0: Floating-point mode The data is converted into 32-bit floating-point format consisting of 4-bit exponent and 28-bit mantissa and stored to the external RAM. The 4-bit exponent and the higher 12 bits of the mantissa are input or output from the RAMD7-0 pins; the lower 16 bits of the mantissa are input or output from the RAMD15-8 pins. Use floating-point mode when in DRAM mode (ERAMSEL1-0 = 00) or when in SRAM/fast SRAM mode (ERAMSEL1-0 = 1*) using two SRAM of 8-bit data width or a SRAM of 16-bit data width.

1: Fixed-point mode The data is converted into 16-bit fixed-point format and stored to the external RAM. 16-bit fixed-point data is input or output from the RAMD7-0 pins in two steps. The RAMD15-8 pins are always 0s. In some cases, fixed-point mode may produce better sound quality than floating-point mode when in SRAM/fast SRAM mode (ERAMSEL1-0 = 1*) using a single SRAM of 8-bit data width.

31 4 3 030

Sign

MSB

LSB

ExponentMantissa

*2-3

*2-0

Bus Data

3 280 31 19 12

27 20 11 4

RAMD 7-0 RAMD 15-8

1st2nd

31 24

23 16

1st2nd

all 0all 0

ERAMMOD=0

ERAMMOD=1 ( via Linear Converter )

• bit1-0: ERAMSEL1-0 These bits specify the external RAM type and access mode.

00: DRAM mode DRAM of the following specifications can be connected for the external memory when the DSP’s internal operating clock CK is 30.72 MHz.

• 4 Mbits or more (262144 words or more * 16 bits) • Row address = A0-A8 or more and column address = A0-A8 or more • Refresh = 8 ms or more per 512 cycle • Fast page mode • Access time 60 ns or less • The delay from the rising edge of RAMOEN and CASN to the time when Read

DATA is set to high impedance is 20 ns or less. DRAM cannot be used when the DSP’s internal operating clock CK is 30.72 MHz or faster. Use floating-point mode (ERAMMOD = 0) when using DRAM mode. [Connection]

Connect the A0-A8, D0-D15, /WE, /RAS, /CAS of the DRAM to the RAMA0-RAMA8, RAMD0-RAMD15, RAMWEN, RASN, CASN pins of the YSS920B , respectively. Connect the /OE pin of the DRAM to the RAMOEN pin or GND of the YSS920B .


32-bit data is exchanged with the DRAM once every 6 clock cycles of the DSP’s internal operating clock. The maximum number of accesses at sampling frequency fs [kHz], maxACCESS, varies depending on the DSP’s internal operating clock CK [MHz] as follows:

maxSTEP = CK/fs*1000-10 maxACCESS = (maxSTEP-7)/6

01: Do not use. 10: SRAM mode

SRAM of the following specifications can be connected as the external memory. Note that the required access time varies depending on the DSP’s internal operating clock CK [MHz].

• One or two SRAMs of 2 Mbits or less (262144 words or less * 8 bits) • Or, one SRAM of 4 Mbits or less (262144 words or less * 16 bits) • The delay from the rising edge of RAMOEN to the time when Read DATA is set to

high impedance is 1000/CK [ns] or less. • Access time derived from the following equation is met.

3000/CK-30 [ns] [Example] 67 ns or less when CK = 30.72 MHz. 43 ns or less when CK = 40.96 MHz.

[Connection] Connect the A0-A17, D0-D7 (or D0-D15), /WE, and /OE pins of the SRAM to the RAMA0-RAMA17, RAMD0-RAMD7 (or RAMD0-RAMD15), RAMWEN, and RAMOEN pins of the YSS920B, respectively. Leave unused pins of the YSS920B open. When using one SRAM of 8-bit data width, 16-bit data is exchanged with the SRAM once every 6 clock cycles of the DSP’s internal operating clock. The maximum number of accesses at sampling frequency fs [kHz], maxACCESS, varies depending on the DSP’s internal operating clock CK [MHz] as follows:


11: Fast SRAM mode SRAM of the following specifications can be connected as the external memory. Note that the required access time varies depending on the DSP’s internal operating clock CK.

• One or two SRAMs of 2 Mbits or less (262144 words or less * 8 bits) • Or, one SRAM of 4 Mbits or less (262144 words or less * 16 bits) • The delay from the rising edge of RAMOEN to the time when Read DATA is set to

high impedance is 1000/CK [ns] or less. • Access time derived from the following equation is met.

2000/CK-30 [ns] [Example] 35 ns or less when CK = 30.72 MHz. 18 ns or less when CK = 40.96 MHz.

[Connection] Connect the A0-A17, D0-D7 (or D0-D15), /WE, and /OE pins of the SRAM to the RAMA0-RAMA17, RAMD0-RAMD7 (or RAMD0-RAMD15), RAMWEN, and RAMOEN pins of the YSS920B, respectively. Leave unused pins of the YSS920B open. When using one SRAM of 8-bit data width, 16-bit data is exchanged with the SRAM once every 4 clock cycles of the DSP’s internal operating clock. The maximum number of accesses at sampling frequency fs [kHz], maxACCESS, varies depending on the DSP’s internal operating clock CK [MHz] as follows:



[Note 1] Essentially, the same DSP program can be used in DRAM mode (ERAMSEL = 00) and SRAM mode (ERAMSEL = 10). However, note that in SRAM mode, write command immediately after the read cycle is prohibited. The DSP program for fast SRAM mode (ERAMSEL =11) cannot be used in SRAM mode.

[Note 2] If floating-point mode (ERAMMOD = 0) is specified using a single SRAM of 8-bit data width

in SRAM mode (ERAMSEL = 10) or fast SRAM mode (SRAMSEL = 11), the data is stored in 16-bit floating-point format consisting of 4-bit exponent and 12-bit mantissa. The mode, floating-point or fixed-point, that produces better sound quality varies depending on the DSP program. Check the actual sound to make the mode selection. If you connect the D0-D7 pins of another equivalent SRAM to the RAMD8-RAMD15 pins of the YSS920B and specify floating-point mode (ERAMMOD = 0), the data is stored in 32-bit floating-point format consisting of 4-bit exponent and 28-bit mantissa.

[Note 3] Position the external memory as close to the YSS920B as possible to minimize the wiring

capacitance.

0x04 IOSEL_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IOSEL19 IOSEL18 IOSEL17 IOSEL16

0x05 IOSEL_M Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IOSEL15 IOSEL14 IOSEL13 IOSEL12 IOSEL11 IOSEL10 IOSEL9 IOSEL8

0x06 IOSEL_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IOSEL7 IOSEL6 IOSEL5 IOSEL4 IOSEL3 IOSEL2 IOSEL1 IOSEL0

• IOSEL_H, bit3-0: IOSEL19-16 • IOSEL_M, bit7-0: IOSEL15-8 • IOSEL_L, bit7-0: IOSEL7-0

These bits select whether the general-purpose input/output pins IOPORT19-0 are used as input pins (IPORT) or output pins (OPORT). Set input or output for each pin separately.

0: The pin corresponding to the register bit is set to input (IPORT). [Example] If IOSEL0 = 0, the IOPORT0 pin is set to input. The signal input to the IPORT can be read through IPORT_H, M, and L registers.

1: The pin corresponding to the register bit is set to output (OPORT).

[Example] If IOSEL0 = 1, the IOPORT0 pin is set to output. The signal output from the OPORT pin varies depending on OPSEL19-0 of the OPSEL_H, M, and L registers.


0x07 OPSEL_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPSEL19 OPSEL18 OPSEL17 OPSEL16

0x08 OPSEL_M Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPSEL15 OPSEL14 OPSEL13 OPSEL12 OPSEL11 OPSEL10 OPSEL9 OPSEL8

0x09 OPSEL_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPSEL7 OPSEL6 OPSEL5 OPSEL4 OPSEL3 OPSEL2 OPSEL1 OPSEL0

• OPSEL_H, bit3-0: OPSEL19-16 • OPSEL_M, bit7-0: OPSEL15-8 • OPSEL_L, bit7-0: OPSEL7-0

These bits specify the type of signal output from the pins when IOSEL19-0 = 1 and the general-purpose input/output pins IOPORT19-0 are set to output pins (OPORT). Specify the signal for each pin separately.

0: The values set to OPORT19-0 of the OPORT_H, M, and L registers are output from the corresponding pins. [Example] If IOSEL0 =1 and OPSEL0 = 0, the value set to OPORT_L register OPORT0 is output from the IOPORT0 pin.

1: The following signal is output from the corresponding pin.

IOPORT0 ZEROF0L (SDO0 Lch zero flag) IOPORT1 ZEROF0R (SDO0 Rch zero flag) IOPORT2 ZEROF1L (SDO1 Lch zero flag) IOPORT3 ZEROF1R (SDO1 Rch zero flag) IOPORT4 ZEROF2L (SDO2 Lch zero flag) IOPORT5 ZEROF2R (SDO2 Rch zero flag) IOPORT6 ZEROF3L (SDO3 Lch zero flag) IOPORT7 ZEROF3R (SDO3 Rch zero flag) IOPORT8 ZEROF4L (SDO4 Lch zero flag) IOPORT9 ZEROF4R (SDO4 Rch zero flag) IOPORT10 ZEROF5L (SDO5 Lch zero flag) IOPORT11 ZEROF5R (SDO5 Rch zero flag) IOPORT12 ZEROF6L (SDO6 Lch zero flag) IOPORT13 ZEROF6R (SDO6 Rch zero flag) IOPORT14 ZEROF7L (SDO7 Lch zero flag) IOPORT15 ZEROF7R (SDO7 Rch zero flag) IOPORT16 OVF (Program overflow) IOPORT17 END (Program end) IOPORT18 SDBCKO (64fs clock) IOPORT19 SDWCKO (fs clock)


0x0A OPORT_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPORT19 OPORT18 OPORT17 OPORT16

0x0B OPORT_M Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPORT15 OPORT14 OPORT13 OPORT12 OPORT11 OPORT10 OPORT9 OPORT8

0x0C OPORT_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

OPORT7 OPORT6 OPORT5 OPORT4 OPORT3 OPORT2 OPORT1 OPORT0

• OPORT_H, bit3-0: OPORT19-16 • OPORT_M, bit7-0: OPORT15-8 • OPORT_L, bit7-0: OPORT7-0

When IOSEL19-0 = 1 and OPSEL19-0 = 0, the values set to OPORT19-0 bits are output from the corresponding IOPORT19-0 pins. [Example] If IOSEL0 =1 and OPSEL0 = 0, the value set to OPORT0 is output from the IOPORT0 pin. If IOSEL19-0 = 0, the IOPORT19-0 pins are set to input. Thus, the values set to OPORT19-0 are not output. If OPSEL = 1, various status signals are output. Thus, the values set to OPORT19-0 are not output.


0x0D IPORT_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IPORT19 IPORT18 IPORT17 IPORT16

0x0E IPORT_M Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IPORT15 IPORT14 IPORT13 IPORT12 IPORT11 IPORT10 IPORT9 IPORT8

0x0F IPORT_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

IPORT7 IPORT6 IPORT5 IPORT4 IPORT3 IPORT2 IPORT1 IPORT0

• IPORT_H, bit3-0: IPORT19-16 • IPORT_M, bit7-0: IPORT15-8 • IPORT_L, bit7-0: IPORT7-0

The data input to the IOPORT19-0 pins can be read through these registers when IOSEL19-0 = 0. [Example] If IOSEL0 = 0, the IOPORT0 pin input is set to the IPORT0 bit.

The data equal to the output of the IOPORT19-0 pins can be read through these registers when IOSEL19-0 = 1.

[Example] If IOSEL0 = 1 and OPSEL = 0, the value equal to OPORT0 is set to the IPORT0 bit. IPORT7-0 can be used for conditional branching of the DSP program. By setting IOSEL7-0 = 1, OPORT7-0 or ZEROF3R-0L can also be used for conditional branching. Note that if multiple YSS920Bs are used, IPORT15-12 also function as chip address setting pins. These registers are read-only.


0x10 MPCNT_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MPLOAD MPCLEARN DSPMUTEN MPCNT11 MPCNT10 MPCNT9 MPCNT8

0x11 MPCNT_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MPCNT7 MPCNT6 MPCNT5 MPCNT4 MPCNT3 MPCNT2 MPCNT1 MPCNT0

• MPCNT_H bit7: MPLOAD This bit is set when downloading data to the coefficient RAM, program RAM, and address RAM. After setting this bit to 1, set /CS to low to download the data sequentially from the address specified by MPCNT11-0. This bit is cleared (to 0) when /CS is set high. See section 3.5, “Program Download” for details.

• MPCNT_H bit6: MPCLEARN This bit is used to clear all registers coefficient RAM, program RAM, and address RAM to 0s. Set this bit to 0 after setting DSPMUTEN = 0 (or at the same time) and the aforementioned RAMs are cleared 150 s later (be sure to combine with DSPMUTEN = 0). When downloading data to the RAMs and during normal use, be sure to set this bit to 1.

• MPCNT_H bit5: DSPMUTEN This bit specifies whether to forcibly mute the SDO output.

0: Mutes the SDO7-0 output. 1: Disables the muting of the SDO7-0 output.

When DSPMUTEN is set to 0, the SDO7-0 output is muted, and, at the same time, the internal data RAM and external RAM are all cleared to 0. This bit does not clear the coefficient RAM, program RAM, and address RAM. The time it takes to clear the internal data RAM entirely is 70 s. The time it takes to clear the external RAM entirely is 26 ms. When downloading data to the coefficient RAM or address RAM, the DSPMUTEN can remain at 1. However, since noise may be generated depending on the DSP program, it is recommended that DSPMUTEN be set to 0 when downloading data. See section 3.5-5, “When Overwriting Only the Coefficient RAM” and 3.5-6, “When Overwriting Only the Address RAM.” Normally, when downloading program data to the program RAM, set DSPMUTEN = 0 in advance. Otherwise, noise may be generated in the SDO7-0 output. For the procedure of downloading the data with DSPMUTEN = 1, see section 3.5-7, “When Overwriting Only the Program RAM.”

• MPCNT_H bit3-MPCNT_L bit0: MPCNT11-0 These bits specify the load start address when downloading data to the coefficient RAM, program RAM, or address RAM (see section 3.5, “Program Download” for details).


0x12 ZEROB Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ZEROB7 ZEROB6 ZEROB5 ZEROB4 ZEROB3 ZEROB2 ZEROB1 ZEROB0

• bit7-0: ZEROB7-0 When the higher 24 bits of the mantissa of the SDO7-0 L/Rch output are 0s consecutively for the number of samples specified by this register, the ZEROF** register corresponding to the channel is set to 1. The ZEROF** register value is undefined after setting this register until the specified time elapses. The lower 4-bits of the mantissa of the SDO output and the exponent do not take part in the ZEROF** detection. Below is the relationship of this register and the number of samples used for zero detection.

00000000: 1 sample (when fs=44.1 kHz 0.000 s)00000001: 257 samples (when fs=44.1 kHz 0.006 s)00000010: 513 samples (when fs=44.1 kHz 0.012 s)

：： :11111111: 65281 samples (when fs=44.1 kHz 1.480 s)

(the number of samples) = (ZEROB7-0) * 256 + 1


0x13 ZEROF_H Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ZEROF7R ZEROF7L ZEROF6R ZEROF6L ZEROF5R ZEROF5L ZEROF4R ZEROF4L

0x14 ZEROF_L Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ZEROF3R ZEROF3L ZEROF2R ZEROF2L ZEROF1R ZEROF1L ZEROF0R ZEROF0L

• ZEROF_H bit7-ZEROF_L bit0: ZEROF7R-0L When the higher 24 bits of the mantissa of the SDO7-0 L/Rch output are 0s consecutively for the number of samples specified by ZEROB7-0, the bit corresponding to the output channel is set to 1. Otherwise, it is set to 0. The lower 4-bits of the mantissa of the SDO output and the exponent are discarded in the ZEROF** detection. Below is the relationship between the bits and channels. ZEROF7R --- SDO7 Rch ZEROF7L --- SDO7 Lch ZEROF6R --- SDO6 Rch ZEROF6L --- SDO6 Lch ZEROF5R --- SDO5 Rch ZEROF5L --- SDO5 Lch ZEROF4R --- SDO4 Rch ZEROF4L --- SDO4 Lch ZEROF3R --- SDO3 Rch ZEROF3L --- SDO3 Lch ZEROF2R --- SDO2 Rch ZEROF2L --- SDO2 Lch ZEROF1R --- SDO1 Rch ZEROF1L --- SDO1 Lch ZEROF0R --- SDO0 Rch ZEROF0L --- SDO0 Lch If IOSEL15-0 = 1 and OPSE15-0 = 1, the value of these register is output from the IOPORT15-0 pins. These registers are read-only.


0x15 MI STATE Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MI7S MI6S MI5S MI4S MI3S MI2S MI1S MI0S

• bit7: MI7S This bit controls the status of the MI70-MI73 registers (described later). Carry out the procedure below to read the MI70-MI73 registers.

1) Write 0 to MI7S. 2) Read MI7S.

MI7S = 0 indicates that the values of the MI70-MI73 registers have not yet been updated. MI7S = 1 indicates that the values of the MI70-MI73 registers have been updated.

3) After confirming that MI7S = 1, read the MI70-MI73 registers. When MI7S = 1, updating of the MI70-73 registers does not occur.

• bit6: MI6S This bit controls the status of the MI60-MI63 registers. The operation is the same as MI7S.








0x20 MI00 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MI0REG31 MI0REG30 MI0REG29 MI0REG28 MI0REG27 MI0REG26 MI0REG25 MI0REG24







• MI00 bit7- MI03 bit0: MI0REG31-0 By outputting the computed results of the internal DSP to this register, the results can be read via the microprocessor interface. How the results are used depends on the DSP program loading the results. If the DSP computed results are output in floating-point format, 4-bit exponent and 28-bit mantissa are output to MI0REG31-28 and MI0REG27-0, respectively (32 bits total). If the DSP computed results are output in fixed-point format, 0s and 28-bit fixed-point data are output to MI0REG31-28 and MI0REG27-0, respectively. Read these registers by controlling the MI0S bit of the MI STATE register. Using these registers allow debugging of the DSP program, level detection via the microprocessor, and so on. These registers are read-only.










• MI10 bit7- MI13 bit0: MI1REG31-0 These registers are similar to the MI00-MI03 registers. Read these registers by controlling the MI1S bit of the MI STATE register.






0x2A MI22 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x2B MI23 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0




0x2C MI30 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x2D MI31 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x2E MI32 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x2F MI33 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0




























0x3A MI62 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x3B MI63 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0




0x3C MI70 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x3D MI71 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x3E MI72 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0


0x3F MI73 Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0



0x7F DEVICE ID Register bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 0 0 0 0 0 1 0

• bit7-0 This register indicates the device ID. The device ID of the YSS920B is 0x02. This register is read-only.


3.3 Serial Data Interface Format The PCM signal is input/output via the SDI and SDO interfaces.

3.3-1 SDI Interface (Serial Data Input) Below are the serial data input formats according to the SDI register settings. The input signal from the SDI7-0 pins is always handled as 32-bit data consisting of 4-bit exponent and 28-bit mantissa regardless of the settings.

M L

SDWP=0

SDWP=1

SDBP=0

SDBP=1

SDIFMT1-0=00SDIBIT1-0=XX

SDIFMT1-0=10SDIBIT1-0=XX

SDIFMT1-0=01SDIBIT1-0=00




SDWCK

SDBCK

SDI7

SDI0

Lch Rch

1 Frame

M : MSB L : LSB

No Delay

LM

Lch RchM L LM

Mantissa Exponent Mantissa Exponent

L LM

Lch RchM L MML L

1bit Delay

L LM

LchM MM L

RchEIAJ

L

Rch

16 bits 16 bits

L LM

LchM MM L

RchL

Rch

18 bits 18 bits

L LM

LchM MM L

RchL

Rch

20 bits 20 bits

L LM

LchM MM L

RchL

Rch

24 bits 24 bits


3.3-2 SDO Interface (Serial Data Output) Below are the serial data output formats according to the SDO register settings. The SDO7-0 pins always output 32-bit data consisting of 4-bit exponent and 28-bit mantissa regardless of the format. If the SDO7-0 output is passed to another device such as a D/A converter, specify fixed-point (linear) output in the DSP program of the YSS920B. In addition, if multiple YSS920Bs are used, you can specify floating-point output to pass 32-bit data consisting of 4-bit exponent and 28-bit mantissa between the devices.

M L

SDWP=0

SDWP=1

SDBP=0

SDBP=1

SDOFMT1-0=00SDOBIT1-0=XX

SDOFMT1-0=10SDOBIT1-0=XX

SDOFMT1-0=01SDOBIT1-0=00




SDWCK

SDBCK

SDO7

SDO0

Lch Rch

1 Frame

M : MSB L : LSB

No Delay

LM

Lch RchM L LM

Mantissa Exponent Mantissa Exponent

L LM

Lch RchM L MML L

1bit Delay

L LM

LchM MM L

RchEIAJ

L

Rch

16 bits 16 bits

L LM

LchM MM L

RchL

Rch

18 bits 18 bits

L LM

LchM MM L

RchL

Rch

20 bits 20 bits

L LM

LchM MM L

RchL

Rch

24 bits 24 bits


3.4 Microprocessor Interface Format Reading and writing of registers are performed through the four-wire serial interface indicated below.

3.4-1 When /CS Is Used Only By One Device

A1A0 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Don't CareDon't Care

A1A0 A2 A3 A4 A5 A6 Don't Care Don't CareDon't Care

R/W

R/W

D0 D1 D2 D3 D4 D5 D6 D7

High impedance

High impedance Highimpedance

/CS

SCK

SI

SO

SO

SI

write R/W = L

read R/W = H

SO is set to output mode only when all of the conditions below are met. • /CS=L • Read operation on a valid address setting • During (8-bit) data output timing

In all other cases, the interface is set to high impedance, and SO, SI, and SCK can be shared with devices having similar interfaces. If multiple YSS920Bs are used, /CS can be shared by specifying the CHIP ADR registers CA3-0. See section “3.4-2”.

If the general-purpose output pins (IOPORT19-0) are used as input pins (IPORT), the value of the IOPORT (IPORT) during the “R/W” period indicated above is read from the SO pin. If used as output pins (OPORT), the output of the IOPORT (OPORT) switches at time “D7” indicated above.

[Note] Set /CS = high during initial clear (/IC = low).


3.4-2 When /CS Is Shared with Multiple Devices

When multiple YSS920Bs are used or /CS is shared with other LSI, be sure to set CAE=1 and CA 3-0 immediately after the falling edge of /CS as shown in the following figure. For details, refer to “0x00 CHIP ADR Register” description in the section 3.2 Register Details.

write R/W = L

read R/W = H

A0 A5 A6 D7A4A3A2A1CA3-0R/W CAE D0 D5 D6D4D3D2D1R/W

/CS

High-Z

SCK

SI

SO

Don’t Care Don’t Care

A0 A5 A6

D7

A4A3A2A1CA3-0R/W CAE

D0 D5 D6D4D3D2D1

R/W

High-Z

SI

SO

Don’t Care Don’t CareDon’t Care

High-Z

A setup of CAE=1 and CA 3-0 isperformed by access after the fallingedge of /CS.

Address=0x00

Address=0x00

[Note] Set /CS = high during initial clear (/IC = low).


3.5 Program Download The YSS920B is controlled by writing program data to the coefficient RAM, program RAM, and address RAM via the microprocessor interface.

3.5-1 MPCNT and RAM Address The program data is written from the RAM address specified by MPCNT11-0. Below is the relationship between MPCNT11-0 and RAM address. MPCNT11-0 = 000000000000(0) Address 0 of the coefficient RAM MPCNT11-0 = 000000000001(1) Address 1 of the coefficient RAM : : MPCNT11-0 = 001111111111(1023) Address 1023 of the coefficient RAM -------------------------------------------------------------------------------------------------------------- MPCNT11-0 = 010000000000(1024) Address 0 of the program RAM MPCNT11-0 = 010000000001(1025) Address 1 of the program RAM : : MPCNT11-0 = 011111111111(2047) Address 1023 of the program RAM ------------------------------------------------------------------------------------------------------------- MPCNT11-0 = 100000000000(2048) Address 0 of the address RAM MPCNT11-0 = 100000000001(2049) Address 1 of the address RAM : : MPCNT11-0 = 100011111111(2303) Address 255 of the address RAM

3.5-2 Basic Download Procedure Below is the basic download procedure. 1) Set MPCNT7-0 of the MPCNT_L register. 2) Set MPCNT11-8 of the MPCNT_H register and set MPLOAD = 1, MPCLEARN = 1, and

DSPMUTEN = 0. 3) Set MPLOAD = 1 and then load the program data with /CS set to low. 4) After the last data is loaded, set /CS to high. MPLOAD is automatically cleared. 5) Set DSPMUTEN = 1 to clear the output mute. Note that if /CS is set to high after setting MPLOAD = 1 before downloading the program data, MPLOAD will be cleared to 0, and you will not be able to download the program.


3.5-3 Basic Download Format Pins used in downloading data are the /CS, SCK, and SI pins of the microprocessor interface. Load the data LSB first according to the format shown below.

SCK/CS

SIADR=0x10

MPCNT_H RegisterW

MPCNT8-11 set,MPCLEARN=1,MPLOAD=1,

DSPMUTEN=0

MPCNT8-11

/CS=0 Downlaod DataSet MPLOAD bit of the MPCNT_H Register

↑ LSB of the start address dataspecified by MPCNT11-0

↑MSB of the last data

The coefficient RAM data is written to the RAM each time 16 bits are transferred. SCK

SIData at address (N) of the

coefficient RAM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

LSB MSB

Data at address (N-1) of thecoefficient RAM

Data at address (N+1) of thecoefficient RAM

0 1 2 3 4 5 6 7 8 9 10 11 127 8 9 10 11 12 13 14 15

The program RAM data is written to the RAM each time 56 bits are transferred. However, the valid data is 50 bits from bit 49 to 0. Since the values from bit 55 to 50 are discarded, they can be 0 or 1. SCK

SIData at address (N) of the program RAM

0 1 2 3 4 5 6 7 8 9 43 44 45 46 47

LSB MSB

Data at address (N-1) of theprogram RAM

Data at address (N+1) of theprogram RAM

0 150 51 52 53 54 55 48 49 50 51 52 53 54 55 2 3 4494847

The address RAM data is written to the RAM each time 24 bits are transferred. However, the valid data is 17 bits from bit 16 to 0. Since the values of bit 23 to 17 are discarded, they can be 0 or 1. SCK

SIData at address (N) of the address RAM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

LSB MSB

Data at address (N-1) of theaddress RAM

Data at address (N+1) of theaddress RAM

0 116 2 3 41615 17 18 19 20 21 22 23 17 18 19 20 21 22 23

The data at coefficient RAM address 1023 and program RAM address 0 can be written consecutively without having to reset MPCNT11-0. In this case, write the MSB (bit 15) of coefficient RAM address 1023 and the LSB (bit 0) of program RAM address 0. Likewise, program RAM address 1023 and address RAM address 0 can also be written consecutively.


3.5-4 Download Procedure When Overwriting the Program The basic procedure of overwriting the DSP program entirely is to set MPCNT11-0 = 0 and load the entire data from coefficient RAM address 0 to address RAM address 255. However, if the program data consists mostly of 0s, the program can be overwritten more quickly by using MPCLEARN as described below. For example, assume the following DSP program to be downloaded.

• Only coefficient RAM address 0-20 are used. All other addresses are 0s. • Only program RAM address 0-100 are used. All other addresses are 0s. • Only address RAM address 0-30 are used. All other addresses are 0s.

In this case, download the data according to the procedure below.

1) Set DSPMUTEN of the MPCNT_H register to 0 to mute the output. Set MPCLEARN = 0 and wait 150 µs. This act clears all of the coefficient RAM, program RAM, and address RAM to 0s.

2) Set the MPCNT_L register to MPCNT7-0 = 00000000. 3) Set the MPCNT_H register to MPCNT11-8 = 0000 (coefficient RAM address 0) and set

MPCLEARN = 1 and MPLOAD = 1 (keep DSPMUTEN at 0). 4) After setting MPLOAD = 1, load the data of coefficient RAM address0-20 with /CS set to low. 5) Set /CS to high. MPLOAD is automatically cleared. 6) Set MPCNT_L register to MPCNT7-0 = 00000000. 7) Set the MPCNT_H register to MPCNT11-8 = 0100 (program RAM address 0) and set

MPCLEARN = 1 and MPLOAD = 1 (keep DSPMUTEN at 0). 8) After setting MPLOAD = 1, load the data of program RAM address0-100 with /CS set to low. 9) Set /CS to high. MPLOAD is automatically cleared. 10) Set MPCNT_L register to MPCNT7-0 = 00000000. 11) Set the MPCNT_H register to MPCNT11-8 = 1000 (address RAM address 0) and set

MPCLEARN = 1 and MPLOAD = 1 (keep DSPMUTEN at 0). 12) After setting MPLOAD = 1, load the data of address RAM address0-30 with /CS set to low. 13) Set /CS to high. MPLOAD is automatically cleared. 14) Set DSPMUTEN = 1 to clear the output mute.

3.5-5 When Overwriting Only the Coefficient RAM When overwriting the data of the coefficient RAM such as when changing the filter coefficient, the coefficient can be changed with DSPMUTEN = 1. This allows smooth change in the characteristics without pause in the sound output. For example, when overwriting only address 15, 16, and 17 of the coefficient RAM, carry out the procedure below.

1) Set MPCNT_L register to MPCNT7-0 = 00001111. 2) Set the MPCNT_H register to MPCNT11-8 = 0000 (coefficient RAM address 15) and set

MPLOAD = 1 and MPCLEARN = 1. Keep DSPMUTEN at 1. 3) After setting MPLOAD = 1, load the data of coefficient RAM address 15, 16, and 17 with /CS

set to low. 4) Set /CS to high. MPLOAD is automatically cleared.


3.5-6 When Overwriting Only the Address RAM As with the coefficient RAM, when overwriting the data of the address RAM such as when changing the delay value, the address value can be changed with DSPMUTEN = 1. This allows smooth change in the characteristics without pause in the sound output. For example, when overwriting only address 5 to 10 of the address RAM, carry out the procedure below.

1) Set MPCNT_L register to MPCNT7-0 = 00000101. 2) Set the MPCNT_H register to MPCNT11-8 = 1000 (address RAM address 5) and set MPLOAD

= 1 and MPCLEARN = 1. Keep DSPMUTEN at 1. 3) After setting MPLOAD = 1, load the data of address RAM address 5 to 10 with /CS set to low. 4) Set /CS to high. MPLOAD is automatically cleared.

3.5-7 When Overwriting Only the Program RAM The basic procedure of overwriting the program RAM is to do it with DSPMUTEN = 0 (sound output muted). However, it is possible to overwrite the program data without muting the output by downloading the data while checking the END status signal (program end detection output). Below is a procedure for an example in which program RAM address 20 to 100 are overwritten without muting the sound output.

1) Set IOSEL17 = 1 and OPSEL17 = 1 and get the END information from the IOPORT17 pin. Connect the IOPORT17 pin to the microprocessor interrupt pin so that it can be checked.

2) Set MPCNT_L register to MPCNT7-0 = 00010100. 3) Set the MPCNT_H register to MPCNT11-8 = 0100 (program RAM address 20) and set

MPLOAD = 1 and MPCLEARN = 1. Keep DSPMUTEN at 1. 4) Load the MPend (program end) command to program RAM address 20 (it is a good idea to

write a DSP through output program at address 0 to 19. It is also a good idea to set address 21 and 22 to NOP, because the MPend command is executed in 2 steps after it is issued).

5) After loading the data at address 20, wait until END changes from low to high. When it does, load the data at program RAM address 21 (it is a good idea to set address 21 and 22 to NOP, because the MPend command is executed in 2 steps after it is issued).

6) Repeat step 5 until address 100 is reached. 7) After loading address 100, load the NOP command at address 20. This activates the command

at address 20 to 100. The procedure above only allows a maximum of one address data to be written within a sample period. Therefore, the time to load the data takes longer than the case when data is loaded by muting the sound output. [Note] When overwriting the coefficient RAM, program RAM or address RAM with DSPMUTEN = 1, the internal data RAM and external RAM (RAMs that are cleared with DSPMUTEN = 0) are not cleared. Note that this may produce noise in the output depending on the contents of the overwriting data.

Chapter 4 Basic Design Example - 45 -

Chapter 4 Basic Design Example This chapter describes the basic system configuration using the YSS920B by giving examples.

4.1 Peripheral Circuits (When One YSS920B Is Used) Below is the basic connection example when one YSS920B is used.

YSS920B(EVE)

DA

C, D

SP

etc

XI

HOSTPROCESSOR

/CS

SC

K SI

SO

XO

SD

BC

K

SD

WC

K

SDO0

SDO2

SDO3

SRAM or DRAM(option)

12.288-15.0MHz

CP

O

1kO

4700pF

RA

MD

15-0

CA

SN

RA

SN

RA

MW

EN

RA

MO

EN

RA

MA

17-0

/IC/IC

470p

F

SDO1

SDO4

SDO6

SDO7

SDO5

SDI0

SDI2

SDI3

SDI1

SDI4

SDI6

SDI7

SDI5

AD

C, D

SP

, DIR

etc

64fs

fs

• When only one YSS920B is used, you do not have to set the chip address (CA3-0). • Since the SO pin is sometimes set to high impedance, a pull-up resistor may be necessary depending

on the system configuration. • If a bit clock with inverse polarity is needed in the peripheral devices such as and ADC or DAC, set

IOSEL18 = 1, OPSEL18 = 1, and BCKOP = 1 and use the SDBCKO output from the IOPORT18 pin.

- 46 - Chapter 4 Basic Design Example

4.2 Peripheral Circuits (When Multiple YSS920Bs Are Used) Below is the basic connection example when multiple YSS920Bs are used.

YSS920B(EVE)

XI

HOSTPROCESSOR

/CS

SC

K SI

SO

XO

SD

BC

K

SD

WC

K

SDO0

SDO2

SDO3


12.288-15.0MHz

CP

O

1kO

4700pF

RA

MD

15-0

CA

SN

RA

SN

RA

MW

EN

RA

MO

EN

RA

MA

17-0

/IC

470p

F

SDO1

SDO4

SDO6

SDO7

SDO5

SDI0

SDI2

SDI3

SDI1

SDI4

SDI6

SDI7

SDI5

64fs

fs

YSS920B(EVE)

XI

/CS

SC

K SI

SO

XO

SD

BC

K

SD

WC

K

SDO0

SDO2

SDO3


12.288-15.0MHz

CP

O

1kO

4700pF

RA

MD

15-0

CA

SN

RA

SN

RA

MW

EN

RA

MO

EN

RA

MA

17-0

/IC

470p

F

SDO1

SDO4

SDO6

SDO7

SDO5

SDI0

SDI2

SDI3

SDI1

SDI4

SDI6

SDI7

SDI5

IOP

OR

T1 5

IOP

OR

T1 4

IOP

OR

T1 3

IOP

OR

T1 2

IOP

OR

T1 5

IOP

OR

T1 4

IOP

OR

T1 3

IOP

OR

T1 2

/IC

• You can share /CS by setting the chip address (CA3-0) to the IOPORT15-12 pins. To switch the device to be controlled, overwrite the register address 0x00 (CA3-0) setting as necessary. See below for the example in the figure above.

To control the left device, set CAE = 1 and CA3-0 = 0000. To control the right device, set CAE = 1 and CA3-0 = 0001.

• If a bit clock with inverse polarity is needed in the peripheral devices such as and ADC or DAC, set IOSEL18 = 1, OPSEL18 = 1, and BCKOP = 1 and use the SDBCKO output from the IOPORT18 pin.

• Since the SO pin is sometimes set to high impedance, a pull-up resistor may be necessary depending on the system.

Chapter 4 Basic Design Example - 47 -

4.3 Clock Connection for High fs The SDO signal is output slightly delayed with respect to the SDBCK input clock as specified in section 5.4-4, “Serial Data Interface.” Therefore, if the sampling frequency (fs) is high (above 96 kHz), there is a possibility that, when SDBCK and SDWCK are connected to each device in parallel such as in the “Peripheral Circuits” described before, the data will not be transmitted correctly to certain devices that are connected after the YSS920B due to the SDO output delay. In such cases, supply the SDBCKO and SDWCKO outputs of the YSS920B to the subsequent device as shown below. SDBCKO and SDWCKO are output from IOPORT 18 and 19, respectively, by setting the IOSEL_H register and OPSEL_H register. The polarities of SDBCKO and SDWCKO are set with BCKOP and WCKOP, respectively. For timing details, see section 5.4-4, “AC Characteristics” of the YSS920B and the AC characteristics of the connected devices.

YSS920B(EVE)

DA

C, D

SP etc

SDB

CK

SDW

CK

SDO0

SDO2

SDO3

SDO1

SDO4

SDO6

SDO7

SDO5

SDI0

SDI2

SDI3

SDI1

SDI4

SDI6

SDI7

SDI5

AD

C, D

SP, DIR

etc

64fs

fsIO

POR

T1 8IO

POR

T1 964fs

fs

- 48 - Chapter 5 Electrical Characteristics

Chapter 5 Electrical Characteristics 5.1 Absolute Maximum Ratings Item Symbol Condition Min. Typ. Max. Unit

Power supply voltage VDD1 AVDD VDD2

VSS -0.5VSS -0.5VSS -0.5

VSS+4.6 VSS +3.6 VSS +3.6

V V V

Input voltage VI Pins other than XI pin *1 XI pin

-0.5

-0.5

VSS +5.75

VDD1+0.5

V

V Storage temperature Tstg -50 125 °C

*1 Using a 5-V tolerant input pin.

5.2 Recommended Operating Conditions Item Symbol Condition Min. Typ. Max. Unit

Power supply voltage VDD1 AVDD VDD2

Internal Operation Frequency 30.72MHz ~ 50.00MHz

3.0 2.3 2.3

3.3 2.5 2.5

3.6 2.7 2.7

V V V

Operating temperature Top -40 25 85 °C

5.3 DC Characteristics Condition: Under recommended operating conditions

Item Symbol Condition Min. Typ. Max. Unit

Input voltage high level (1) VIH1 *1 0.7 VDD1 V Input voltage low level (1) VIL1 *1 0.3 VDD1 V Input voltage high level (2) VIH2 *2 2.4 V Input voltage low level (2) VIL2 *2 0.8 V Input voltage high level (3) VIH3 *3 2.2 V Input voltage low level (3) VIL3 *3 0.8 V Output voltage high level VOH IOH = -80 µA VDD1-0.4 V Output voltage low level VOL IOL = 1.0 mA 0.4 V Input leak current (1) ILI1 Applies to all input pins

other than pull-up pin. ±10 µA

Input leak current (2) ILI2 Applies to pull-up pin. +10／-90 μA Power consumption (VDD1) PD1 *4 45 65 mW Power consumption (VDD2

/AVDD) PD2 *4 120 145 mW

*1 Applies to the XI input pin. *2 Applies to the /IC input pin. *3 Applies to the input pins other than above. *4 Power consumption largely depends on the DSP program, DSP internal operation clock, and other

items to be operated. Values listed above are measured under the following conditions:

・ 50.00 MHz DSP internal operation clock ・ fs=96 kHz data input to SDI7-0 pins ・ Using SRAM (ERAMSEL1-0=10) as external RAM ・ Using a YAMAHA evaluation board ・ Using programs that are assumed to produce a high level of processing (maximum number of

steps, frequent access to external RAM) The standard values are obtained at VDD1=3.3 V and VDD2=AVDD=2.5 V. The Maximum values are obtained at VDD1=3.6 V and VDD2=AVDD=2.7 V.

Chapter 5 Electrical Characteristics - 49 -

5.4 AC Characteristics Condition: Under recommended operating conditions

5.4-1 Clock No. Item Symbol Condition Min. Typ. Max. Unit

1 XI clock frequency fxin 12.288 15.000 MHz 2 XI clock duty Xduty 40 60 % 3 PLL lock frequency fxpll fxin×10 MHz 4 PLL lock-up time tlpll 900 µs

CKUP = 0

12.288 MHz ≤ fxin ≤ 15.000 MHz26.66 1/( fxpll/4) 32.55 ns

5 CK (Internal operation clock)

tckc CKUP = 1

12.288 MHz ≤ fxin ≤ 15.000 MHz20.00 1/(fxpll/3) 24.41 ns

5.4-2 Power-on / Hardware Reset No. Item Symbol Condition Min. Typ. Max. Unit

6 /IC low time ticl *1 1 ms *2 0 1 s

7 Power-on time *4 tV1V2 *3 -1 1 s

*1: Be sure to set /IC to L at power-up. Set /IC to H 1 ms after VDD1, VDD2, and AVDD of the power supply

and XI input have stabilized. Also, the initial setting of the control register and the downloading of programs shall be started 1 ms after setting /IC to H.

*2: When a Schottky barrier diode is not connected

The 3.3 V power supply (VDD1) voltage should be higher than the 2.5V power supply (VDD2 and AVDD) voltage at anytime (at the time of power on and power off).


*3: When a Schottky barrier diode is connected Insert a Schottky barrier diode with a forward voltage of 0.4 V or less between the 3.3 V power supply

(VDD1) and 2.5 V power supply (VDD2 and AVDD) (cathode is VDD1 and anode is VDD2). Power on and power off order do not matter and it do not need to care voltage relation for the 3.3 V power supply and the 2.5 V power supply.

*4: The time lag of power ON or OFF between 3.3V power supply and 2.5V power supply must be within one

second. Only one power keeps on supplying, LSI would be damaged.

5.4-3 Microprocessor Interface No. Item Symbol Condition Min. Typ. Max. Unit

1 SCK cycle tcc 160 ns 2 SCK rise time tcr 20 ns 3 SCK fall time tcf 20 ns 4 SCK high level time tch 80 ns 5 SCK low level time tcl 80 ns 6 /CS, SI setup time tset 10 ns 7 /CS, SI hold time thold 50 ns 8

9 SO delay time /CS high level time

tdelaytcsnh

CL=50 pF

160

50

ns ns

3 4

1

6

SCK

25

/CS

SO

6 7

SI

7

4

9

8High impedance

(when reading)

High impedance

See section 3.4, “Microprocessor Interface Format” for the conditions in which SO is set to high-impedance.


5.4-4 Serial Data Interface No. Item Symbol Condition Min. Typ. Max. Unit

1 SDBCK input frequency fbck 2 12.3 MHz 2 SDBCK rise time tibr 20 ns 3 SDBCK fall time tibf 20 ns 4 Input setup time tis 5 ns 5 Input hold time tih 10 ns 6 Output delay time from

input clock tiodly CL = 50 pF 50 ns

7 Clock delay time tbdly CL = 50 pF 50 ns 8 Output delay time from

output clock toodly CL = 50 pF -10 10

9 SDBCKO rise time tobr CL = 50 pF 20 ns 10 SDBCKO fall time tobf CL = 50 pF 20 ns

SDBCK

2

1

3

SDI7-0

4 5

SDBCKO

7

9

10

SDWCK

4

SDWCKO

SDO7-0

6

8

5

• SDBCKO will be output from the IOPORT18 pin by setting IOSEL18=1 and OPSEL18=1. • SDWCKO will be output from the IOPORT19 pin by setting IOSEL19=1 and OPSEL19=1. • When SDBP=1, the polarity of SDBCK is inverted. • When BCKOP=1, the polarity of SDBCK becomes opposite to SDBCKO. • When WCKOP=1, the polarity of SDWCK becomes opposite to SDWCKO.


5.4-5 RAM Interface In ERAMSEL 1-0=1* (SRAM/high speed SRAM mode) (CL=20 pF)

No. Item Symbol Condition Min. Typ. Max. Unit

(When reading) 1 Read cycle trc ERAMSEL1-0 = 11 tckc×2 ns ERAMSEL1-0 = 10 tckc×3 ns 2 Data input setup time tdis 20 ns 3 Data input hold time tdih 0 ns 4 Address delay time tad 10 ns (When writing) 5 Write cycle time twc ERAMSEL1-0 = 11 tckc×2 ns ERAMSEL1-0 = 10 tckc×3 ns 6 Address setup time tas 0 ns 7 Write pulse width twp ERAMSEL1-0 = 11 tckc×1 ns ERAMSEL1-0 = 10 tckc×2 ns 8

9 10

Write recovery time Data output delay time Data output hold time

twr tdod tdoh

0

0

8

ns ns ns

Note) See section 5.4-1, “Clock” for details on tckc (=internal operation clock cycle time).

RAMA17-0

RAMWEN

RAMOEN

RAMD15-0

(when reading)

1

2 3

4

(when writing)

5

6 7 8

9 10


When ERAMSEL 1-0=00 (DRAM mode) (CL=20 pF) No. Items Symbol Condition Min. Typ. Max. Unit 1 Setup time for Row address tras 5 ns 2 Hold time for Row address trah 10 ns 3 RASN pulse width trpw 115 ns 4 RASN pre-charge time trpt 55 ns 5 Setup time for Column address tcas 5 ns 6 Hold time for Column address tcah 40 ns 7 CASN pulse width tcpw 40 ns 8 CASN pre-charge time tcpt 10 ns 9 CASN access time tcat 30 ns

10 Access time from Column address taat 45 ns 11 Access time from RASN trat 60 ns 12 Hold time for read data trdh 0 ns 13 Setup time for write data twds 5 ns 14 Hold time for write data twdh 40 ns 15 Setup time for write command twcs 5 ns 16 Hold time for write command twch 40 ns 17 CASN high-RASN low delay time tcrd 40 ns 18 Refresh cycle time trc RASREF=1 200 ns

Note) Set the internal operation clock cycle time tckc to 32.55 ns (30.72 MHz) in DRAM mode.

(when reading)

RAMA8-0

RAMWEN

RAMOEN

RAMD15-0

1

9

ROW COLUMN COLUMN

2 5 56 6

CASN

RASN

3 4

7 78

109

101112 12

17


(when writing)

RAMA8-0

RAMWEN

RAMOEN

RAMD15-0

1

ROW COLUMN COLUMN

2 5 56 6

CASN

RASN

3 4

7 78 17

15 16

13 1314 14

(during /RAS only refresh (RASREF = 1))

CASN

RASN

3 4

17

18

Chapter 6 Package Dimensions - 55 -

Chapter 6 Package Dimensions

- 56 - APPLICATION NOTES

APPLICATION NOTES * Warning for the device which makes sound using speaker A speaker radiates heat in a voice-coil by air flow accompanying vibration of an oscillating board. When DC signal (several Hz or less *) is inputted, heat radiation characteristics falls rapidly. In addition, even if it is used lower than rated input, it may lead to disconnection of a voice-coil, emitting smoke or ignition of a speaker. In order to avoid such situations, be sure to implement one or more preventive measures from the following. 1. Do not select a setup (sound production) which may generate DC signal.

(Since thoroughness of this preventive measure is generally difficult, we recommend the combined use with the following 2, 3, and 4)

2. Add a DC cut digital filter for cutting DC signal into a digital section.

(As long as "Built-in" is not mentioned in the manual, there is no such built-in circuit inside of a device).

3. Add a DC cut capacitor for cutting DC signal into an analog section.

(When addition is specified in the example of a recommended circuit diagram, be sure to add) 4. When a latter stage device exists in the signal path from this device to speaker, DC cut is realized

in a latter stage device. In addition, the above-mentioned measures are made that the device it-self, DC cut condenser, and a latter stage device will be in a normal operation. Therefore, it is also necessary to implement the safety measures supposing failure of these parts * separately.

The specifications of this product are subject to improvement changes without prior notice.Notice

Documents

YSS920B APPLICATION MANUAL - pudn.comread.pudn.com/downloads154/sourcecode/asm/682421... · 70 RAMA2 O Address output pin for external memory 2 71 RAMA4 O Address output pin for external