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Z80-SIOProduct Specification Z80A-SI0

General Description

The Z80-SIO (Serial Input/Output) is a dual-channelITII. !ti-function peripheral cornponent designed to satisfya wide variety of.serial data conimunications require-ments in microcomputer Systems. Its basic function is a serial-to-parallel, parallel-to-serial converter/controller,Jul-within that role-it is configurable by Systemssoftware so its “personality” can be optirnized for agiven serial data cornrnunications application.

The Z80-SI0 is capabie of handling asynchronousformats. synchronous byte-oriented protocols such asIBM Bisync, and synchronous bit-oriented protocolssuch as HDLC and SDLC. This versatile device can also beused to support virtually any other serial protocol forapplications other than data cornrnunic’ations (cassetteor floppy disk interfaces. for example).

The Z8O-SI0 can generate and check CRC Codes inany synchronous mode and can be programmed tocheck data integrity in various modes. The device alsohas facilities for modern controls in both channels. Inapplications where these controls arc not needed, themodern controls can be used for general-purpose VO.

Fig. 8 - SI0 BLOCK DIAGRAM

Structure

m N-channel silicon-gate depletion-load technologyn 40-pin DIP

m Single S V power supplyw Single-Phase 5 V clockm All inputs and Outputs TTL compatible

Features

Two independent full-duplex channelsData rates in synchronous or isosynchronous rnodes:l 0-50OK bits/second with 2.5 MHz System

clock ratel O-800K bits/second with 4.0 MHz System

clock rate

Receiver data regisrers quadruply buffered; trans-rnitter doubly buffered. Asynchronous features:l 5, 6. 7 or 8 bits/character

Z8040Z80A-SI0

Z-8O SIO Pin Description

l 1, I % or 2 srop bitsl Even. odd or no parityl x 1. x 16. x32 and x64 clock modesl Break generation and detecrionl Parity. overrun and framing error detection

m Binary synchronous features:l Internal or external Character synchronization

‘ l One or IWO sync characters, in separate registersl Automatic sync Character insertion/deletionl CRC generation and checking

n HDLC and SDLC features: ,. Abort sequence generation and detectionl Automatic zero insertion and deletionl Autbmatic flag insertion between messages9 Address‘field recognition. Support for one to eight bits/characterl Valid receive messages protected from overrun. CRC generation and checking

l Interrupt features:

Pin Description

l Daisy-chain interrupt logic provides automaticinterrupt vectoring with no external logic

l Prograrnmable interrupt vectorl Status Affects Interrupt Vcctor mode for fast

interrupt processing

n CRC-16 or CRC-KITT block frame checkn Separate modern control inputs and Outputs for both

channelsm Modem Status tan be monitored ’

DO-DT. Qsrcm Duru Bus (bidirectional. 3-state). TheSystem dara bus Iransfers dara and commands betweenthe CPV and the Z80-SIO. 00 is rhe least significant bit.

B/n. CkonneI A Or E St& (inpur. High selects Chan-nel B). This input defines which channel is accessedduring a data t ransfer between the CPU a n d t h eZ80-SIO. Address bit Ao from the CPU is oftcn used forthe selection function.

CIE. Con~rol Or Dutu Selecr (inpur. High Sekts Con-trol). This input defmes the type of information trans-fer pcrformed between the CPC and the Z80-SIO. AHigh at this input during a CPC write to the Z80-SI0Causes the information on the data bus IO be interpretedas a command for the chatinel selected by EI/:. A Low at~8 means rhat the information on the data bus is data.Address bit Al is often used for this function.

CE. Chip Enuble (input. activc Low). A Low level atthis input enables the Z80-SI0 to accept command ordzita input from the CPU during a write cycle, or C Otransmit data IO the CPU during a read cycle.

r#. Sysrem Glock (input). The ZBO-SI0 uses the stand-ard Z80 System Glock to synchroniie internal Signals.This is a smgle-Phase clock.

Mi. Muchine Cyc/e One (input frorn ZSO-CPU, activeL o w ) . U’hen z is active and G is also active, theZIO-CPU is fetthing an instruction from memory; whenMi is active while e is active, the ZSO-SI0 accepts Mi

-FIG. 9 - 280~SlO/O PIN CDNFIGURATION FIG. 10- Z80-SIOll PIN CONFIGURATION

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28040Z80A-SI0

Z-80 SI0 Pin Description

and E as an interrupt acknouledge if the DO-SI0 isthe highest priority device that has interrupted thezso-CPU .

IORQ. Inpur/Oulpur Reques/ (input from CPU. activeLew). IORQ is used in conjunction with BiÄ.‘C/E. z

-lnd R6 10 transfer commands and dara beiween the CPU--and the 28030. When CE, RD and RT@ are all active,the channel selected byE,Ä transfers data to the CPU (aread Operation). When CE and K are active, but E isinactive, the channel selecred by B .x is written to by theCPU wich either data or control information as specifiedbv c-6. As mentioned oreviouslv. if E and .G are ac-,tive simultaneously. the CPU is acknowledging an inter-rupt and the 280~SI0 automatically places itsinterruptvector on the CPU data bus if it is the highest prioritydevicc requesting an interrupt.

RD. Reud Cycle Srurus. (input from CPU. active Low).If K is active. a memory or VO read Operation is inprogress. 3 is used with B/Ä, r?)? and E Co Iransferdata from the Z80-SI0 to the CPU.

RESFT. Rcser (input. active Low). A Low RESET dis-ables both receivers and transmirters, forces TrDA a n dTXDB marking. forces the modern controls High and dis-abla all interrupts. The control registers must be re-written afta the ZBO-SI0 is reset and before data istransmitted or received.

IEI. Infempr Enuble In (input, active High). This sig-nal is used with IE0 IO form a priority daisy chain whenthere is more than one interrupt-driven device. A High

on this line indicates that no other device of higher pri-ority is being serviced by a CPU interrupt Serviceroutine.

IEO. Inrerrupr Enobk Our (output, active High). IE0is High only if IE1 is High and the CPL’ is not servicing aninterrupt from this ZSO-SIO. Thus, this Signal blockslower priority devices from interrupting while a higherpriority device is beirigg serviced by irs CPIJ interrupt ser-vice routine.

INT. /n(ert-upt Requexr (output, open drain, activeLow). When the Z8OSIO is requesring an interrupt, itpulls INT Low.

W/RDi’A. W/RDYB. WuiUReady A , Wait/Ready B(Outputs, open drain when programmed for Wait func-tion, driven High and Low when programmed forReady function). These dual-purpose Outputs may beprogrammed as Ready lines for a DHA controller or asWait lines that synchronize the CPC to the ZBO-SI0 datarate. The reset state is open drain.

?%Ä, m. C/eur To S e n d (inputs, active Low).When programmed as Auto Enables, a Low on theseinputs enables the respective transmitter. If not pro-grammed as Auto Enables, these inputs may be pro-grammed as general-purpose inputs. Both inputs areSchmitt-trigger buffered to accommodate slow-risetimeSignals. The ZBO-SI0 detects pulses on these inputs andinterrupts the CPU on both logic Ievel transitions. TheSchmitt-trigger buffering does not guarantee a specifiednoise-level margin.

FIG. 11 - 280.SlO/2 PIN CONFIGURATION

280~SI0Z80A-SI0

Z-SO SI0 Bonding Options--DCDA, DC‘DR. Data Currier Derpct (inpur<. acIiveLw). Thev pin5 funcIion ar receher cnable5 i f IhcZRO-SI0 ix programmed Tor Auto Enablej; othcrtiserhry may bz ured as general-purpore input Pins. BoIhplnr are Schmitt-Irigger buffered Io accommadate SIOH-risetime signal5. The ZSO-SI0 detects pulse5 on therepinc and it?Ierruptr Ihe CPI: on both logic le\el transi-tlonc. Schmitr-trigger buffering d o e r no1 guaranree a5pecific noire level margin.

- - RxDA, R\DB; Receive Dora ( inpu ts , acIive H i g h ) .

TxDA, TxDB. 7”unsmir D a t a (Outputs, actixe High).- -RKA, RxCB. Receiver Clocks (inputj). Receive data1s sampled on Ihe rising edge of RK. The ReceiLe Clocksmay be 1, 16, 32 or 64 rimes the dara r a t e In Asyn-chronous modes. These clocks may be driven by theZBO-CTC Counter Timer Circuit Tor programmablebaud rate generation. Both inputs arc Schmirt-triggerbuffered (no noise level margin is specified). See theiollowing secrion for bonding options.- -TxCA, TxCB. Tronsmifler C l o c k s (inpurs). TXDchanges on Ihe falling edge of ??. In Asynchronousmodes, the TransmitIer Clocks may be 1, 16, 32 or 64times [he data rate; however, the clock multiplier for Ihet;ans/nitter and [he receiver must be the Same. T h eTrammit Glock inpuls-sre SchmiII-trigger buffered forrelaxed rise- and fall-time requiremenrs (no noise levelmargin is specified). Transmitter Clocks may be drivenby the ZIO-CTC Counter Timer Circuit for program-mahle baud rate generarion. See the following sectionfor bonding Options.

m, &?%. Request To Send (ou~purs. acli\e Lew).LVhen Ihe RTS bi1 is sel. the E output goes Los. Whenthe RTS bit is reset in Ihe Asynchronous mode. the oul-pur goer H i g h after [he Iransmiller is empty. In Syn-chronous modes. Ihe RTS pin strictly follows Ihe state of

-rhe RTS bit. Both pins tan be used as general-purposeoulpuls;

m, m. Dato Termins/ Re0d.v (outputs. active1.0~). See note on honding Option5 These oufputs fol-low the Slafe programmed into the DTR bit. They tanalte he programmed as general-purpose outpufs.

-7SYNC A. SYYC B. S~v~chroni:o/ion (inputs/ouIpuIs.actike Low). These pins tan acr either as inputs or out-Puls. In the .45ynchronous Receiue mode. they are in-puts ~imilar Io <y and MI). In this mode. the Iransi-tions on these lines affect rhe staIe of [he Sync/HunI5tatu5 biis in RRO. In Ihe Extemal Sync mode, these linesal5o ac1 ar inputs. When external synchronization isachieved. 5yuC must be drl\en Low on the second risingedge of R\C after that riring edge 01 R\C on ahich Ihelast bit of the sync character was received. In otherNords, afrer the sync Pattern is detected, the extemallogic must uait for two full Receise Glock cycles IO acti-

-_\ate Ihe CIV Input. Once ~3 i5 forced LOK. it is wiceI O kerp it LW uinil thc KP\ informr the extemal s y n clogic IhaI slnchronizarion has been lost or a new mes-5age i5 abour Io Start. Character a5cembly beglns on theriring edgc of RI(. that immediatcly precedec the fallingedge of \x in Ihe Extemal Sync mode.

In Ihe Inrernal S:nchronization mode (slonosyncand Birync), there pmc act as ourputs that are activeduring Ihe part of Ihe receive clock IGG?I cycle in whichcync characters are recognized. The sync condition isno1 latched, 50 Ihese Outputs arc active each time a syncPattern is recognized. regardles of characrer bounda-rier.

Bonding Options

The constrainls of a j0-pin package make i1 impossibleIo bring out the Receive Glock. Transmit Ciock. DataTerminal Ready and Sync signal; for both channels.Therefore. Cbannel B must sacrifice a Signal or havetwo Signals bonded together. Since user rcquirementsvary. three bonding oprions arc offered:

l Z80-SlO/O has all four Signals, but fxCB and Rmare bonded together (Fig. 9).

-l Z80-SIO/I sacrifices fi and keeps TXCB, an

and SZ (Fig. IO).- -

l Z80-YO/2 sacrifices SYNCB and keeps TxCB, RXCBand m (Fig. 1 1 ).

Architecture

The device internal structure includes a ZBO-CPU inter-face, internal control and inIerrup1 logic, and two full-dupley channels. Esch channel conrains read and writeregisrers, and discrere control and Status logic that pro-LIdes the inrerface IO modems or oIher extemal devica.

The read and write register group includes five 8-bitcontrol registers. IWO sync-Character registers and IwoStatus registerc. The interrupt vector is written into an

‘additional N-bit register (WriIe Register 2) in Channcl Bthat may be read through Read Register 2 in Channel B.The regibters for both channel5 arc designated in the Iextas follows:

U’RO-WR? - Write Registers 0 through 7RRO-RR? - Read Registers 0 through 2

The bit assignment and functional grouping of cachregister is configured Io simplify and organize the pro-gramming-procecs. Table I lirts the functions as5ignedto.each read or write rcgicter.

280410z 80A-SI0

2-80 SI0 Architecture

- - - - --..I---WR0 Register poinlers. C R C initializq. inilialuatlon corn-

mands for fhe various modes. etc---_W R , Transnvtlflecewe mlerrupl snd.dala Iransfer m o d e -

deftniliop.WR2 Inlerrupl reclor (Channel B only)WR3 Recewt parame!ers and controlWR4 TransmitlRtceive miscellaneous parame!ers a n d

modes-.-~ ~-WR5 Transmll paramelers and conlrolsWR6 Sync chatacler or SDLC address Feld --~-~--~~_._._ ~.WR7 Sync character or SDLC flaa

H’rk Regirser Fuacdoas

Tabk 1. Functional Assignmcnls of Rcnd and H’riccRegisters

The logic for both channels provides formats. syn-chronization and Validation Tor data transfcrrcd IO andfrom thc channcl intcrface. The modern control inputsClear to Send tTTS) and Data Carrier Detect ~ncn) arcmonitored by the discrete control logic undcr programcontrol. A,ll the modern control Signals arc general pur-pose in nature and tan be used for functions other thanmodern control.

For automatic interrupt vectoring. the interrupt con-trol logic determines which channel and which deviccwithin the channel has the highest priority. Priority isfixed with Channel A assigned a higher priority thanChannel B; Receive, Transmit and External Status in-terrupts are prioritized in that Order within each chan-nel.

FIG. 12 -TRANSMIT AND RECEIVE DATA PATH

28040Z80A-SI0

‘Z-80 SI0 ArchitedureData Path

The transmit and rcceive dara path illustrated for Chan-ne1 A in Flpure 12 is identical Tor both channeI\. Thereceiver has three 8-bit buffer registers in a I-KW ar-rangement in addition IO tb a-bit receive shift repitter.This scheme createc additional time for the CPU IO ser-vice an inrerrupt at the bepinning of a block of-high-speed daia. Incoming data is routed through one o fseveial paths (data or CRC-1 depending on the selecredmode and-in Asynchronouc modes-the Characterlength.

The transmitter has an 8-bit transmit data registerthat is loaded from the internal data bus. and a ?O-bittransmit shift register thar tan be loaded from the syncCharacter buffers (u’R~ and hR7) or from the transmitdata register. Depending on the operational mode, out-going data is routed rhrough one of four main pathsbefore it is transmitted from the Transmit Data Output(TxD).

Functional Description

The funcrional capabilities of the Z80-SI0 tan bedescribed from WO different Points of view: as a datacommunications device. it transmits and receives serialdata, and meets the requirements of barious data com-munications protocols; as a 280 family peripheral. itinteracts with the ZBO-CPU and other 280 peripheralcircuits, and shares the data, address and controlbusses. as weil as being a part of the 280 interrupt struc-ture. As a peripheral to other microprocessors, theZSO-SI0 offers valuable features such as non-vectoredinterrupts, polling and simple handshake capability.

The first part of the following functional descriptiondescribes the interaction between the CPC and Z80-90;the second parr inrroducer its data communicationscapabilities.I/O Interface Capabilities

-The Z80-SI0 offers the choice of Polling. Interrupt(vectored or non-vectored) and Block Transfer modes 10transfer daia, Status and control information to andfrom the CPI-. The Block Transfer mode tan be im-plemented under CPU 01 Dv4 conuol.

Polling. There are no interruptc in the Polled mode.Status registers RRO and RRI are updated at a,ppropriatetimes for each function beirigg performed (for example,CRC Error Status valid at [he end of the message). ,411the interrupt modes of the ZSO-SI0 must be disabled tooperate the debice in a polled environment.

While in its Polling sequence, the <PL’ eltamines theStatus contained in RRO for each channel; the RRO statusbits Serbe as an acknowledge to the Pol1 inquiry. Thetwo RRO status bits ~0 and DZ indicate that a daratransfer is needed. The Status also indicates Error orother special \tatus conditions (See “ZRO-SI0 Program-ming”). The Special Recei\e Condiiion ctalus contained

in RRI does no1 havc Io he read in a Polling requencebecau\e rhe \tatu\ bit\ in RKI mu\t hc accompanied by aReceive Character Available SI~IU\ in RRO.

Interrupts. The Z80-SI0 offers an elaborate interruptscheme IO probide fa\t interrupt response in real-tlmeapplications. Channel B regirters WR? and RRZ containthe interrupt bector thar polnts !o an interrupt Serviceroutine in the memory. To service operationc in bothchannels and IO eliminate the necessir) of writinp aSIRIUS analytis routine. the Z80-SI0 tan modify the in-terrupt yeclor in RR? so it points directly to orte of eightinterrupt service routines. this is done under programcontrol by setting a program bit WRI. D?) in Channel Bcalled “Status Affects Vector.” When 16s bit is sei, theinterrupt vector in WR? is modified according IO theassigned priority of the various interrupting conditions.The table in the Write Register 1 description (280.SI0Programming section) Shows the modiftcation details.

Transmit interrupts. Receive interrupts and ExternaVStatus interrupts are the main sources of interrupts.Esch interrupt Source is enabled undir program controlwith Channel A having a higher priority than ChannelB. and with Receiver, Transmit and Elternal/Statusinrerrupts prioritized in that Order within each channel.When the Transmit interrupt is enabled, the C-PL is‘interrupted by the transmi! buffer becoming empty.(This implies that the transmitter must have had a datacharacler written into it so it tan become empty.) Whenenabled, the receiver tan interrupf the CPU in one ofthree ways:

l Interrupt on the first reteived Characterl Interrupt on all received charactersl Interrupt on a Special Receive condition

Interrupt On First Character is typically ured with rheBlock TJansfer mode..lnterrupt On All Receibe Charac-ters has the Option of modifying the interrupt vector inthe event of a parity err& The Special Receibe Condi-tion interrupt tan occur on a ch’aracter or message baris(End Of Frame interrupt in SDLC, for e’tample). TheSpecial Receive condition tan Cause an interrupt only ifthe Interrupt On First Receite Character or InterruptOn .AII Receive Characters-mode is \elected. In InterruptOn First Receive Character, an interruft tan occur fromSpecial Receive conditions (exccpt Parity Error) afrert h e firrl receive character infelrupt (csamplc: RcceiveOberrun interrupt).

The main function of the E\ternal/Status interrupt isIO monitor the Signal transitions of the c%, E andsj x Pins; however. an External/Status interrupt is alsocauted by a Transmit Underrun condition or b> thcdetrction of a Break (As>nchronour mode) or Abort(st>l.c mode) sequence in the data stream. The interruptcaused by the Break/Abort \r&tence hat a special fea-turc thar allous the ZRO-SI0 to interrupt when theBreaklAbor sequence ic detected or tcrminated. T h i sfeatu.re facilitates the proper termination of the currentmessage. correct initialiiaiion of the next message. and

56

2 8O=SIOz 80A40

Functional Descriptionthc accurate timing of the Break/Abort condition in ex-ternal logic.

In Asynchronous modcs, the sm pin may be pro-grammed for an input (hat tan bc used for functionssuch as monitoring a ring indicator.

CPU/DMA Block Transfer. The Z80-SI0 provides aBlock Transfer modc IO accommodate cpu block trans-fer functions and ~514 Controllers (Z80-DMA or otherdesigns). The Bloch Transfer mode UFCS the WAITIREADY ouiput in conjunction with the Wait/Ready bitsof W’ritc Register 1. The W’AIT’READY out~u! tan bedcfined under softwar< control as a iKiT line in thc CPL’.

Block Transfer mode or as a READY li& in the DMABlock Transfer mode.

To a DCA Controller, rhe ZRO-SI0 READY ourpuf in-dicates that the Z80-SI0 is ready IO transfer data to orfrom memory. To the CPU, the WAIT output indicatesthat thc ZBO-SI0 is not ready to transfer data, therebyrequesting the CPC to extend the I/O cycle. The pro-gramming of bits 5, 6 and 7 of Write Register I and thelogic Stares of the wAIT/READY line are defined in theWritc Register I description (ZSO-Si0 Programmingscction).

Data Communicntions Cnpnbilities

In addition IO thc 110 capabilities previously discussed,the Z80-SI0 providcs IWO independent full-duplexchannels that tan bc programmed for use in Asynchro-nous. Synchronous and SDLC (HDLO modes. These dif-ferent modes are providcd to facilitate the implementa-tion of commonly uscd data communications protocols.The following is a short description of the data com-munications protocols supported by the Z80-30. Amorc dctailcd explanation of these modes tan be foundin thc Z80-SI0 Technical Manual.

Asynchronous Mods. Tbc Z8OSIO offcrs-transmissionand reception of five to eight bits per Character, plus op-tional evcn or odd parity. The transmitter tan supplyone. one and a half or two stop bits per Character andtan provide a break output at any time. The receiver

break dctcction logicinterrupts the CPU only at the start-and end of a received break. Reception is protected

from Spikes by a transicnt Spike rejection mechanismthat Checks thc signal.onc-half a bit time after a Lowlevel is dct’ected on the Receive Data input. If the Lowdocs not persist-as in the case of a transicnt-the char-acter asscmbly process is not started.

Framing errors and ovcrrun crrors arc detected andbuffercd rogcther with thc partial Character on whichthcy occurred. Vectored interrupts allow fast servicingof error conditions using dedicated routincs. Further-more, a built-in chccking process avoids interpreting aframing crror as a ncw Start bit: a framing error resultsin the addition of one-half a bit time to thc Point atwhich thc search for the next starr bit is bcgun.

The Z8OSIO does not rcquire symmctric Transmitand Rcccivc Glock Signals-a feature that allows it Io bcused. with a ZBO-CTC or any other clock Source. Thetransmittcr and rccciver tan handle data at a rate of 1.1116. 1132 or 1164 of the clock rate supplicd to t h cRcccivc and Transmit Glock inputs.

Synchronous Modcs. The ZSO-SI0 supports both byte-oricnted and bit-oriented synchronous communication.Synchronous byte-oriented prorocols tan be handled inseveral modes that allou Character synchronization withan S-bit sync Character (Monosync), any Io-bit sync pat-tern (Bisync), or uith an extemal sync Signal Leadingsync characters tan he removed uithout intcrrupting theCPU. CRC checking for synchronous b y t e - o r i e n t e dmodes is delayed by one Character time so the CPU mayditable CRC checking on tpecific characters. This per-mits implementation of protocols such as tß\t Bisync.

B o t h CRC-16 (Xrs+ Xts+ X-‘+ 1) a n d CCITT(Xts+ Xtz t Xs + 1) error checking polynomials are sup-ported. In all nOWSDLC modes, the CRC generator is in-itialized IO 0’s; in SDLC modes, it is initializcd to 1’s.(This means that the Z80-SI0 cannot generate or checkCRC for IBM-compatible soft-sectorcd disks.) TheZBO-SI0 also provides a feature that automaricallytransmits CRC data when no other data is available fortransmission. This allows very high-speed transmissionsundcr DMA control with no need for CPU intervention atthe end of a message. When therc is no’data or CRC tosend in Synchronous modes, the transmitter inserts 8- orl6-bit sync characters regardlcss of the programmedCharacter length. Sincc the CPU tan read Status informa-tjon from the Z8OSIO. it tan determine thc type oftransmission (data, CRC or sync characters) that is tak-ing place at any timt.

The Z80-SI0 supports synchronous bit-oriented pro-tocols such as SDLC and HDLC by performing automaticflag scnding, zero insertion and CRC generation. A spe-cial command tan be uscd to abort a frame in transmis-sion. The Z80-SI0 automatically transmits the CRC andtrailing flag when the transmit buffer becomes empty.An interrupt warns thc CPU of this Status Change so anabort may be issucd if a transmitter undcrrun has oc-curred. Onc IO eight bits per Character tan be sent,which allows transmission of a message exactly asreceived with no Prior information about the Characterstructure in the information field of a framc.

The receiver automatically synchronizes on the lead-ing flag of a frame and provides a synchronization sig-nal [hat tan bc programmcd to intcrrupt. In addition,an intcrrupt on the first rcceivcd Character or on everyCharacter tan be selectcd. The rcccivcr automaticallydeletes all zeroes inserted by the transmittcr during char-acter assembly. lt also calcularcs and automaticallyChecks the cRc to validate framc transmission. At [heend of transmission. the Status of a received framc isavailablc in thc Status registers. The receiver tan be pro-grammed IO scarch for frames addressed IO only a spcci-fied user-sclectablc address or to a global broadcast ad-dress. In this modc, framcs that do not match thc user-

57

zeo-ao-.iZ80A-SIO'

sclectcd or broadcast addrcss arc ignored. The AddressSearch modc providcs Tor a singlc-bytc address rccog-nizable by thc hardware. Tbc numbcr of addrcss bytcstan be extcndcd undergoftware control.

Tbc ZEO-SI0 tan bc convcnicntly uscd under DMAcontrol to providc high-Speed rcccption. Tbc Z80-SI0tan interrupt the CPU whcn the first Character of a mes-sage is rcccived. Tbc CPL’ thcn cnables thc DMA to trans-fer the messagc IO memory. The ZSO-SI0 then issues anEnd Of Frame interrupf and the CPU Checks the Status

-h_ of the receivcd mcssage. Thus. thc CPU is freed for otherService while thc mcssage is bcing ieceived. A similarschcme allous message tiansmission undcr DMA con-trol.

Z80-SI0 Programming

T o program the ZEO-SiO, thc System program firstissues a scrics of commands thaf initialize the basicmodc of Operation and then other commands that qual-ify conditions within thc selected modc. For cxamplc,the Asynchronous mode. Character Icngth. clock rate,number of stop bi&, even or odd pririty arc Brst Set,then thc in te r rupt modc and, finally, receiver o rtransmittcr cnablc. Tbc WRI Parameters must be issuedbcforc any othcr Parameters arc issued in thc initializa-

i tion routinc.

Borh channcls contain command registers that mustbc programmed via the System progr’am Prior to opera-tion. Tbc Channel Select input (BI& and the Control/Data input (~6 are the command structurc addressingcontrols, and are normally controlled by the C~ii ad-dress bus. Figure 14 illustratcs thc timing rclationshipsfor programming the write registers, and transferringdata and Status.

Write Registers .

fi- Tbc ZSO-SI0 conta ins c ight registcrs (WRO-WR71 i ncach channcl that are programmed separately byt h e System program t o configure t h c functionalpersonality of thc channels. With thc exception ofWRO. programming thc write registers requires twobytcs. The first bytc contains three bits (DO-D21 thatpoint IO the selectcd register; the sccond byre isthc actual control word that is writtcn into thercgister to configure thc ZBO-90.

WRO is a spezial casc in tha t a l l thc basic com-mands (CMD,-CMD2) tan be acccsscd with a Singlebytc. Reset ( i n t e r n a l o r external) ‘initializes t h cpoinlcr bits DO-D2 10 Point IO H’RO.

Resd Registers

Tbc ZSO-SI0 contains thrcc regislers, RRO-RR2 (Figurel?).thar tan bc rcad IO obtain thc Status information foreach channcl (except Tor RR? - Channcl B only). Tbc

status information includcs error conditions, interruptvector and Standard communiations-interfacc Signals.

To rcad the contents of l selected rcad registero t h e r t h a n RRO, t h e systm program m u s t f i r s twrite the Pointer byte IO WRO in cxactly thc ramcway as a writc register ogreration. Then, by cx-ecuting an input instruction. thc contents of theaddressed read register tan b-e rcad by the CPU.

T h e Status bits of RRO a n d RRI are carcful lygroupcd to simplify Status monitoring. For cxam-ple. when the interrupt mtor indicates that aSpecial Rcceive Condition iatcrrupt has occurrcd,all the appropriate error. l6s.s tan be rcad from. aSingle register (RRI).

FIG. 12 - READ REGISTER BIT FUNTIONS

MAO REGISTER 0

REAO REGISTER 1 I

READ REGISTER 2

58

28040z8oA-sIo

F I G . 1 3 - W R I T E R E G I S T E R B I T FUNCTIO~S

Z-SO SI0 Programming

WRITE REGISTEII 0 WRITE REGISTER 4

R E G I S T E R 0REcNER 1RfGlSlER 2REGISTER 3RE'GISTER ‘REGISTER5ylmlg; ;

: : : *UUcODESENDMORl SDLCI

: ;0 nEaTEX1 Sbr"S INTERRUPTSt CHMNE1 nistr

10

0 ENAWINTON YEKT n, CWRlCRR

; 1RE= TIIWT PENDING

: ERRORRESEl.1 1 1 Rfllm FROH IWT(cn-AoNLYlNULL COOERESET Ra CRC CHECKERRESETTI CRC GENER4RRREftT rr UNDEARUWEWLATCH

B0 SIWC MODES fYABLE

:I STOPSllCCH4n4C~En

/: 1

1'1 STOP UTS CH4R4CTER2 STOP UTS r,HARACTER

i0 8 BIT SING CR4R4C7ER

2,16 UT SING cn4nAcm

1 1SDLC MOGE (01111110 FLIG!EXTEFINAL SVNC MODE

!0 Xl CLOCI MODE

iX16 CLOCK MODE

1 1XU CLOCK MODE161 CLOCK MODE

WRITE REGISTER 1 WRITE REGISTER 5

-WRITE REGISTER 2 (CHANNEL U ONLY)

WAKE REGISTER 3

I I: 0 na na 3 7 mmCWRACRn UTS oun4crfn

1 : In 6 UTSCYAR4CRn1 I na I UTS cbun~crfn

_--

WRITE REGISTER 6

-4190 SOLC mnfss FIEL0

'KM SOLCI, Y"ST,E PROGRAYMEDTO 0,111110 FOR FtAG RECOGNITIOII

TI cnc EN4ELIfmSTi-EtRC.16TI ENAOLESEND onf4K

SVNC Ul 0SVNC BIT ISVNC Ul 2

1svw Ul 5

::;: M: :SYNC Ul 6SYNC Oll 7 I

i

59

28040Z80A-SI0

Synchrontius Modes (continued)

2-80 SI0 TimingTiming

Rend Cycle. The timing Signals gcnerated by a Wrlte Cycle. Figure IJh illustrates the timing and daraZOO-CPU input insrruction Io read a Data or Status byte Signals generated by a ZSO-CPU output instruction tofrom the ZSO-SI0 arc illustrated in Figure 143. write a Data or Control byte into the Zt%SIO.

F IG. 14a - READ CYCLE

DATA OUTInfermpf Acknowledge Cycle. After receiving anI n t e r r u p t R e q u e s t Signal (3 pulled L o w ) , t h eZIO-CPU sends an Interrupt Acknowledge Signal(K and %?i@ both Low). The daisy-chained inter-rupr circuirs determine the highest priority inter-rupr requestor. T h e IE1 o f t h e highest p r i o r i t yperipheral is terminated High. For any peripheralthat has no interrupt pending or, undef Service.IEO= IEI. Any peripheral that does have an interruptpending or under Service forces its IE0 Lew.

T o insure stable conditions i n t h e d a i s y chain.a l l in te r rup t Status Signals are prev:ented f r o mchangmg while \fI is Lou. U’hen KQ is Low, thehiphesI priority interrupt requestor (Ihe one withIE1 High) places its interrupt vector on the data bus

and Sets its infernal interrupt-under-Service latch.

FIG. t4c - INTERRUPT ACKNOWLEDGE CYCLE

FIG. 14b - WRITE CYCLE

OATA x IN X

R e t u r n From I n t e r r u p t Cyele. Normally, t h eZBO-CPU i s s u e s a RET1 (RETUrn f r o m interrupf) in-struction at the end of an inrerrupI Service routine.RETI i s a 2-byIe opcode (ED-4DI thaI resets t h einterrupt-under-Service latch t o terminate t h e in-terrupt that has just been processed. This is ac-compl i shed by manipulating the daisy chain in Ihefolloring way.

The normal daisy chain Operation tan be used IOdetect a pending interrupt; hau-ever. iI cannot distin-guish between an interrupt under Service and a pendingunacknowledged interrupt of a higher priority. When-ever “ED” is decoded. Ihe daisy chain is modified byforcing High the IEO of any imerrupt that has not yeIbeen acknowledged. Thus the daisy chain identifies thedevice presently under Serviceas the only one wirb an IE1

FiG. 14d - t3ETUR.N FRDM INTERRUPT CYCLE

60

2-80 SI0 Timing

I High and an IE0 Low. lf the next opcode byte is ?D,’ Esch box in the illustration could be a separate exter-. the interrupt-under-Service latch is reset. nal 280 peripheral circuit with a user-defined order ol'

interrupt priorities. However. a similar daisy chain

The ripple timt of thc irterrupt daisy chain (both rheHigh-to-Low and the Low-to-High transitions) limitsthe number of devices tht tan be placed in the daisychain. Ripple time tan be improved with carry-look-ahead, or by extending the interrupt acknowledge cycle.

Daisy C.hain Interrupl Nesting

Figure 15 illustrates the daisy chain configuration ofinterrupt circuits and their behavior with nested inter-rupts (an interrupt that is interrupted by another with ahigher priority).

structure also exists inside the ZRO-SIO. Hhich- has sixinterrupt levels with a fixed Order of prioriries.

The case illustrated occurs when the transmitter ofChannel B interruprs and is granted Service. While thisinterrupt is being serviced, it is interrupted by a higherpriority interrupt frorn Channel A. The second interruptis serviccd and-upon completion-a RETI instruction isexecuted or a R E T I command is wittert into theZBO-HO, resetting the interrupt-under-Service latch of.the Channel A interrupt. At this rime, the Service rotinefor Channel B is resumed. W’hen it is completed,another RETI instruction is executed IO complete the in-terrupt Service.

FIG. 15 - TYPICAL INTERRUPT SEQUENCE

1. PRIORITV1IIERRUPT DAISY CHAIN~BEFORE ANY ItiTERRUPT OCCURS.

2. CtiANNEL ß TRANSMITTER INTERRUPTS AND IS ACKNOWLEDCED

3. EXTEANALBTATUS OF CHANNEL A I N T E R R U P T S SUSPENDING SERVICE OF CHANNEL BTRANSMI7lER.

, CHANNEL A EXTERNAL STATUS ROUTINE COMPLETE RET1 ISSUED CHANNEL BTRANSMITIER SERVICE RESUYED

5 CHANNEL8TRANSMITTER SERVICE ROUTINE COMPLETE. SECOND RET1 ISSUED.

61

Z8040'Z80A-SI0

n

Electrical Characteristics

F I G . 1 6 - T Y P I C A L I N T E R R U P T S E Q U E N C E

AC CharaclerislicsT,=O”C, Vcc= +JV. i5%

Electrical Characteristics

Electrical Characteristics

AC Charactcristics

JJC CharactcrMicsTA=O”C Io 70°C. Vcc= +SV, rtS%

CapocitanceTA=25”C. f= I MHz

Package Information

MECHANICAL DATA (dimensions in mm)

40-PIN CERAMIC DUAL IN-LINE SLAM PACKAGE 40-PIN PLASTIC DUAL IN-LINE PACKAGE

ORDERING NUMBERS:Z80-SI0 DDl for dual in-he ceramic slam packageZ8O-SIO Bl for dual in-line plastic packageZ8OA-SIO D1l for dual in-line ceramic slam packageZ8OA-SI0 BI for dual in-line plastic package

l65