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LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17, 2018 European Developers Meeting Bristol, United Kingdom

Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Page 1: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

LLVM Greedy Register Allocator – Improving Region Split DecisionsMarina Yatsina

Intel Corporation, Israel

April 16-17, 2018 European Developers Meeting

Bristol, United Kingdom

Page 2: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

2

Motivation

Page 3: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

3

Motivation

Page 4: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

4

Motivation

* idiv implicitly clobbers %edx

Page 5: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

5

Motivation

%ecx %ebx %edi %edx

%ebp %ecx %ebx %edi

%ebp %ecx %ebx %edi

%ecx %ebx %edi %edx

* idiv implicitly clobbers %edx

Page 6: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

6

Motivation

%ecx %ebx %edi %edx

%ebp %ecx %ebx %edi

%ebp %ecx %ebx %edi

%ecx %ebx %edi %edx

* idiv implicitly clobbers %edx

Page 7: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

7

Motivation

%ecx %ebx %edi %edx

%ebp %ecx %ebx %edi

%ebp %ecx %ebx %edi

%ecx %ebx %edi %edx

* idiv implicitly clobbers %edx

Page 8: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

8

Motivation

%edx

%ebp

%ebp

%edx

* idiv implicitly clobbers %edx

Page 9: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

9

Motivation

%edx

%ebp

%ebp

%edx

* idiv implicitly clobbers %edx

Page 10: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

10

Greedy Register Allocator

• Greedy Register Allocator Overview

• Region Split

• Encountered Issues

• Performance Impact

Page 11: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

11

Greedy Register Allocator

• Greedy Register Allocator Overview

• Region Split

• Encountered Issues

• Performance Impact

Page 12: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

12

High Level Design of Code Generator

Instruction Selection

Scheduling and Formation

Late Machine Code

Optimizations

Prolog/Epilog Code Insertion

Register Allocation

SSA-based Machine Code Optimizations

Code Emission

Instruction Selection

Scheduling and Formation

SSA-based Machine Code Optimizations

Page 13: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

13

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

Page 14: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

14

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

Page 15: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

15

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Stand alone passPriority Queue Construction

Page 16: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

16

Live Interval Analysis

BB#0:x = ……

BB#1:… = …x……

BB#2:…… = …x……

Page 17: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

17

Live Interval Analysis• Earlier pass named SlotIndexes added numbering to the instructions

000 BB#0:001 x = …002 …

003 BB#1:004 … = …x…005 …

006 BB#2:007 …008 … = …x…009 …

Page 18: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

18

Live Interval Analysis• Analyze x’s live interval

000 BB#0:001 x = …002 …

003 BB#1:004 … = …x…005 …

006 BB#2:007 …008 … = …x…009 …

x

Page 19: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

19

Live Interval Analysis• Look for uses and defs

000 BB#0:001 x = …002 …

003 BB#1:004 … = …x…005 …

006 BB#2:007 …008 … = …x…009 …

x

Page 20: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

20

Live Interval Analysis• Connect them into intervals

000 BB#0:001 x = …002 …

003 BB#1:004 … = …x…005 …

006 BB#2:007 …008 … = …x…009 …

x

Page 21: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

21

Live Interval Analysis• Represented x’s liveness as a collection of segments

x [001, 004), [006, 008)000 BB#0:

001 x = …002 …

003 BB#1:004 … = …x…005 …

006 BB#2:007 …008 … = …x…009 …

Page 22: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

22

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

Page 23: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

23

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

RegAllocGreedy Pass

Page 24: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

24

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

Page 25: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

25

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

For every interval

Page 26: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

26

Spill Weight Calculation• Intervals calculated by Live Interval Analysis

w x y z

Page 27: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

27

Spill Weight Calculation• Estimate spill weight of each interval based on interval characteristics• w has uses in a hot loop

• Higher spill weight

• x is cheaply rematerializable• Lower spill weight

30 KG5 KG 10 KG

w x y z

20 KG

Page 28: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

28

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

Page 29: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

29

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Spill

Priority Queue Construction

For every interval

Page 30: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

30

Priority Queue Construction

w x y z

Page 31: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Priority Queue Construction

w x y z

Page 32: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

32

Priority Queue Construction

w x y z

Page 33: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

33

Priority Queue Construction• Calculate interval allocation priority and insert into the queue

Priority Queue

w x y z

Page 34: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

34

Priority Queue Construction• Calculate interval allocation priority and insert into the queue• w is local in one basic block

• Lower allocation priority

Priority Queuew

x y z

Page 35: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

35

Priority Queue Construction• Calculate interval allocation priority and insert into the queue• x is global and spans across a lot of instructions

• Higher allocation priority

Priority Queuew x

y z

Page 36: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

36

Priority Queue Construction• Calculate interval allocation priority and insert into the queue

Priority Queuew xy

z

Page 37: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

37

Priority Queue Construction• Calculate interval allocation priority and insert into the queue

Priority Queuew xy z

Page 38: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

38

Priority Queue Construction• The Priority Queue will always dequeue the interval with the highest priority

Priority Queuew xy z

Page 39: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

39

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

Page 40: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

40

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

For every interval in queue

Page 41: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

41

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

Page 42: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

42

Register Assignment• R0, R1 are the physical registers in the system

R0 R1

Page 43: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

43

Register Assignment

Priority Queue

w xy z

R0 R1

Page 44: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

44

Register Assignment• Dequeue interval with highest priority

Priority Queue

y zw x

R0 R1

Page 45: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

45

Register Assignment

R0 R1

Priority Queue

y zw

x

Page 46: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

46

Register Assignment• Assign to available register if possible

R0 R1

Priority Queue

y zw

x

x

x

Page 47: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

47

Register Assignment• Dequeue interval with highest priority

R0 R1

Priority Queue

wy

x

x

x

z

Page 48: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

48

Register Assignment

R0 R1

Priority Queue

wy

x

x

x

z

Page 49: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

49

Register Assignment• Assign to available register if possible

R0 R1

Priority Queue

wy

x

x

xz

z

Page 50: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

50

Register Assignment• Dequeue interval with highest priority

R0 R1

Priority Queue

y

x

x

xz

z

w

Page 51: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

51

Register Assignment

R0 R1

Priority Queue

y

x

x

xz

z

w

Page 52: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

52

Register Assignment• Interference with x in R0

R0 R1

Priority Queue

y x

xz

z

w

x

Page 53: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

53

Register Assignment• Interference with z in R1

R0 R1

Priority Queue

y

xz

z

w

x

x

Page 54: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

54

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

Page 55: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

55

Eviction

R0 R1

Priority Queue

y

x

x

xz

z

w

Page 56: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

56

Eviction• Compare spill weights of interfering intervals

R0 R1

Priority Queue

y

x

x

xz

z

w

20 KG30 KG5 KG

Page 57: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Eviction• x cheaper than w

R0 R1

Priority Queue

y

x

x

xz

z

w

20 KG30 KG5 KG

Page 58: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

58

Eviction• Evict x

R0 R1

Priority Queue

y

z

z

w x

Page 59: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

59

Eviction• Assign w

R0 R1

Priority Queue

y

z

z

x

w

Page 60: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

60

Eviction

R0 R1

Priority Queue

y

z

zw

x

Page 61: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Eviction• Enqueue x back to the queue• Usually receives the same allocation priority R0 R1

Priority Queue

y

z

zw

x

Page 62: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

62

Register Assignment

R0 R1

z

zw

Priority Queue

xy

Page 63: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

63

Register Assignment

• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

y x

Page 64: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

64

Register Assignment

R0 R1

z

zw

Priority Queue

y

x

Page 65: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

65

Register Assignment

• Interference with w in R0

R0 R1

z

zPriority Queue

y

x

w

Page 66: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

66

Register Assignment

• Interference with z in R1

R0 R1x

z

zw

Priority Queue

y

Page 67: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

67

Eviction• Compare spill weights of interfering intervals• Can we Evict? R0 R1

z

zw

Priority Queue

y

x

20 KG30 KG5 KG

Page 68: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Eviction• Compare spill weights of interfering intervals• Can we Evict? No!

• x is the cheapest oneR0 R1

z

zw

Priority Queue

y

x

20 KG30 KG5 KG

Page 69: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment

R0 R1

z

zw

Priority Queue

y

x

Page 70: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

70

Register Assignment• Mark x to be split

R0 R1

z

zw

Priority Queue

y

x*

Page 71: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

71

Register Assignment

R0 R1

z

zw

Priority Queue

y x*

Page 72: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment• Enqueue x* back to the queue• Intervals marked to be split receive lower allocation priority R0 R1

z

zw

Priority Queue

y x*

Page 73: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment

R0 R1

z

zw

Priority Queue

yx*

Page 74: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x* y

Page 75: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment

R0 R1

z

zw

Priority Queue

x*

y

Page 76: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment• Assign to available register if possible

R0 R1

z

zw

Priority Queue

x*y

Page 77: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x*y

Page 78: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Register Assignment• x is marked to be split

R0 R1

z

zw

Priority Queue

x*

y

Page 79: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

79

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

Page 80: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

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Split• Is split beneficial?

R0 R1

z

zw

Priority Queue

x*

y

Page 81: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

81

Split• Is split beneficial? • (Assume) Yes! R0 R1

z

zw

Priority Queue

x*

y

Page 82: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

82

Split• Is split beneficial? • (Assume) Yes!

• Find the best way to splitR0 R1

z

zw

Priority Queue

x*

y

Page 83: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

83

Split• Do the split

• Add COPY instruction between the intervals

R0 R1

z

zw

Priority Queue

x* x1 x2

y

x2 =COPY x1

x1 =COPY x2

Page 84: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

84

Split

R0 R1

z

zw

Priority Queue

x1 x2

y

Page 85: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

85

Split• Calculate spill weights• Split artifacts may receive higher weight

than the original intervalR0 R1

z

zw

Priority Queue

x1 x2

15 KG2 KG

y

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Split

R0 R1

z

zw

Priority Queue

x1 x2y

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Split• Enqueue x1, x2 into the queue• This will also calculate their allocation priority R0 R1

z

zw

Priority Queue

x1 x2y

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Register Assignment

R0 R1

z

zw

Priority Queue

yx1x2

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

yx2 x1

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Register Assignment

R0 R1

z

zw

Priority Queue

yx2

x1

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Register Assignment• Assign to available register if possible

R0 R1

z

zw

Priority Queue

yx2

x1

x1

x1

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

y

x1

x1x2

x1

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Register Assignment

R0 R1

z

zw

Priority Queue

y

x1

x1

x2

x1

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Register Assignment• Interference with y in R0

R0 R1

z

zw

x1

x1

x2

Priority Queue

y

x1

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Register Assignment• Interference with z in R1

R0 R1

z

x1

x1

x2

w

y

Priority Queue

x1

z

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Register Assignment

R0 R1

z

zw

Priority Queue

y

x1

x1

x2

x1

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Eviction• Compare spill weights of interfering intervals

R0 R1

z

zw

Priority Queue

y

x1

x1

x2

15 KG 10 KG

x1

20 KG

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Eviction• y cheaper than x2

R0 R1

z

zw

Priority Queue

y

x1

x1

x2

15 KG 10 KG

x1

20 KG

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Eviction• Evict y

R0 R1

z

zw

Priority Queue

x1

x1

x2 y

x1

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Eviction• A split artifact can evict original interval

• Part of the split-eviction gradual refinement

R0 R1

z

zw

Priority Queue

x1

x1

x2 y

x1

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Eviction• Assign x2

R0 R1

z

zw

Priority Queue

x1

x1x2

y

x1x2

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Eviction

R0 R1

z

zw

Priority Queue

x1

x1x2y

x1x2

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Eviction• Enqueue y back to the queue

R0 R1

z

zw

Priority Queue

x1

x1x2y

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y

x1x2

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x1

x1x2y

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2

y

x1x2

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Register Assignment• Interference with x2 in R0

R0 R1

z

zw

x1

x1

y

Priority Queue

x2

x1x2

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Register Assignment• Interference with z in R1

R0 R1

z

x1

x1

y

Priority Queue

w

x2

x1

zx2

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Eviction• Compare spill weights of interfering intervals• Can we Evict? R0 R1

z

zw

Priority Queue

x1

x1x2

y

15 KG10 KG

x1

20 KG

x2

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Eviction• Compare spill weights of interfering intervals• Can we Evict? No!

• y is the cheapest oneR0 R1

z

zw

Priority Queue

x1

x1x2

y

15 KG10 KG

x1

20 KG

x2

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Eviction

R0 R1

z

zw

Priority Queue

x1

x1x2

y

x1x2

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Register Assignment• Mark y to be split

R0 R1

z

zw

Priority Queue

x1

x1x2

y*

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y*

x1x2

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Register Assignment• Enqueue y* back to the queue

R0 R1

z

zw

Priority Queue

x1

x1x2y*

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y*

x1x2

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x1

x1x2y*

x1x2

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Register Assignment• Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2

y*

x1x2

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Split• Is split beneficial?

R0 R1

z

zw

Priority Queue

x1

x1x2

y*

x1x2

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Split• Is split beneficial? • (Assume) No! R0 R1

z

zw

Priority Queue

x1

x1x2

y*

x1x2

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Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

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Spill

R0 R1

z

zw

Priority Queue

x1

x1x2

y*

x1x2

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Spill• Spill around uses• Spill after def

• Reload before useR0 R1

z

zw

Priority Queue

x1

x1x2

y*

spillreload

x1x2

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Spill• Create new intervals for spills and reloads

R0 R1

z

zw

Priority Queue

x1

x1x2

y* y1 y2

spillreload

spillreload

x1x2

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Spill

R0 R1

z

zw

Priority Queue

x1

x1x2

y1 y2

x1x2

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Spill• Calculate spill weights

R0 R1

z

zw

Priority Queue

x1

x1x2

y1 y2

3 KG 2 KG

x1x2

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Spill• Spill

R0 R1

z

zw

Priority Queue

x1

x1x2

y1 y2

y2y1

x1x2

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Spill• Enqueue y1, y2 into the queue• This will also calculate their allocation

priorityR0 R1

z

zw

Priority Queue

x1

x1x2

y1 y2

y2y1

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y2y1

x1x2

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x1

x1x2y1 y2

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y1

y2

x1x2

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Register Assignment• Assign to available register if possible

R0 R1

z

zw

Priority Queue

x1

x1x2y1y2

x1x2

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Register Assignment• Dequeue interval with highest priority

R0 R1

z

zw

Priority Queue

x1

x1x2y2

y1

x1x2

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Register Assignment

R0 R1

z

zw

Priority Queue

x1

x1x2y2

y1

x1x2

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Register Assignment• Assign to available register if possible

R0 R1

z

zw

Priority Queue

x1

x1x2y2

y1

x1x2

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Greedy Register Allocator

• Greedy Register Allocator Overview

• Region Split

• Encountered Issues

• Performance Impact

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Motivation

%ecx %ebx %edi %edx

%ebp %ecx %ebx %edi

%ebp %ecx %ebx %edi

%ecx %ebx %edi %edx

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Exploration• Why did the register allocator create these redundant mov instructions?

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Exploration• Why did the register allocator create these redundant mov instructions?• Artifacts of split x* x1 x2

x2 =COPY x1

x1 =COPY x2

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Exploration• Why did the register allocator create these redundant mov instructions?• Artifacts of split

• If we would have chosen to do the split differently we could have avoided the redundant mov instructions

• Why was this way to split was chosen?

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140

Greedy Register Allocator Overview• General flow

Live Interval Analysis

Spill Weight Calculation

SplitEvictionRegister Assignment

Priority Queue Construction

Spill

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Region Split• How to find the best way to split?

• How to know if split is beneficial?

R0 R1

z

zw

Priority Queue

x*

y

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Find Best Split

R0 R1x R2 … Rn

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Find Best Split• The registers already have assigned intervals

R0 R1x R2 … Rn

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Find Best Split• The registers already have assigned intervals

R0 R1

z

zy

x

w

R2 … Rn

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Find Best Split• The registers already have assigned intervals• These intervals impose allocation constraints

R0 R1x R2 … Rn

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Find Best Split• Do the split of x for each one of the registers

R0 R1x R2 … Rn

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Find Best Split• Do the split of x for each one of the registers

R0 R1x R2 … Rn

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Find Best Split• Do the split of x for each one of the registers

R0 R1x R2 … Rn

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Find Best Split• Do the split of x for each one of the registers

R0 R1x R2 … Rn

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Find Best Split• Do the split of x for each one of the registers• Estimate split cost, e.g. the amount of spill code this split may cause

R0 R1x R2 … Rn

20$15$10$20$

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Find Best Split• Do the split of x for each one of the registers• Choose the cheapest one

R0 R1x R2 … Rn

20$15$10$20$

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Find Best Split• Do the split of x for each one of the registers

R0 R1x R2 … Rn

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Find Best Split for Given Register• How do we do the best split for a given register R1?

153

x R1

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• The region split is usually divided into 2 intervals

154

Find Best Split for Given Register

x x1

x2 =COPY x1

x2

x1 =COPY x2

R1

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• The region split is usually divided into 2 intervals• ByReg

• Parts of x that pass on R1 register• Should comply with current allocation

constraints provided by intervals alreadyassigned to R1

• ByStack• Parts of x that pass on or on the stack• Usually where the already allocated

R1 intervals interfere with x

Find Best Split for Given Register

155

x x1ByReg

x2 =COPY x1

x2ByStack

x1 =COPY x2

R1

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• A good split

Find Best Split for Given Register

156

x x1ByReg

x2 =COPY x1

x2ByStack

x1 =COPY x2

R1

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• A good split• Reduces the transitions between ByReg and ByStack

• Each such transitions is potentially a spill/reload• In case ByStack is not allocated to

another register

• Places the transitions in blocks less frequently executed

Find Best Split for Given Register

157

x x1ByReg

x2 =COPY x1

x2ByStack

x1 =COPY x2

R1

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• A good split• Reduces the transitions between ByReg and ByStack

• Each such transitions is potentially a spill/reload• In case ByStack is not allocated to

another register

• Places the transitions in blocks less frequently executed

• Use Hopfield neural network• Converges to a result that satisfies

the above characteristics

Find Best Split for Given Register

158

x x1ByReg

x2 =COPY x1

x2ByStack

x1 =COPY x2

R1

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• Split reduces the amount of spills compared to spilling around uses

Determine if Split is Beneficial

159

BB#1:… = …x……

BB#2:…

BB#3:…

BB#0:x = ……

BB#4:…

BB#5:… = …x……

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• Split reduces the amount of spills compared to spilling around uses• Use/def blocks must have x in a register

at some point

Determine if Split is Beneficial

160

BB#1:… = …x……

BB#2:…

BB#3:…

BB#0:x = ……

BB#4:…

BB#5:… = …x……

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• Split reduces the amount of spills compared to spilling around uses• Use/def blocks must have x in a register

at some point

• If the split can create “regions” of several basic blocks where x is passed by registerthis will reduce the amount of spills• Only if constraints allow it

Determine if Split is Beneficial

161

BB#1:… = …x……

BB#2:…

BB#3:…

BB#0:x = ……

BB#4:…

BB#5:… = …x……

ByReg

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• Split reduces the amount of spills compared to spilling around uses• Use/def blocks must have x in a register

at some point

• If the split can create “regions” of several basic blocks where x is passed by registerthis will reduce the amount of spills• Only if constraints allow it

Determine if Split is Beneficial

162

BB#1:… = …x……

BB#2:…

BB#3:…

BB#0:x = ……

BB#4:…

BB#5:… = …x……

Passed by register region

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163

Greedy Register Allocator

• Greedy Register Allocator Overview

• Region Split

• Encountered Issues

• Performance Impact

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• Inaccurate split cost calculation• Root cause of the following encountered issues

• Does not model the affect of local interference caused by the split• Makes the split cost inaccurate

• The “cheapest” split may actually be more expensive than other splits

• Can choose suboptimal split

Region Split Cost Issues

164

20$15$10$20$

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• Find best split of interval x for R1• Using Hopfield neural network

Local Interference

165

BB#1:… ……… … ……

R1

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• Find best split of interval x for R1• Using Hopfield neural network

• The network determines how x will be passed on the CFG edges

Local Interference

166

BB#1:… ……… … ……

R1

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• Find best split of interval x for R1• Using Hopfield neural network

• The network determines how x will be passed on the CFG edges• “ByReg” interval or “By stack” interval

Local Interference

167

BB#1:…………… ……

R1

x1 ByReg

x2 ByStack

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• Find best split of interval x for R1• Using Hopfield neural network

• The network determines how x will be passed on the CFG edges• “ByReg” interval or “By stack” interval• Determined which basic block will have a copy

between these two intervals

Local Interference

168

BB#1:………x2 = x1… ……

R1

x1 ByReg

x2 ByStack

Page 169: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• Find best split of interval x for R1• Using Hopfield neural network

• The network determines how x will be passed on the CFG edges• “ByReg” interval or “By stack” interval• Determined which basic block will have a copy

between these two intervals

• The Hopfield neural network does not model what happens to x inside the basic block

Local Interference

169

BB#1:…………… ……

R1

x1 ByReg

x2 ByStack

Page 170: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• The Hopfield neural network does not model what happens to x inside the basic block

Local Interference

170

BB#1:…………… ……

R1

Page 171: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• The Hopfield neural network does not model what happens to x inside the basic block• x split for R1 determined x’s ByReg

interval should enter and leave BB#1

Local Interference

171

BB#1:…………… ……

R1

x1 ByReg

x1 ByReg

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• The Hopfield neural network does not model what happens to x inside the basic block• x split for R1 determined x’s ByReg

interval should enter and leave BB#1

• y in BB#1 is already assigned to R1

Local Interference

172

BB#1:…y = ……… = …y…… ……

R1

y

x1 ByReg

x1 ByReg

Page 173: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• The Hopfield neural network does not model what happens to x inside the basic block• x split for R1 determined x’s ByReg

interval should enter and leave BB#1

• y in BB#1 is already assigned to R1

• x is used in BB#1

Local Interference

173

BB#1:… = …x…y = …… = …x…… = …y……… = …x……

R1

y

x1 ByReg

x1 ByReg

Page 174: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• The Hopfield neural network does not model what happens to x inside the basic block• x split for R1 determined x’s ByReg

interval should enter and leave BB#1

• y in BB#1 is already assigned to R1

• x is used in BB#1

• y interferes with assigning x to R1 locally in BB#1

Local Interference

174

BB#1:… = …x…y = …… = …x…… = …y……… = …x……

R1

y

x1 ByReg

x1 ByReg

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• The Hopfield neural network does not model what happens to x inside the basic block• x split for R1 determined x’s ByReg

interval should enter and leave BB#1

• y in BB#1 is already assigned to R1

• x is used in BB#1

• y interferes with assigning x to R1 locally in BB#1• The part of x that contains this local interference

will be added to x’s “ByStack” split artifact

Local Interference

175

BB#1:… = …x…y = …… = …x…… = …y……… = …x……

R1

y

x1 ByReg

x2 ByStack

x1 ByReg

Page 176: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

• Local interferences may have very negative affectson assignment of the “ByStack” split artifact• Can cause bad eviction chains

• Encountered issues #1, #2

• Can cause a lot of reloads• Encountered issue #3

• This affect is not considered during split cost calculation

Local Interference

176

BB#1:… = …x…… = …y…… = …x…… = …y……… = …x……

R1

y

x1 ByReg

x2 ByStack

x1 ByReg

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177

Encountered Issue• Bad eviction chain• Cyclic eviction/split chain – Issue #1

• Domino effect eviction – Issue #2

• Multiple reloads from the same location• Issue #3

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178

Encountered Issue #1• Bad eviction chain – scenario 1• llvm/test/CodeGen/X86/

greedy_regalloc_bad_eviction_sequence.ll

Page 179: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

179

Encountered Issue #1• Bad eviction chain – scenario 1• llvm/test/CodeGen/X86/

greedy_regalloc_bad_eviction_sequence.ll%ecx %ebx %edi %edx

%ebp %ecx %ebx %edi

%ebp %ecx %ebx %edi

%ecx %ebx %edi %edx

Page 180: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

180

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

Page 181: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

181

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

Page 182: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

182

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi

ediy

x

Page 183: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

183

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi

ediy

x

2 KG 1 KG

Page 184: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

184

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi

edixyEvicts

y x

Page 185: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

185

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi

edix

y

Evicts

y x

Page 186: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

186

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

edix

y

Evicts

y x

Page 187: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

187

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

edix

yy x

Evicts

Page 188: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

188

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

edix2

y

x1

y x

x

part ofSplit

Evicts

Page 189: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

189

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

• x1 represent the part of the split that has local interference with y

edix1

y x

xInterfering part

of

ySplit

Evicts

Page 190: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

190

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

• x1 represent the part of the split that has local interference with y

edi

y

x1

y x

xInterfering part

ofSplit

Evicts

Page 191: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

191

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

• x1 represent the part of the split that has local interference with y

• x1 evicts y from edi edi

y

x1

3 KG 2 KG

y x

xInterfering part

ofSplit

Evicts

Page 192: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

192

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

• x1 represent the part of the split that has local interference with y

• x1 evicts y from edi ediyx1

y x

xInterfering part

ofEvicts Split

Evicts

Page 193: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

193

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• y evicts x from edi• x is split into x1 and x2

• x1 represent the part of the split that has local interference with y

• x1 evicts y from edi ediy

x1Evicts Split

Evicts

y x

xInterfering part

of

Page 194: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

194

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• Every such “movl” duo was created by cyclic eviction/split chain

Evicts Split

Evicts

y x

xInterfering part

of

Page 195: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

wInterfering part

of

195

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• Every such “movl” duo was created by cyclic eviction/split chain

Evicts Split

Evicts

z w

Page 196: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

bInterfering part

of

196

Encountered Issue #1• Bad eviction chain – scenario 1• Cyclic eviction/split chain

• Every such “movl” duo was created by cyclic eviction/split chain

Evicts Split

Evicts

a b

Page 197: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

197

Encountered Issue #1• Bad eviction chain – scenario 1• The problem

• x is split in such a way that creates local interference split artifact

• That artifact causes cyclic eviction

• The solution• Tailored for this case

• Identify if a split will create a local interference artifact• Identify if that split artifact will cause a cyclic eviction• Increase split cost

• Make this split less attractive compared to other splits

• Commit: https://reviews.llvm.org/rL31629520$

Evicts Split

Evicts

y x

xInterfering part

of

Page 198: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

198

Encountered Issue #2• Bad eviction chain – scenario 2• https://bugs.llvm.org/show_bug.cgi?id=26810

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199

Encountered Issue #2• Bad eviction chain – scenario 2• https://bugs.llvm.org/show_bug.cgi?id=26810

• This time parts of the chain are spread around

%xmm5 %xmm4 %xmm3 %xmm2

%xmm7 %xmm5 %xmm4 %xmm3

%xmm7 %xmm5 %xmm4 %xmm3

%xmm5 %xmm4 %xmm3 %xmm2

Page 200: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

200

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

Page 201: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

201

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2

xmm2x

y

Page 202: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

202

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2

x

y

4 KG 1 KG

xmm2

Page 203: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

203

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2

xmm2x yEvicts y

x

Page 204: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

204

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2

xmm2y

x

Evicts yx

Page 205: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

205

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

xmm2y

x

Evicts yx

Page 206: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

206

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

xmm2y

x

Evicts yx

Page 207: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

207

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

xmm2

x

y2y1Evicts y

Split part of y

x

Page 208: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

208

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

xmm2y1

x

Evicts ySplit Interfering part

of y

x

Page 209: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

209

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

xmm2

x

y1Evicts y

Split Interfering part of y

x

Page 210: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

210

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2 xmm2

x

y1

4 KG3 KG

Evicts ySplit Interfering part

of y

x

Page 211: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

211

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2 xmm2

x

y1Evicts y

Split Interfering part of y

x

Page 212: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

212

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2 y1Evicts y

Split Interfering part of y

x

Page 213: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

213

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2• y1 evicts z from xmm3

xmm3y1

z

Evicts ySplit Interfering part

of y

x

Page 214: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

214

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2• y1 evicts z from xmm3

xmm3

z

y1

1 KG3 KG

Evicts ySplit Interfering part

of y

x

Page 215: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

215

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2• y1 evicts z from xmm3

xmm3y1 zEvicts y

Split

Evicts zy

Interfering part of

x

Page 216: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

216

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• x evicts y from xmm2• y is split into y1 and y2 for xmm2

• y1 represent the part of the split that has local interference with x

• y1 cannot evict x from xmm2• y1 evicts z from xmm3

xmm3

y1

zEvicts y

Split

Evicts zy

Interfering part of

x

Page 217: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

217

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3

xmm3

y1

zEvicts y

Split

Evicts zy

Interfering part of

x

Page 218: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

218

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

xmm3z

y1

Evicts ySplit

Evicts zy

Interfering part of

x

Page 219: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

219

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

xmm3z

y1

Evicts ySplit

Evicts zy

Interfering part of

x

Page 220: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

220

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

xmm3z2z1

y1

zpart of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

Page 221: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

221

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

xmm3z1

y1

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

Page 222: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

222

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

xmm3z1

y1

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

Page 223: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

223

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3 xmm3z1

y1

2 KG 3 KGz

Interfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

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Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3 xmm3z1

y1

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

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225

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3 z1

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

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226

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3• z1 evicts w from xmm4

xmm4

w

z1

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

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227

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3• z1 evicts w from xmm4

xmm4z1

2 KG 1 KG

w

zInterfering part of

Evicts ySplit

Evicts zSplit

yInterfering part of

x

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228

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3• z1 evicts w from xmm4

xmm4z1 w

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

w

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229

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• y1 evicts z from xmm3• z is split into z1 and z2 for xmm3

• z1 represent the part of the split that has local interference with y1

• z1 cannot evict y1 from xmm3• z1 evicts w from xmm4

xmm4

z1

w

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

w

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230

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• Every such “movl” duo was created by the domino effect

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

w

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231

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• Every such “movl” duo was created by the domino effect

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

wSplit

Evicts a w

Interfering part of

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232

Encountered Issue #2• Bad eviction chain – scenario 2• Domino effect eviction

• Every such “movl” duo was created by the domino effect

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

wSplit

Evicts aSplit

Evicts b

wInterfering part of

aInterfering part of

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233

Encountered Issue #2• Bad eviction chain – scenario 2• The problem

• y is split to fit the register it was evicted from• This split creates local interference split

artifact that causes domino effect eviction

• The solution• Tailored for this case

• Identify if a split for evicted register creates local interference artifact• Identify if that split artifact will cause domino effect eviction• Increase split cost

• Make this split less attractive compared to other splits

• Commit: https://reviews.llvm.org/rL31629520$

zInterfering part of

Evicts ySplit

Evicts zSplit

Evicts

yInterfering part of

x

w

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234

Encountered Issue #3• Multiple reloads from the same location

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235

Encountered Issue #3• Multiple reloads from the same location• All the reloads are from the same

location

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236

Encountered Issue #3• Multiple reloads from the same location• All the reloads are from the same

location

• Appeared in a hot loop after a higher level change

Page 237: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

237

Encountered Issue #3• Multiple reloads from the same location

Before Change After ChangeLoop MBB is the same until Greedy

Loop MBB is the same until Greedy

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238

Encountered Issue #3• Multiple reloads from the same location

Before Change After ChangeLoop MBB is the same until Greedy

x is split for R0

Loop MBB is the same until Greedy

x is split for R1

Page 239: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

239

Encountered Issue #3• Multiple reloads from the same location

Before Change After ChangeLoop MBB is the same until Greedy

x is split for R0

Split doesn’t have local interferences

Loop MBB is the same until Greedy

x is split for R1

Split has local interference in Loop’s MBB

Page 240: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

240

Encountered Issue #3• Multiple reloads from the same location

Before Change After ChangeLoop MBB is the same until Greedy

x is split for R0

Split doesn’t have local interferences

Loop MBB is the same until Greedy

x is split for R1

Split has local interference in Loop’s MBB

Local interference spilled & reloaded around uses

Page 241: Yatsina-LLVM Greedy Register Allocator Greedy Registe… · LLVM Greedy Register Allocator – Improving Region Split Decisions Marina Yatsina Intel Corporation, Israel April 16-17,

241

Encountered Issue #3• Multiple reloads from the same location• The problem

• Local interference interval has a lot of uses

• This interval is spilled and reloaded

• Solution• Identify if the created local

interference interval will spill• Increase split cost

• Make this split less attractive compared to other splits

• Commit: https://reviews.llvm.org/rL32387020$

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242

Greedy Register Allocator

• Greedy Register Allocator Overview

• Region Split

• Encountered Issues

• Performance Impact

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• Fix affected mostly EEMBC workloads

• Regressions unrelated to this change

• No actual compile time impact on CTMark

Fix for Bad Eviction Chains - Issues #1, #2

Run

Tim

e C

hang

e (%

)

Affected workloads-2.67-2.64-2.52-2.30-2.18

2.462.783.373.403.433.473.473.503.503.65

12.0813.02

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• Fix affected mostly EEMBC workloads

• No actual compile time impact on CTMark

Fix for Multiple Reloads - Issue #3

Run

Tim

e C

hang

e (%

)

Affected workloads

2.13.033.2644.394.424.945.16

11.2711.2812.0612.1312.212.412.4412.8613.08

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Conclusions• Local interference caused by split may have a negative affect

• Current split cost does not take this affect into account

• Committed solutions tailored to catch 3 specific scenarios

• Need a more holistic approach for quantifying the cost of local interferences caused by split