XTP053: SP601 Standalone Applications - Xilinx · 6.01.a Product Specification for more details. Updated SI Labs USB UART Drivers URL Overview Xilinx SP601 Board Software Requirements

© Copyright 2012 Xilinx

SP601 Standalone Applications

March 2012

XTP053

http://www.xilinx.com/legal.htm�

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Revision History

Date Version Description 03/16/12 13.4 Up-rev 13.3 GPIO_HDR Design to 13.4.

10/26/11 13.3 Up-Rev 13.2 GPIO_HDR Design to 13.3.



12/21/10 12.4 Up-Rev 12.3 GPIO_HDR Design to 12.4. Added SDK flow.


07/23/10 12.2 Up-Rev 12.1 GPIO_HDR Design to 12.2. Set RZQ and ZIO pins in MPMC core GUI. See MPMC 6.01.a Product Specification for more details. Updated SI Labs USB UART Drivers URL

Overview

Xilinx SP601 Board Software Requirements SP601 Setup Multi-pin Wake-up GPIO Header References

Note: This presentation applies to the SP601

SP601 Standalone Apps

Description – The standalone applications tutorial extends the board feature tests offered

through the BIST. A derived EDK design with additional software is used to test features such as the GPIO header pins

Multi-pin Wake-up Design – Simple counter design show the Multi-pin Wake-up functionality of the

Spartan-6 FPGA Family

GPIO Header Loopback Test – EDK IP: MicroBlaze system derived from EDK BIST design

• Embedded System Tools Reference Guide (UG111) • http://www.xilinx.com/ise/embedded/edk_ip.htm

Note: Presentation applies to the SP601

http://www.xilinx.com/ise/embedded/edk_ip.htm�

Xilinx SP601 Board


ISE Software Requirement

Xilinx ISE 13.4 software


EDK Software Requirement

Xilinx EDK 13.4 software


EDK Software Requirement

Xilinx SDK 13.4 software


SP601 Setup

Connect a USB Mini-B Cable to the USB UART connector on the SP601 board for the UART Driver install

– Connect this cable to your PC

Power on the SP601 board for UART Driver Install

SP601 Setup

Install USB UART Drivers – CP210x_VCP_Win_XP_S2K3_Vista_7.exe


http://www.silabs.com/Support Documents/Software/CP210x_VCP_Win_XP_S2K3_Vista_7.exe�

SP601 Setup

Reboot your PC if necessary Right-click on My Computer

and select Properties – Select the Hardware tab – Click on Device Manager


SP601 Setup

Expand the Ports Hardware – Right-click on Silicon Labs

CP210x USB to UART Bridge and select Properties


SP601 Setup

Under Port Settings tab – Click Advanced – Set the COM Port to an open Com

Port setting from COM1 to COM4


SP601 Setup

Unzip the rdf0015.zip file – Available through http://www.xilinx.com/sp601 – Includes AR32713 – Recommended constraints for the XPS_LL_TEMAC

systems


http://www.xilinx.com/support/answers/32713.htm�

Multi-pin Wake-up

Multi-pin Wake-up

Connect a USB Mini-B Cable to the USB JTAG connector on the SP601 board

– Connect this cable to your PC

Multi-pin Wake-up

This test will involve removing the Suspend Jumper, seen below – In this design, when an internal FPGA condition occurs and the suspend

jumper is in place, suspend is initiated – The FPGA condition is when the two bit counter reaches “11”


Multi-pin Wake-up

Open an ISE Design Suite Command prompt Run xmd to download the Bitstream file

– The xmd.ini file will enter the required download commands cd C:\sp601_standalone_apps\multi_pin_wake_up xmd

Note: Suspend jumper can be on or off during programming

Multi-pin Wake-up

Install a jumper on J14 The Counter LEDs continues to “11” and then

stops counting (DS11 & 12) The Awake LED goes out


Multi-pin Wake-up

Remove the jumper on J14 The Awake LED comes on The Counter LEDs resume counting at “11”


GPIO Header Loopback Test

Embedded Processor Design

The provided embedded reference design is supported “as is” – Please refer to the click through license agreement

Embedded reference design has been verified on the SP601 Evaluation Kit – Design consists of Early Access IP – Design may change in subsequent releases

The reference design will allow users to: – Re-build and verify functionality on the SP601 evaluation kit

SP601 MicroBlaze Hardware

The SP601 MicroBlaze Design Hardware includes: – DDR2 Interface (128 MB) – BRAM – External Memory Controller (EMC)

• Flash Memory

– Networking – UART – Interrupt Controller – GPIO (HDR Pins, IIC, LEDs) – Timer – SPI – PLB v46 Bus



Connect two USB Type-A to Mini-B cables to the USB JTAG and UART connectors on the SP601 board

– Connect these cables to your PC


Connect jumpers across J13 as shown here



Do not connect any jumpers across pins 9, 10, 11, or 12 – These pins are connected to power and ground



Board Power must be on before starting Tera Term Start the Terminal Program

– Select your USB Com Port – Set the baud to 9600

Note: Tera Term may need to be restarted if board power is cycled


Open an ISE Design Suite Command prompt Run xmd to download the Bitstream and ELF file

– The xmd.ini file will enter the required download commands cd C:\sp601_standalone_apps\gpio_hdr\ready_for_download xmd



The test results will appear in the terminal window


Compile SP601 GPIO Header Loopback Design


If desired, FPGA compile can be skipped by opening SDK directly: Start → All Programs → Xilinx ISE Design Suite 13.4 → EDK → Xilinx Software Development Kit

Select the workspace: <design files>\SDK\SDK_Workspace_35 Go to SDK Software Compile


Open XPS project <project directory>\ system.xmp

Create the hardware design, system.bit, located in <project directory> /implementation – Click the Generate

Bitstream button (1) – Or from the menu,

select Hardware → Generate Bitstream


1


Open SDK – Click the Export

Design button (1) – Click Export & Launch

SDK (2)

2 Note: Presentation applies to the SP601

1


SDK Software Compile – Build ELF files in SDK – Select Project → Build All (1) – Note: If by-passing the FPGA compile, the ELF files are already built; if

desired, the ELF files can be re-built by selecting Clean… followed by Build All

1

Download SP601 GPIO Header Loopback Design


Init memory with the Bootloop ELF – Update the bitstream (download.bit) with the Bootloop ELF – Select Xilinx Tools → Program FPGA (1)

1


Init memory with the Bootloader Application ELF – Select bootloop (1) – Click Program

Note: Verify the Bitstream and BMM File paths match your design path

1


Launch XMD – Select Xilinx Tools → XMD Console (1)

1


Connect XMD to the MicroBlaze: cd C:/sp601_standalone_apps/gpio_hdr/SDK/SDK_Workspace_35 connect mb mdm


To execute a memory read, type mrd 0x00000000

This will read the memory address at the reset vector; the value should be 0xB8000000 as shown below


Download and run the System Monitor ELF file: dow hello_gpio_hdr/Debug/hello_gpio_hdr.elf


Download and run the System Monitor ELF file: con





Init memory with the GPIO Header ELF – Update the bitstream (download.bit) with the GPIO Header ELF – Select Xilinx Tools → Program FPGA (1)

1


Init memory with the GPIO Header ELF – Select <Design Files>\gpio_hdr\SDK\SDK_Workspace_35

\hello_gpio_hdr\Debug\hello_gpio_hdr.elf (1) – Click Program

1

Note: Always reselect the desired ELF file at this step




References

References

EDK Documentation – Embedded System Tools Reference Guide

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/est_rm.pdf

Spartan-6 Configuration – Spartan-6 FPGA Configuration User Guide

http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/est_rm.pdf�

http://www.xilinx.com/support/documentation/user_guides/ug380.pdf�

Documentation

Documentation

Spartan-6 – Spartan-6 FPGA Family

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm

SP601 Documentation – Spartan-6 FPGA SP601 Evaluation Kit

http://www.xilinx.com/products/boards-and-kits/EK-S6-SP601-G.htm – SP601 Getting Started Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug523.pdf – SP601 Hardware User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug518.pdf – SP601 Reference Design User Guide

http://www.xilinx.com/support/documentation/boards_and_kits/ug524.pdf

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm�

http://www.xilinx.com/products/boards-and-kits/EK-S6-SP601-G.htm�

http://www.xilinx.com/support/documentation/boards_and_kits/ug523.pdf�

