EECE2323 Digital Logic Design Lab Lab 0

XOR gate

1 Objective

The purpose of this lab experiment is to get you familiar with the tools and hardware demo boardthat you will be using for all EECE2323 labs this semester. This rst experiment is a tutorial. Bystepping through all the instructions you will learn techniques and tools you will use throughoutthe course.

2 Conventions

The following conventions are used throughout all lab manuals.

Text Style Use Example

boldface Actions you need to take Draw a wire from A to B.Names of programs or tools Open ISE Simulator and enter...

italics Names of handouts and tutorials Refer to the Using ECS handout.Menus and menu items Select File ! Quit to exit.Buttons Click Finish to continue.

monospace User interface objects Enter a name into the Net Name eld.Names of symbols Insert two nand2 gates.Text you enter into elds Call your schematic xorgate.Items you pick from a list Choose Schematic from the list.

You should read through the entire lab manual before coming to lab so that you are familiarwith the concepts and the procedure to be followed. Additional information that is important tounderstanding the experiment may not be printed in boldface, but you should read it anyway.

You should also have a copy of the following handouts: Software and Accounts, Creating a NewProject, Simulating Designs, Using ECS, Using iMPACT. You should read these handouts beforebeginning the this lab assignment.

3 Overview

In this lab you will implement an EXCLUSIVE-OR (XOR) gate out of NAND gates using the toolsavailable in the Xilinx ISE software package. This XOR gate is only an example; in future labsyou will use an XOR gate that is part of the ECS gate library because it is more convenient.

The logic symbol and truth table for an XOR gate are shown in Figure 1(a). A schematic showinghow to build an XOR out of NAND gates is shown in Figure 1(b). There are several possible waysto build an XOR from NANDs; this one uses the minimum number of gates.

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A B0011

0101

C0110

CB

AA

B

X

Y

Z

C

(b)(a)

Figure 1: XOR gate symbol and truth table (a), Implementation of XOR using NANDs (b)

This lab will teach you how to use the Xilinx ISE design tools. The steps taken in this labmanual, as well as the processes and procedures that are described, will be repeated throughoutthe semester. This assignment will introduce you to these practices.

First, you will enter the schematic shown in Figure 1 with ECS. Then, you will create a VerilogTest Fixture and simulate your design with ISE Simulator. Show the completed simulation tothe TAs for the rst part of your grade.

Once the simulation is complete, you will use the XST synthesis tools to translate your design toa bitstream that can be used to program the eld programmable gate array (FPGA) chip on thedemoboard. Finally you will use iMPACT to download the program to the FPGA and test it inhardware. Demonstrate the working hardware to the TAs for the second part of the lab grade.

For this tutorial lab, your grade will consist of the grade for the simulation and the grade for thehardware. There are no prelab assignments and no lab report for this lab. All other labs willhave one or more prelab assignments, one or more simulation/hardware grades, and one lab reportgrade.

4 XOR Gate

The rst and only part of this lab assignment is to create the XOR gate out of NAND gates. Futurelabs will often have two or more sections of work to be done.

4.1 Prelab

There is no prelab assignment for this part of the lab.

4.2 Entering Your Design

The Xilinx ISE toolkit is accessed through an interface called Project Navigator. All of thedesign and implementation tools can be accessed, run, and controlled through Project Navigator.You can also access the les and documents associated with your project. See the Software andAccounts handout for more information on the software.

Launch Project Navigator by selecting it from the Start menu:

Start ! All Programs ! COE Applications ! Xilinx ISE Design Suite 13.3 ! ISE Design Tools! Project Navigator

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4.2.1 Starting a New Project

Read and Perform the steps in the Creating a New Project tutorial. Create a new project for this lab called lab0. Project Navigator automatically createsthe directory C:/Users/NEU username EECE2323/lab0.

When you have created a new project your Project Navigator window should look like Figure 2.Lab manual directions will often refer to the various \panes" of the Project Navigator window,as labelled here.

Figure 2: Project Navigator Main Window

4.2.2 Creating a New Schematic

The rst step in this lab assignment is to enter the schematic design for the XOR gate into ECS(the Engineering Capture System). First we must create a new schematic le to add to our project,then we can edit the schematic.

Right-click in the Sources pane and select New Source from the popup menu. The\New Source Wizard" window appears (see Figure 3). Select Schematic from the listof le types on the left. In the File name eld, enter xorgate. Do not change the

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location. Make sure Add to project is checked, then click the Next button. ClickFinish to continue.

Figure 3: New Source Wizard window

A tab bar appears at the bottom of the MDI pane for all of your currently open les. You shouldsee an empty schematic in the MDI pane. If not, double-click on the entry for your schematic le(xorgate.sch) in the Sources pane.

4.2.3 Entering a Design with ECS

Read and Perform the steps in Using ECS tutorial. We will now enter the schematic shown in Figure 1(b). Detailed directions on each step are availablein the tutorial. You should keep this tutorial handy and refer to it often during the semester.

Add four 2-input NAND gates to your schematic. In the ECS symbol library these arecalled nand2. Add wires connecting the NAND gates together, as shown in Figure 4.

Figure 4: Completed XOR schematic

Now you will indicate the ports (inputs and outputs) of your design, and name thesignals (See Using ECS). Use the Wire tool to draw short wires on the input signals.

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Select the I/O Marker tool by clicking the button on the toolbar, pressing Ctrl-G, orselecting Add ! I/O Marker from the menu. Add input markers to the input wiresand an output marker to the output of the rightmost NAND gate. Then use the Nametool (See Using ECS) to name the wires connected to the inputs of your circuit A andB, and the output C. You do not need to name the intermediate wires X, Y , and Zbut you can if you wish. When you are done your schematic should look like Figure 4.

It is generally a good idea at this point to run the DRC (Design Rules Check) to ensure that yourcircuit is properly constructed. Click the DRC button (Figure 5) on the toolbar. If any errors orwarnings are displayed in the Transcript pane, ask the TA for assistance as the error messages areoften dicult to interpret.

Figure 5: Check Schematic button (circled)

Once you are nished, save your schematic by clicking the Save button on the toolbar,pressing Ctrl-S, or selecting File ! Save from the menu.

4.2.4 Creating A Symbol From Your Schematic

Refer to the Using ECS handout, Section \Creating a Symbol" for detailed directions on creatinga symbol for your XOR gate.

4.3 Simulating Your Design

Now that you have nished constructing the schematic you must test it. To test designs you usea software simulator which creates a computer simulation of the schematic. To do this, you mustspecify the test vectors, or set of input values, that will be used to test your circuit. In this sectionyou will use Verilog testbench to construct your test vectors, and then use ISim, short for ISESimulator to simulate the circuit's response to those test vectors.

In this lab we will tell you what test vectors you should use. Since this is a very simple circuit withonly two inputs, you will test all possible input combinations (22 = 4 possibilities). In some futurelabs it will be up to you to choose an appropriate set of vectors that demonstrates that your circuitworks correctly.

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Time (ns)Signal 200 300 400 550

A 1 0 1 0B 0 1 1 0

C 1 1 0 0

Table 1: XOR Gate Test Vectors

4.3.1 Creating a Verilog Test Fixture

Read and Perform the steps in Simulating Designs handout

Create a Verilog Test Fixture called xorgate tb. Remember to set Design View toSimulation. Use the test vectors in Table 1 to test your XOR gate.

Follow the code shown in Figure 6 to see how to specify how the input values willchange at 200ns, 300ns, 400ns, and 550ns. This is how you will create your own testvectors in future labs. Before running it in ISE Simulator, make sure that you set theSimulation Run Time property to an appropriate value before running your simulation,which should be no smaller than the your simulation time in your Verilog testbenchcode. For this part, 1000ns is enough. Refer to Simulating Designs for detailedinformation.

Figure 6: Verilog Test Fixture for XOR Gate

Once you are nished, save your testbench by clicking the Save button on the toolbar,

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pressing Ctrl-S, or selecting File ! Save from the menu.

4.3.2 Running a Testbench with ISE Simulator

Continue with the Simulating Designs handout. Compare the results that appear inyour ISE Simulator waveform with the results shown for the signal C in Table 1. Yourwaveform should resemble Figure 7.

Figure 7: ISE Simulator Waveform for XOR Gate

If the results are correct, get the TA to check o your simulation. This is the rstpart of your lab grade.

4.4 Testing in Hardware

The last step is to test your design in hardware. To do this, you need to create a new schematicthat indicates how the hardware on the FPGA prototype board should be connected to your design.The synthesis tools will then create a bitstream that can be used to program the FPGA. Finallywe will connect the FPGA board to the PC and download the program.

4.4.1 Creating a Hardware-Test Schematic

Create a new schematic called xorgate hw. (Refer to Section 4.2.2 for instructions.)Add the symbol for the XOR gate that you created in Section 4.2. In the Categorieslist of the Symbols pane, the second entry is the current project directory. Select thatcategory and the xorgate symbol appears in the Symbols list.

Now we will connect the XOR gate's inputs to switches on the FPGA board, and the output to anLED. Whenever we connect inputs or outputs to devices on the FPGA board we use a symbolfrom the library called IBUF (for input buers) or OBUF (for output buers). Specifying the LOC(pin location) attribute for these buers attaches them to pins on the FPGA chip; those pins areconnected to devices on the FPGA board.

Click the All Symbols category. Then add two IBUFs, one for each input to the xorgate.Add one OBUF for the output. Then add input markers (see Section 4.2.3) to the inputsof the IBUFs and an output marker to the output of the OBUF. The ports (input andoutput markers) will have default names like XLXN 3. You do not need to rename them.

Set the LOC attributes of the buers (IBUFs and OBUFs) to the values specied in Table 2.Right-click on a buer and choose Object Properties from the popup menu. The\Instance Attributes" window appears. Click New to create a new attribute. The

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Signal A B CDevice SW1 SW0 LED0

LOC p38 p36 p15

Table 2: LOC Attributes for I/O Buers

Figure 8: Schematic for XOR Gate with I/O Buers

\New Attribute" window appears. Select or type LOC into the Attribute Name eld,and the pin name from Table 2 in the Attribute Value eld. Click OK to close theNew Attribute window, and OK to close the Instance Attributes window.

When complete your schematic should resemble Figure 8. Save it before continuing.

4.4.2 Implementing a Design with XST

The process of transforming your design specication (i.e. schematic les) into a bitstream that canbe used to program the FPGA is called synthesis. Project Navigator includes the XST toolkitto perform synthesis on your design. Since synthesis is specic to a particular FPGA, it is criticalthat your project be designed for the right part. In this case we are using the xc3s100e-4tq144chip, which you should have set when you created a new project. If this part number does notappear in the Sources pane, ask a TA to help you x it before going on.

In the Sources pane, change the Design View to Implementation. Click on it once toselect it. Then in the Processes pane, Double-click on Generate Programming File to runthe synthesis process. Project Navigator will run the Synthesis and Implementationprocesses automatically. A swirling circle appears next to the process that is currently running;you can see diagnostic output scroll past in the Messages pane. If any errors occur they will bemarked with a red circle. Warnings are marked with a yellow triangle with an exclamation point.If you see errors or in your output, ask the TA for help. Most warnings can be ignored though.Processes that complete successfully will be marked with a green circle with a check mark inside.

4.4.3 Programming the FPGA with iMPACT

Read and Perform the steps in Using iMPACT tutorial. Refer to the handout for directions on programming your prototyping board with the bitstreamyou created. The bitstream le name is xorgate hw.bit.

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4.4.4 Testing your Design

Table 3 below shows which devices on the protoype board (switches, buttons) are connected to theinputs of your design. This table will appear in every lab manual to show you how to test yourdesign. Also recall Table 2 on page 8, which showed similar information.

For this design, switches 0 and 1 (the right-most switches in the bank) are connected to the inputs,and LED 0 (again, the right-most light) is connected to the output. Using the switches, run thesame test vectors that you simulated (see Table 1). Verify that the LED turns o when bothswitches are in the same position and turns on when the switches are in dierent positions.

BTN1 BTN0 LED0 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0

C B ATable 3: Hardware inputs

If your hardware works, demonstrate the tests for the TA. This is the other half ofyour lab grade. Refer to the Software and Accounts handout for information on backing up yourles, if you wish.

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