16
of Sheet Date: Title: Ver: A B C D 1 2 3 4 D C B A 4 3 2 1 Sheet Size: B Rev: Drawn By GPIO Headers Page 10 U1 Page 8 3.0V@500mA max Linear Regulator Monolithic Regulator 0.9V@3A max Dual Switcher TDI PWR Jack TDO JTAG Chain SCHEM, ROHS COMPLIANT 5V FMC LPC Expansion Connector GMII Differential Clock Clock Socket SMA Clock LEDs DIP Switches TDI FPGA FMC Expansion MODE DIP Switch Push Buttons SP601 EVALUATION PLATFORM TDO USB UART 3.3V@8A max Dual Switcher 1.2V@8A max 1.8V@8A max 2.5V@8A max Buck-Boost Regulator Power Supply JTAG or USB HDR EEPROM: External Config 12V@1A max Other Devices: DDR2 Page 5 Page 6 Page 7 Parallel Flash Page 8 USB JTAG Connector Page 14 Page 10 Page 8 IIC EEPROM and Header Page 10 Page 9 Page 9 Page 9 Page 9 SPI X4 or 0b1010010 0bXXXXX10 J1 U5 J1 J2 or J3 XC6SLX16 U1 SP601 Block Diagram Spartan-6 J4 IIC Addresssing 10/100/1000 Ethernet WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY CHANGE WITHOUT NOTICE. THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") Disclaimer: 0b1010100 PCB P/N: 0431512, 0431608 SCH P/N: 0381290 Test P/N: TSS0121 ART P/N: 1280464 BF 04 1 16 10-20-2009_14:54 C

Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

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Page 1: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

GPIO Headers

Page 10

U1

Page 8

3.0V@500mA maxLinear Regulator

Monolithic Regulator0.9V@3A max

Dual Switcher

TDI

PWRJack

TDO

JTAG Chain

SCHEM, ROHS COMPLIANT

5V

FMC LPC ExpansionConnector GMII

Differential ClockClock SocketSMA Clock

LEDs

DIP Switches

TDI

FPGAFMC Expansion

MODE DIP Switch

Push Buttons

SP601 EVALUATION PLATFORM

TDO

USB UART

3.3V@8A max

Dual Switcher

1.2V@8A max

1.8V@8A max

2.5V@8A max

Buck-Boost Regulator

Power Supply

JTAG or

USB HDR

EEPROM:

External Config

12V@1A max

Other Devices:

DDR2Page 5

Page 6 Page 7

Parallel Flash

Page 8

USB JTAG Connector

Page 14Page 10Page 8

IIC EEPROMand Header

Page 10

Page 9

Page 9

Page 9

Page 9

SPI X4 or

0b1010010

0bXXXXX10

J1

U5

J1

J2 or J3

XC6SLX16

U1

SP601 Block Diagram

Spartan-6

J4

IIC Addresssing

10/100/1000 Ethernet

WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED

WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR

ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA

SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR

USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH

AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION

THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY

OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS

IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO

APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO

ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY

CHANGE WITHOUT NOTICE.

THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")

Disclaimer:

0b1010100

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

BF

04

1 16

10-20-2009_14:54 C

Page 2: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC3V3

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

Y8

Y1

Y3Y4Y5Y6Y7

Y2

OE1_NA1

A3A4

A2

A5

A8A7A6

GND

SN74LV541APWR

OE2_NVCC

IO_L01P_1_A25_F15IO_L01N_1_A24_VREF_1_F16IO_L02P_1_A23_M1A13_C17IO_L02N_1_A22_M1A14_C18

IO_L03P_1_A21_M1RESET_F14IO_L03N_1_A20_M1A11_G14IO_L04P_1_A19_M1CKE_D17IO_L04N_1_A18_M1A12_D18IO_L05P_1_A17_M1A8_H12IO_L05N_1_A16_M1A9_G13IO_L06P_1_A15_M1A10_E16IO_L06N_1_A14_M1A4_E18IO_L07P_1_A13_M1WE_K12IO_L07N_1_A12_M1BA2_K13IO_L08P_1_A11_M1A7_F17IO_L08N_1_A10_M1A2_F18IO_L09P_1_A9_M1BA0_H13IO_L09N_1_A8_M1BA1_H14IO_L10P_1_A7_M1A0_H15IO_L10N_1_A6_M1A1_H16

IO_L11P_1_A5_M1CLK_G16IO_L11N_1_A4_M1CLKN_G18

IO_L12P_1_M1A3_J13IO_L12N_1_M1ODT_K14

IO_L13P_1_GCLK11_M1A5_L12IO_L13N_1_GCLK10_M1A6_L13

IO_L14P_1_GCLK9_IRDY1_M1RASNK15IO_L14N_1_GCLK8_M1CASN_K16IO_L15P_1_GCLK7_M1UDM_L15

IO_L15N_1_GCLK6_TRDY1_M1LDM_L16IO_L16P_1_GCLK5_M1DQ4_H17IO_L16N_1_GCLK4_M1DQ5_H18

IO_L17P_1_A3_M1DQ6_J16IO_L17N_1_A2_M1DQ7_J18IO_L18P_1_A1_M1LDQS_K17IO_L18N_1_A0_M1LDQSN_K18IO_L19P_1_FCS_B_M1DQ2_L17IO_L19N_1_FOE_B_M1DQ3_L18IO_L20P_1_FWE_B_M1DQ0_M16IO_L20N_1_LDC_M1DQ1_M18IO_L21P_1_HDC_M1DQ8_N17

IO_L21N_1_M1DQ9_N18IO_L22P_1_M1DQ10_P17IO_L22N_1_M1DQ11_P18IO_L23P_1_M1UDQS_N15

IO_L23N_1_M1UDQSN_N16IO_L24P_1_M1DQ12_T17IO_L24N_1_M1DQ13_T18IO_L25P_1_M1DQ14_U17IO_L25N_1_M1DQ15_U18

IO_L26P_1_M14IO_L26N_1_VREF_1_N14

IO_L27P_1_L14IO_L27N_1_M13

IO_L28P_1_AWAKE_P15IO_L28N_1_DOUT_P16

VCCO_1_E17VCCO_1_G15VCCO_1_J14VCCO_1_J17VCCO_1_M15VCCO_1_R17

sa16cs324BANK 1SOCKET

IO_L01P_0_HSWAPEN_D4IO_L01N_0_VREF_0_C4

IO_L02P_0_B2IO_L02N_0_A2IO_L03P_0_D6IO_L03N_0_C6IO_L04P_0_B3IO_L04N_0_A3IO_L05P_0_B4IO_L05N_0_A4IO_L06P_0_C5IO_L06N_0_A5IO_L07P_0_F7IO_L07N_0_E6IO_L08P_0_B6

IO_L08N_0_VREF_0_A6IO_L09P_0_E7IO_L09N_0_E8IO_L10P_0_C7IO_L10N_0_A7IO_L11P_0_D8IO_L11N_0_C8IO_L12P_0_G8IO_L12N_0_F8IO_L13P_0_B8IO_L13N_0_A8

IO_L14P_0_GCLK19_D9IO_L14N_0_GCLK18_C9IO_L15P_0_GCLK17_B9IO_L15N_0_GCLK16_A9

IO_L16P_0_GCLK15_D11IO_L16N_0_GCLK14_C11IO_L17P_0_GCLK13_C10IO_L17N_0_GCLK12_A10

IO_L18P_0_G9IO_L18N_0_VREF_0_F9

IO_L19P_0_B11IO_L19N_0_A11IO_L20P_0_G11IO_L20N_0_F10IO_L21P_0_B12IO_L21N_0_A12IO_L22P_0_F11IO_L22N_0_E11IO_L23P_0_D12IO_L23N_0_C12IO_L24P_0_C13IO_L24N_0_A13IO_L25P_0_F12IO_L25N_0_E12IO_L26P_0_B14

IO_L26N_0_VREF_0_A14IO_L27P_0_SCP7_F13IO_L27N_0_SCP6_E13IO_L28P_0_SCP5_C15IO_L28N_0_SCP4_A15IO_L29P_0_SCP3_D14IO_L29N_0_SCP2_C14IO_L30P_0_SCP1_B16IO_L30N_0_SCP0_A16

VCCO_0_D7VCCO_0_B5VCCO_0_E10VCCO_0_B10VCCO_0_D13VCCO_0_B15

sa16cs324BANK 0SOCKET

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

in JTAG chain

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

Jumper to include FMC

Banks 0, 1

Banks 0, 1

C

2 16

10-20-2009_14:56

04

BF

9GPIO_LED_010GPIO_HDR6

D4C4B2A2D6C6B3A3B4A4C5A5F7E6B6A6E7E8C7A7D8C8G8F8B8A8D9C9B9A9D11C11C10A10G9F9B11A11G11F10B12A12F11E11D12C12C13A13F12E12B14A14F13E13C15A15D14C14B16A16

D7B5E10B10D13B15

U1

4FPGA_TDI_BUF2,14 USB_TDIFPGA_TMS_BUF 4

FMC_PWR_GOOD_FLASH_RST_B 6,810GPIO_HDR2

GPIO_HDR5 109GPIO_LED_3

7PHY_TXD17PHY_TXD0

PHY_TXCTL_TXEN 7PHY_TXER 7

7PHY_TXCLK7PHY_TXC_GTXCLK

6FMC_CLK0_M2C_P6FMC_CLK0_M2C_N

F15F16C17C18F14G14D17D18H12G13E16E18K12K13F17F18H13H14H15H16G16G18J13K14L12L13K15K16L15L16H17H18J16J18K17K18L17L18M16M18N17N18P17P18N15N16T17T18U17U18M14N14L14M13P15P16

E17G15J14J17M15R17

U1

1

2X5R10V0.1UF

C169

NCNCNC

11

18

1615141312

17

12

45

3

6

987

10

1920

U21

USB_TMS2,14

SMACLK_N 9SMACLK_P 9

10GPIO_HDR3

1

2

3

J4

H-1X3

1

2

R81100

1/16W5%

2,14USB_TD0

FPGA_TDO 4,6

6FMC_TDO

PHY_MDIO 78FPGA_AWAKE7PHY_CRS7PHY_COL

PHY_MDC 7PHY_RXD0 7PHY_RXD1 7PHY_RXD2 7PHY_RXD3 7PHY_RXD4 7PHY_RXD5 7PHY_RXD6 7PHY_RXD7 7PHY_RXER 7

7PHY_RXCTL_RXDVGPIO_HDR0 10

10GPIO_HDR1FLASH_WE_B 8FLASH_OE_B 8FLASH_CE_B 8FLASH_A0 8FLASH_A1 8FLASH_A2 8FLASH_A3 8

PHY_RXCLK 7

SYSCLK_N 9SYSCLK_P 9PHY_RESET 7

10USB_1_RX10USB_1_TX

PHY_INT 7FLASH_A4 8FLASH_A5 8FLASH_A6 8FLASH_A7 8FLASH_A8 8FLASH_A9 8FLASH_A10 8FLASH_A11 8FLASH_A12 8FLASH_A13 8FLASH_A14 8FLASH_A15 8FLASH_A16 8FLASH_A17 8FLASH_A18 8FLASH_A19 8FLASH_A20 8FLASH_A21 8FLASH_A22 8FLASH_A23 8FLASH_A24 8GPIO_HDR4 10

6FMC_LA04_N6FMC_LA04_P9GPIO_LED_19GPIO_SWITCH_06FMC_LA02_N

FMC_LA02_P 6

6FMC_LA05_N6FMC_LA05_P9GPIO_SWITCH_19GPIO_SWITCH_26FMC_LA03_N6FMC_LA03_P

FMC_LA06_N 6FMC_LA06_P 6

6FMC_LA08_N6FMC_LA08_P6FMC_LA11_N

FMC_LA11_P 6FMC_LA09_N 6FMC_LA09_P 6

6FMC_LA13_N6FMC_LA13_P6FMC_LA15_N6FMC_LA15_P

6FMC_LA01_CC_N6FMC_LA01_CC_P

6FMC_LA00_CC_N6FMC_LA00_CC_P

FMC_LA10_N 6FMC_LA10_P 6FMC_LA16_N 6FMC_LA16_P 6

6FMC_LA07_N6FMC_LA07_P

6FMC_LA12_N6FMC_LA12_P

FMC_LA14_N 6FMC_LA14_P 6

9GPIO_LED_2FPGA_HSWAPEN

NCNCNC

7PHY_TXD27PHY_TXD37PHY_TXD47PHY_TXD57PHY_TXD6

PHY_TXD7 7

2,14 USB_TCK 4FPGA_TCK_BUF6FMC_TCK_BUF

6FMC_TMS_BUF

Page 3: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC1V8

VCC2V5VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC1V8

VCC1V8VCC2V5

CMP_CS_B_P13DONE_V17

IO_L01P_2_CCLK_R15IO_L01N_2_M0_CMP_MISO_T15

IO_L02P_2_CMP_CLK_U16IO_L02N_2_CMP_MOSI_V16

IO_L03P_2_D0_DIN_MISO_MISO1_R13IO_L03N_2_MOSI_CSI_B_MISO0_T13

IO_L04P_2_U15IO_L04N_2_V15

IO_L05P_2_D1_MISO2_T14IO_L05N_2_D2_MISO3_V14

IO_L06P_2_M1_N12IO_L06N_2_D10_P12IO_L07P_2_D11_U13IO_L07N_2_D12_V13

IO_L08P_2_M11IO_L08N_2_N11IO_L09P_2_R11

IO_L09N_2_VREF_2_T11IO_L10P_2_T12IO_L10N_2_V12IO_L11P_2_N10IO_L11N_2_P11IO_L12P_2_M10IO_L12N_2_N9

IO_L13P_2_U11IO_L13N_2_V11

IO_L14P_2_GCLK3_R10IO_L14N_2_GCLK2_T10

IO_L15P_2_GCLK1_D13_U10IO_L15N_2_GCLK0_CFGMCLK_V10

IO_L16P_2_GCLK31_D14_R8IO_L16N_2_GCLK30_D15_T8

IO_L17P_2_GCLK29_T9IO_L17N_2_GCLK28_V9

IO_L18P_2_M8IO_L18N_2_N8IO_L19P_2_U8

IO_L19N_2_VREF_2_V8IO_L20P_2_U7IO_L20N_2_V7IO_L21P_2_N7IO_L21N_2_P8IO_L22P_2_T6IO_L22N_2_V6IO_L23P_2_R7IO_L23N_2_T7IO_L24P_2_N6IO_L24N_2_P7

IO_L25P_2_D7_R5IO_L25N_2_RDWR_B_VREF_2_T5

IO_L26P_2_D3_U5IO_L26N_2_D4_V5IO_L27P_2_D5_R3IO_L27N_2_D6_T3

IO_L28P_2_T4IO_L28N_2_V4

IO_L29P_2_D8_N5IO_L29N_2_D9_P6

IO_L30P_2_INIT_B_U3IO_L30N_2_CSO_B_V3

PROGRAM_B_V2

VCCO_2_U14VCCO_2_R12VCCO_2_U9VCCO_2_P9VCCO_2_R6VCCO_2_U4

sa16cs324BANK 2SOCKET

IO_L01P_3_N4IO_L01N_3_VREF_3_N3

IO_L02P_3_P4IO_L02N_3_P3IO_L03P_3_L6

IO_L03N_3_VREF_3_M5IO_L04P_3_M3DQ14_U2IO_L04N_3_M3DQ15_U1IO_L05P_3_M3DQ12_T2IO_L05N_3_M3DQ13_T1IO_L06P_3_M3UDQS_P2IO_L06N_3_M3UDQSN_P1IO_L07P_3_M3DQ10_N2IO_L07N_3_M3DQ11_N1IO_L08P_3_M3DQ8_M3IO_L08N_3_M3DQ9_M1IO_L09P_3_M3DQ0_L2IO_L09N_3_M3DQ1_L1IO_L10P_3_M3DQ2_K2IO_L10N_3_M3DQ3_K1IO_L11P_3_M3LDQS_L4IO_L11N_3_M3LDQSN_L3IO_L12P_3_M3DQ6_J3IO_L12N_3_M3DQ7_J1

IO_L13P_3_GCLK27_M3DQ4_H2IO_L13N_3_GCLK26_M3DQ5_H1

IO_L14P_3_GCLK25_TRDY2_M3UDM_K4IO_L14N_3_GCLK24_M3LDM_K3

IO_L15P_3_GCLK23_M3RASN_L5IO_L15N_3_GCLK22_IRDY2_M3CASNK5

IO_L16P_3_GCLK21_M3A5_H4IO_L16N_3_GCLK20_M3A6_H3

IO_L17P_3_M3A3_L7IO_L17N_3_M3ODT_K6IO_L18P_3_M3CLK_G3IO_L18N_3_M3CLKN_G1IO_L19P_3_M3A0_J7IO_L19N_3_M3A1_J6IO_L20P_3_M3BA0_F2IO_L20N_3_M3BA1_F1IO_L21P_3_M3A7_H6IO_L21N_3_M3A2_H5IO_L22P_3_M3WE_E3IO_L22N_3_M3BA2_E1IO_L23P_3_M3A10_F4IO_L23N_3_M3A4_F3IO_L24P_3_M3A8_D2IO_L24N_3_M3A9_D1IO_L25P_3_M3CKE_H7IO_L25N_3_M3A12_G6

IO_L26P_3_M3RESET_E4IO_L26N_3_M3A11_D3IO_L27P_3_M3A13_F6IO_L27N_3_M3A14_F5

IO_L28P_3_C2IO_L28N_3_VREF_3_C1

VCCO_3_J5VCCO_3_M4VCCO_3_G4VCCO_3_R2VCCO_3_J2VCCO_3_E2

sa16cs324BANK 3SOCKET

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

Banks 2, 3

Banks 2, 3

BF

C

3 16

10-20-2009_14:56

04

2

1

1%1/16W

DNPR86

N4N3P4P3L6M5U2U1T2T1P2P1N2N1M3M1L2L1K2K1L4L3J3J1H2H1K4K3L5K5H4H3L7K6G3G1J7J6F2F1H6H5E3E1F4F3D2D1H7G6E4D3F6F5C2C1

J5M4G4R2J2E2

U1

6FMC_LA27_NFMC_LA30_P 6

6FMC_LA18_CC_P6FMC_LA18_CC_N

6FMC_LA20_P6FMC_LA20_N

6FMC_LA25_P6FMC_LA25_N6FMC_LA27_P

FMC_LA33_N 6FMC_LA33_P 6

10USB_1_CTS

6FMC_LA17_CC_P6FMC_LA17_CC_N

FMC_LA22_P 6FMC_LA22_N 6

10USB_1_RTS

6FMC_LA19_P6FMC_LA19_N

6FMC_LA23_P6FMC_LA23_N

8FPGA_MOSI_CSI_B_MISO08FPGA_D0_DIN_MISO_MISO1

P13V17R15T15U16V16R13T13U15V15T14V14N12P12U13V13M11N11R11T11T12V12N10P11M10N9U11V11R10T10U10V10R8T8T9V9M8N8U8V8U7V7N7P8T6V6R7T7N6P7R5T5U5V5R3T3T4V4N5P6U3V3V2

U14R12U9P9R6U4

U1

FMC_LA32_P 6

FPGA_ONCHIP_TERM2

FPGA_D2_MISO3 8FPGA_M1 8

FMC_LA21_P 6FMC_LA21_N 6

6FMC_LA31_P6FMC_LA31_N

GPIO_HDR7 10

6FMC_LA26_P6FMC_LA26_N

FMC_LA24_P 6FMC_LA24_N 6

FMC_LA32_N 6

FMC_LA28_N 6FMC_LA28_P 6

DDR2_RAS_B 5DDR2_CAS_B 5DDR2_A5 5

DDR2_UDQS_P 5

DDR2_LDQS_P 5

DDR2_CLK_P 5DDR2_CLK_N 5

FPGA_DDR2_VREF

FPGA_VTEMPFPGA_ONCHIP_TERM1

9CPU_RESET

GPIO_BUTTON0 9

2

1

5%1/16W

4.7KR4

DDR2_BA2 5

2

1 C148

120PF50VNPO

1

2

R141140

1/16W1%

USER_CLOCK 9

1

2

R83100

1/16W5%

21C1

0.1UF 10V

X5R

1 2

1%

1/16W

20.0K

R109

21R110

20.0K

1/16W

1%

2

1

5%1/16W

150R87

5DDR2_BA1

DDR2_A10 5

5DDR2_DQ14

FLASH_D3 8

FLASH_D7 8

8FPGA_M0_CMP_MISO

GPIO_SWITCH_3 9

FPGA_INIT_B 9

IIC_SDA_MAIN 6,10IIC_SCL_MAIN 6,10

8FPGA_CMP_CS_B

FMC_PRSNT_M2C_L 6

FPGA_DONE 9

FPGA_CMP_CLK 8FPGA_CMP_MOSI 8

FLASH_D4 8FLASH_D5 8FLASH_D6 8

SPI_CS_B 88,9FPGA_PROG_B

1

2

R54.7K

1/16W5%

GPIO_BUTTON3 99GPIO_BUTTON1

DDR2_A11 59GPIO_BUTTON2

DDR2_A12 5DDR2_CKE 5DDR2_A9 5DDR2_A8 5DDR2_A4 5

DDR2_WE_B 5DDR2_A2 5DDR2_A7 5

DDR2_BA0 5DDR2_A1 5DDR2_A0 5

DDR2_ODT 5DDR2_A3 5DDR2_A6 5

5DDR2_LDMDDR2_UDM 5DDR2_DQ5 5DDR2_DQ4 5DDR2_DQ7 5DDR2_DQ6 5DDR2_LDQS_N 5

DDR2_DQ3 5DDR2_DQ2 5DDR2_DQ1 5DDR2_DQ0 5DDR2_DQ9 5DDR2_DQ8 5DDR2_DQ11 5DDR2_DQ10 5DDR2_UDQS_N 5

DDR2_DQ13 5DDR2_DQ12 5DDR2_DQ15 5

8FPGA_CCLK

FPGA_D1_MISO2 8

FMC_LA30_N 6

6FMC_LA29_P6FMC_LA29_N

FMC_CLK1_M2C_P 6FMC_CLK1_M2C_N 6

Page 4: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCCINT

VCCINT

VCC2V5

VCC1V8

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCC2V5

VCCAUX_P14VCCAUX_P10VCCAUX_P5VCCAUX_M9VCCAUX_K7VCCAUX_J12VCCAUX_G10VCCAUX_E14VCCAUX_E9VCCAUX_E5VCCAUX_B17VCCAUX_B1

sa16cs324VCCAUX PINS

SOCKET

VCCINT_M12VCCINT_L10VCCINT_J10VCCINT_K11VCCINT_K9VCCINT_H11VCCINT_H9VCCINT_L8VCCINT_J8VCCINT_M7VCCINT_G7

sa16cs324VCCINT PINS

SOCKET

TCK_A17TDI_D15TMS_B18TDO_D16

SUSPEND_R16

sa16cs324DED BANKSOCKET

GND_V18GND_V1

GND_U12GND_U6

GND_T16GND_R18GND_R14GND_R9GND_R4GND_R1

GND_N13GND_M17GND_M6GND_M2

GND_L11GND_L9

GND_K10GND_K8GND_J4

GND_J15GND_J11GND_J9

GND_H10GND_H8

GND_G17GND_G12GND_G5GND_G2

GND_E15GND_D10GND_D5

GND_C16GND_C3

GND_B13GND_B7

GND_A18GND_A1

sa16cs324GND PINSSOCKET

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

VCCO / VCCAUX 2.5V

VCCO Bank 3 1.8V

GND Bank, Decoupling caps

GND Bank, Decoupling caps

VCCINT 1.2V

BF

04

10-20-2009_14:54

164

C

2FPGA_TMS_BUF

2FPGA_TCK_BUF

FPGA_TDO 2,6

V18V1U12U6T16R18R14R9R4R1N13M17M6M2L11L9K10K8J4J15J11J9H10H8G17G12G5G2E15D10D5C16C3B13B7A18A1

U1

A17D15B18D16R16

U1

M12L10J10K11K9H11H9L8J8M7G7

U1

P14P10P5M9K7J12G10E14E9E5B17B1

U1

FPGA_SUSPEND8

2

1 C36

2.2UF

X5R6.3V

0402

1

2

C57

6.3V

0402

X5R

2.2UF

1

2

C101

6.3V

0805

X5R

10UF

1

2

C43

6.3V

0402

X5R

2.2UF

2

1

2.2UF

X5R

0402

6.3V

C42

2

1

10UF

X5R

0805

6.3V

C1041

2

C103

6.3V

0805

X5R

10UF

1

2

C96

6.3V

0805

X5R

10UF2

1

10UF

X5R

0805

6.3V

C97 1

2

C98

6.3V

0805

X5R

10UF

2

1

10UF

X5R

0805

6.3V

C941

2

0805

6.3VX5R

10UF

C91

1

2

C133470UF

6.3VTANT

2

1

TANT6.3V

470UFC134

2

1

TANT6.3V

470UFC135

2

1

10UF

X5R

0805

6.3V

C92

2

1

6.3V

C93

10UF

X5R

0805

2

1

6.3V

C95

10UF

X5R

0805

2

1

6.3V

C37

2.2UF

X5R

0402

2

1

2.2UF

X5R

0402

6.3V

C38

2

1

6.3V

C39

2.2UF

X5R

0402

2

1

2.2UF

X5R

0402

6.3V

C40

2

1

6.3V

C41

2.2UF

X5R

0402

2

1

10UF

X5R

0805

6.3V

C99

2

1

10UF

X5R

0805

6.3V

C102

2

1

10UF

X5R

0805

6.3V

C100 1

2

C105

6.3V

0805

X5R

10UF2

1

10UF

X5R

0805

6.3V

C106

2

1

2.2UF

X5R

0402

6.3V

C44 1

2

C45

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C46 1

2

C47

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C48 1

2

C49

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C50

1

2

C51

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C52 1

2

C53

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C54 1

2

C55

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C56

2

1

10UF

X5R

0805

6.3V

C107 1

2

C108

6.3V

0805

X5R

10UF2

1

10UF

X5R

0805

6.3V

C109

2

1

2.2UF

X5R

0402

6.3V

C58 1

2

C59

6.3V

0402

X5R

2.2UF2

1

2.2UF

X5R

0402

6.3V

C60

2FPGA_TDI_BUF

Page 5: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC1V8

VCC1V8

VCC1V8 VCC1V8VCC1V8

VTT_DDR2

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

EDE1116ACBG_8E_E

VREF

VDLL

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ5

VDDQ4

VDDQ3

VDDQ2

VDDQ10

VDDQ1

VDD5

VDD4

VDD3

VDD2

VDD1

UDMLDM

A0

A3A2A1

A5

A7A6

A4

A8A9A10A11A12

BA0BA1BA2

WE

RASCAS

CKCKCKE

ODT

CS

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSS1

VSS2

VSS3

VSS4

VSS5

VSSDL

NC5NC4NC3NC2NC1

UDQSUDQS

LDQSLDQS

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

DDR2 SDRAM

DDR2 Decoupling

DDR2 SDRAM

BF

10-20-2009_14:56

165

C

04

DDR2_CLK_P3

DDR2_LDQS_P 3

J2

J1

G7

G3

G1

E9

C9

C7

C3

C1

G9

A9

R1

M9

J9

E1

A1

B3F3

M8

N2M7M3

N3

P2N7

N8

P8P3M2P7R2

L2L3L1

K3

K7L7

J8K8K2

K9

L8

A7

B2

B8

D2

D8

E7

F2

F8

H2

H8

A3

E3

J3

N1

P9

J7

R8R7R3E2A2

A8B7

E8F7

B9B1D9D1D3D7C2C8F9F1H9H1H3H7G2G8

U2

1

2

0402

6.3VX5R

2.2UF

C62

2

1 C61

2.2UF

X5R6.3V

0402

2

1 C20.1UF

10VX5R

NC

DDR2_BA23

21

5%

1/16W

100

R85

21R111

20.0K

1/16W

1%

1 2

1%1/16W

20.0K

R112

1

2

R6849.9

1/16W1%

DDR2_CAS_B3

DDR2_BA13DDR2_BA03

DDR2_A83

DDR2_A123DDR2_A113DDR2_A103DDR2_A93

DDR2_A73DDR2_A63DDR2_A53DDR2_A43DDR2_A33DDR2_A23DDR2_A13DDR2_A03

2

1

1%1/16W

49.9R66

21C7

0.1UF 10V

X5R

1

2

R84100

1/16W5%

NC

1

2

R6449.9

1/16W1%

2

1

1%1/16W

49.9R72

2

1

1%1/16W

49.9R70

1

2

R6949.9

1/16W1%

1

2

R64.7K

1/16W5%

NCNCNC

2

1

5%1/16W

4.7KR7

1

2

R7149.9

1/16W1%

1

2

R7649.9

1/16W1%

2

1

1%1/16W

49.9R75

1

2

R7449.9

1/16W1%

2

1

1%1/16W

49.9R73

2

1

1%1/16W

49.9R80

1

2

R7949.9

1/16W1%

2

1

1%1/16W

49.9R78

1

2

R7749.9

1/16W1%

2

1

1%1/16W

49.9R63

1

2

R6249.9

1/16W1%

2

1

1%1/16W

49.9R651

2

R6749.9

1/16W1%

DDR2_UDQS_P 3

DDR2_LDQS_N 3

DDR2_DQ15 3DDR2_DQ14 3DDR2_DQ13 3DDR2_DQ12 3DDR2_DQ11 3DDR2_DQ10 3DDR2_DQ9 3DDR2_DQ8 3DDR2_DQ7 3DDR2_DQ6 3DDR2_DQ5 3DDR2_DQ4 3DDR2_DQ3 3DDR2_DQ2 3DDR2_DQ1 3DDR2_DQ0 3

DDR2_UDM 3

DDR2_UDQS_N 3

DDR2_LDM 3

1

2 X5R10V

0.1UFC3

2

1 C40.1UF

10VX5R

1

2 X5R10V

0.1UFC5

2

1 C60.1UF

10VX5R

DDR2_WE_B3

DDR2_RAS_B3

DDR2_CLK_N33 DDR2_CKE

3 DDR2_ODT

Page 6: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC12V_PVCC3V3

VCC3V3

VCC3V3

VCC2V5

VCC3V3

12P0V_1

12P0V_2

3P3V_1

DP0_C2M_N

DP0_C2M_P

DP0_M2C_N

DP0_M2C_P

GA0

LA06_N

LA06_P

LA10_N

LA10_P

LA14_N

LA14_P

LA18_N_CC

LA18_P_CC

LA27_N

LA27_P

SCL

SDA

ASP_134603_01

3P3VAUX

3P3V_2

3P3V_3

3P3V_4

GA1

GBTCLK0_M2C_N

GBTCLK0_M2C_P

LA01_N_CC

LA01_P_CC

LA05_N

LA05_P

LA09_N

LA09_P

LA13_N

LA13_P

LA17_N_CC

LA17_P_CC

LA23_N

LA23_P

LA26_N

LA26_P

PG_C2M

TCK

TDI

TDO

TMS

TRST_L

ASP_134603_01

CLK1_M2C_N

CLK1_M2C_P

LA00_N_CC

LA00_P_CC

LA03_N

LA03_P

LA08_N

LA08_P

LA12_N

LA12_P

LA16_N

LA16_P

LA20_N

LA20_P

LA22_N

LA22_P

LA25_N

LA25_P

LA29_N

LA29_P

LA31_N

LA31_P

LA33_N

LA33_P

VADJ_3

ASP_134603_01

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_130

GND_41

GND_42

GND_43

GND_44

GND_45

GND_46

GND_47

GND_48

GND_49

GND_50

GND_51

GND_52

GND_53

GND_54

GND_55

GND_56

GND_57

GND_58

GND_59

GND_60

GND_61

GND_62

GND_63

GND_64

GND_65

GND_66

GND_67

GND_68

GND_69

GND_70

GND_71

GND_72

GND_73

ASP_134603_01

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

CLK0_M2C_N

CLK0_M2C_P

LA02_N

LA02_P

LA04_N

LA04_P

LA07_N

LA07_P

LA11_N

LA11_P

LA15_N

LA15_P

LA19_N

LA19_P

LA21_N

LA21_P

LA24_N

LA24_P

LA28_N

LA28_P

LA30_N

LA30_P

LA32_N

LA32_P

PRSNT_M2C_L

VADJ_4

VREF_A_M2C

ASP_134603_01

VCC2V5

VCC2V5

VCC3V3

VCC12V_P

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

FMC LPC ConnectorANSI/VITA 57.1-2008 Version 1.1

FMC LPC Connector

FMC Power Good LED

04

10-20-2009_14:56

166

C

BF

1

32

Q1

NDS331N

2

1 R95200

1/16W5%

1

2

C1701UF

50VELEC

1

2X7R16V1UF

C172

2

1 C171

1UF16VX7R

FMC_TMS_BUF 2

FMC_TCK_BUF 2

FMC_PWR_GOOD_FLASH_RST_B 2,6,8

FMC_LA17_CC_N 3

H5

H4

H8

H7

H11

H10

H14

H13

H17

H16

H20

H19

H23

H22

H26

H25

H29

H28

H32

H31

H35

H34

H38

H37

H2

H40

H1

J1

2

1

5%1/16W

10KR116

21

LED-GRN-SMT

DS1

G1

G4

G5

G8

G11

G14

G17

G20

G23

G26

G29

G32

G35

G38

G40

H3

H6

H9

H12

H15

H18

H21

H24

H27

H30

H33

H36

H39

C1

C4

C5

C8

C9

C12

C13

C16

C17

C20

C21

C24

C25

C28

C29

C32

C33

C36

C38

C40

D2

D3

D6

D7

D10

D13

D16

D19

D22

D25

D28

D37

D39

J1

G3

G2

G7

G6

G10

G9

G13

G12

G16

G15

G19

G18

G22

G21

G25

G24

G28

G27

G31

G30

G34

G33

G37

G36

G39

J1

D32

D36

D38

D40

D35

D5

D4

D9

D8

D12

D11

D15

D14

D18

D17

D21

D20

D24

D23

D27

D26

D1

D29

D30

D31

D33

D34

J1

C35

C37

C39

C3

C2

C7

C6

C34

C11

C10

C15

C14

C19

C18

C23

C22

C27

C26

C30

C31

J1

FMC_CLK1_M2C_N 3

FMC_CLK1_M2C_P 3

FMC_PRSNT_M2C_L 3

FPGA_TDO 2,4

2FMC_TDO

IIC_SDA_MAIN 3,10

FMC_LA27_N 3

IIC_SCL_MAIN 3,10

NC

NC

FMC_CLK0_M2C_P 2

FMC_CLK0_M2C_N 2

FMC_LA02_P 2

FMC_LA02_N 2

FMC_LA04_P 2

FMC_LA04_N 2

FMC_LA07_P 2

FMC_LA07_N 2

FMC_LA11_P 2

FMC_LA11_N 2

FMC_LA15_P 2

FMC_LA15_N 2

FMC_LA19_P 3

FMC_LA19_N 3

FMC_LA21_P 3

FMC_LA21_N 3

FMC_LA24_P 3

FMC_LA24_N 3

FMC_LA28_P 3

FMC_LA28_N 3

FMC_LA30_P 3

FMC_LA30_N 3

FMC_LA32_P 3

FMC_LA32_N 3

FMC_LA05_N 2

FMC_LA26_N 3

FMC_LA26_P 3

FMC_LA23_N 3

FMC_LA23_P 3

FMC_LA17_CC_P 3

FMC_LA13_N 2

FMC_LA13_P 2

FMC_LA09_N 2

FMC_LA09_P 2

FMC_LA05_P 2

FMC_LA01_CC_N 2

FMC_LA01_CC_P 2

FMC_LA33_N 3

FMC_LA33_P 3

FMC_LA31_N 3

FMC_LA31_P 3

FMC_LA29_N 3

FMC_LA29_P 3

FMC_LA25_N 3

FMC_LA25_P 3

FMC_LA22_N 3

FMC_LA22_P 3

FMC_LA20_N 3

FMC_LA20_P 3

FMC_LA16_N 2

FMC_LA16_P 2

FMC_LA12_N 2

FMC_LA12_P 2

FMC_LA08_N 2

FMC_LA08_P 2

FMC_LA03_N 2

FMC_LA03_P 2

FMC_LA00_CC_N 2

FMC_LA00_CC_P 2

NC

NC

NC

NC

NC

FMC_LA06_P 2

FMC_LA06_N 2

FMC_LA10_P 2

FMC_LA10_N 2

FMC_LA14_P 2

FMC_LA14_N 2

FMC_LA18_CC_P 3

FMC_LA18_CC_N 3

FMC_LA27_P 3

NC

FMC_PWR_GOOD_FLASH_RST_B2,6,8

Page 7: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCCINTVCC2V5

VCC2V5

VCC2V5

VCC2V5VCCINT

VCC2V5VCCINT

VCC2V5

VCC2V5

VCC2V5

VCC2V5

VCC2V5

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

VCCINT

XTAL_MA506

TD1_P

TD0_N

TD1_N

TD2_P

TD2_N

TD3_N

TD3_P

VCC

TD0_P

GND

SH2

SH1

10/100/1000

MAGNETICS

RJ45 AND

VSS_127

VDDO_122

DVDD_117

VSS_106

AVDD_104

DVDD_96

VDDOH_97

DVDD_90DVDD_85DVDD_78

VDDOX_71

AVDD_64AVDD_59AVDD_52

VSS_65

VSS_9

CONFIG1

CONFIG3CONFIG4CONFIG5CONFIG6

CRS

HSDAC_N

LED_DPLX

LED_LINK10LED_LINK100

LED_LINK1000

LED_RXLED_TX

MDC

MDI1_N

MDI2_N

MDI3_N

MDIO

RXD1RXD2RXD3

RXD4RXD5RXD6

RXER

SIN_P

SCLK_PSCLK_N

TDI

TDO

TMSTRST_B

TXD0TXD1TXD2TXD3

TXD4TXD5

TXD7

TXER

SOUT_NSOUT_P

TCK

RXCLK

RXD0

RXDV

TXCLK

VSS_43

AVDD_49VDDOX_34

GTXCLK

TXEN

MDI0_P

RSETRESET_BCOMAINT_BCLK125

TXD6

RXD7

COL

SIN_N

CONFIG0

CONFIG2

DVDD_118

VDDOH_73

AVDD_44

DVDD_23DVDD_27

DVDD_17DVDD_12DVDD_6DVDD_2

VDDO_5

VSS_119VSS_116VSS_111VSS_108

VSS_103VSS_102VSS_101

VSS_93VSS_84VSS_83VSS_66

VSS_63VSS_60VSS_58

VSS_1

VSS_15VSS_21VSS_22

VSS_40VSS_38

VSS_45VSS_48VSS_51VSS_55

VDDO_30VDDO_11

SEL_OSC

XTAL1XTAL2

VSSC_74

VSS_94

MDI0_N

MDI1_P

MDI2_P

MDI3_P

HSDAC_P

VDDOH_89

NC_50

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANT

111

111

111

000

PHYADR[1]

PHYADR[4]

PHYADR[2]

ENA_PAUSE

ANEG[0]

ANEG[3]

ENA_XC

PHYADR[3]

ANEG[2] ANEG[1]

DIS_125

DIS_FC DIS_SLEEP

SEL_BDT INT_POL 75/50 OHM

111

010

PHYADR[0]

Bit[0]Pin Bit[2] Bit[1]

VCC2V5

GND

101

100

011

010

001

000

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

HWCFG_MD[0]

HWCFG_MD[3]

HWCFG_MD[1]HWCFG_MD[2]

125 CLK option disabled.Auto crossover enabled.all caps; prefer slave.Auto-Neg en, advertise

GMII to Cu mode.Fiber/copper auto-detect diasabled.Sleep mode disabled.MDC/MDIO selected.Active LOW interrupt50Ohm SERDES option.

Constant MappingPin to

[2:0]Bit

111

110

Pin

LED_LINK10

LED_LINK100

LED_LINK1000

LED_DUPLEX

LED_RX

LED_TX

and are all bidirectional pins.

The PHY MDIP Pins below are

10/100/1000 PHY

LED Silkscreen"10"

"100"

"DUP"

"RX"

"TX"

"1000"

SP601 EVALUATION PLATFORM

Media Dependent Interface Pins (MDIP),

10/100/1000 PHY

advertise the PAUSE bitPHYAddr "00111". Don't111

BF

C

04

7 16

10-20-2009_14:56

127

122

117

106

104

96

97

908578

71

645952

65

9

87

82818079

115

54

95

1009998

9291

35

47

57

62

33

128126125

124123121

8

113

110109

67

72

6968

18192024

2526

29

13

105107

70

7

3

4

10

43

4934

14

16

41

3936373231

28

120

114

112

88

86

118

73

44

2327

171262

5

119116111108

103102101

93848366

636058

1

152122

4038

45485155

3011

77

7675

50

74

94

42

46

56

61

53

89

U3M88E1111

1 2

LED-GRN-SMTDS2

1

2

0805

6.3VX5R

10UF

C1111

2

0805

6.3VX5R

10UF

C110

3

2

6

4

5

8

7

9

1

10 SH1

SH2

P1

RJ45

21

FERRITE-220

F471

X1 25MHZ

21

FERRITE-220

F3

1 2 3 4

5678

CP3

0.01UF

16V

X7R

8 7 6 5

4321

X7R

16V

0.01UF

CP4

8 7 6 5

4321 X5R

10V

0.1UF

CP2

1 2 3 4

5678

CP1

0.1UF

10V

X5R

76

5%

4.7K

RP4

1

2

R94.7K

1/16W5%

2

1

5%1/16W

4.7KR8

1

2

R1814.99K1%

10

6

5%

4.7K

RP4

NCNC

XTAL1_25MHZ_ENET 7XTAL2_25MHZ_ENET7

PHY_CONFIG072

1

5%0R160

2

1 C152

22PF50VNPO

1

2NPO50V22PF

C153

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

PHY_AVDD0

PHY_LED_LINK100-R

MDIP0_CAP

68

RP4

4.7K

5%

12 5%150

RP1

45

5%47

RP3

36

RP3

475%

27

5%47

RP3

18

RP3

475%

96

5%

4.7K

RP4

45

RP2

475%

36

5%47

RP2

27

RP2

475%

18

5%47

RP2

15

RP4

4.7K

5%

41

5%

4.7K

RP4

13

RP4

4.7K

5%

21

5%

4.7K

RP4

NC

MDIP3_CAP MDIP1_CAPMDIP2_CAP

2

1 C840.01UF

16VX7R

1

2X7R50V

1000PFC129

2

1 C1271000PF

50VX7R

1

2X7R50V

1000PFC128

1

2 X7R16V

0.01UFC851

2 X7R16V

0.01UFC83

2

1 C860.01UF

16VX7R

21

DS3LED-GRN-SMT

1 2

LED-GRN-SMTDS4

21

DS5LED-GRN-SMT

1 2

LED-GRN-SMTDS6

21

DS7LED-GRN-SMT

NC

NC

2

1 C1301000PF

50VX7R

2

1 C1311000PF

50VX7R

PHY_LED_LINK10-R

PHY_LED_LINK1000-R

PHY_LED_DUPLEX-R

PHY_LED_RX-R

PHY_LED_TX-R

NC

3 1

RP1

150 5%

14 5%150

RP1

5 1

RP1

150 5%

67 5%150

RP1

8 6

RP1

150 5%

69 5%150

RP1

10 6

RP1

150 5%

PHY_AVDD0

1 2

R1

1M

1/8W

5%

1

2

R31DNP

1/16W1%

1

2

0805

6.3VX5R

10UF

C112 1

2

0805

6.3VX5R

10UF

C113

NC

NC

XTAL2_25MHZ_ENET7XTAL1_25MHZ_ENET7

NC

PHY_CONFIG0 7

NC

PHY_COL2

PHY_RXD72

NC

PHY_RESET2

PHY_TXCTL_TXEN2

PHY_TXC_GTXCLK2PHY_TXCLK2

PHY_RXCTL_RXDV2

PHY_RXD02

2 PHY_RXCLK

NC

NCNC

PHY_TXER2

PHY_TXD32PHY_TXD22PHY_TXD12PHY_TXD02

NC

NC

NC

NCNC

NC

2 PHY_RXER

PHY_RXD62PHY_RXD52PHY_RXD42

PHY_RXD32PHY_RXD22PHY_RXD12

PHY_MDC2

NC

PHY_CRS2

PHY_MDI0_P

PHY_TXD72PHY_TXD62PHY_TXD52PHY_TXD42

PHY_RSET

PHY_COMAPHY_INT2

PHY_MDIO2PHY_MDI0_N

PHY_MDI1_PPHY_MDI1_N

PHY_MDI2_PPHY_MDI2_N

PHY_MDI3_PPHY_MDI3_N

PHY_LED_LINK10PHY_LED_LINK100PHY_LED_LINK1000

PHY_LED_DUPLEX

PHY_LED_TX

PHY_LED_RX

PHY_LED_RX

Page 8: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC2V5

VCC3V3

VCC3V3SDMX-2-X

HDR_1X9

TE28F128J3D075

A1

A10A11A12A13A14A15A16A17

A2

A20A21A22

A24

A3A4A5A6A7A8A9

BYTE_B

CE0CE1CE2

DQ0

DQ10DQ11DQ12DQ13DQ14DQ15

DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

GND2

OE_B

RP_B

STS

VCC0VCC1

VCCQ

WE_B

A0

A19

A23

DQ1

VPEN

GND0GND1

A18

VCC3V0

VCC3V0

VCC3V0

VCC2V5

HDR_1x6

W25Q64VSFIG

CLK

CS_B GND

IO0_DIN

IO1_DOUT IO2_WP_B

IO3_HOLD_B

NC0NC1NC2NC3 NC4

NC5NC6NC7

VCC

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

TMS

TDI

TDO

GND

SPI X4

SPI Select Jumper

SPI Selection

Mode pin DIP switchesSuspend Jumper

ON: SPI X4

OFF: SPI External

Parallel Flash, SPI, CMP, Mode, and Suspend

3V3

TCK

SPI Program Header

Silkscreen:

Parallel Flash, SPI, CMP,Mode, and SuspendSCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

C

04

10-20-2009_14:56

168 BF

16

7 10

15

8 9

1

3456 11

121314

2

U17

FMC_PWR_GOOD_FLASH_RST_B2,6

3,8FPGA_D2_MISO3

FPGA_M0_CMP_MISO 3,8

FPGA_CMP_MOSI 3

1

2

3

4

5

6

J3

DNP

2

1 R1851.8K

1/16W5%

SPIX4_CS_B8

FPGA_D0_DIN_MISO_MISO1 3,8

1

2

5%1/16W

200R190

2

1 R1941.5K

1/16W5%

1

2

R111.0K

1/10W5%

1

2

R101.0K

1/10W5%

1

2

R171.0K

1/10W5%

FPGA_D1_MISO2 3,8

3,9FPGA_PROG_B

3,8FPGA_MOSI_CSI_B_MISO0FPGA_CCLK 3,8

FPGA_D0_DIN_MISO_MISO13,8

1

2X5R10V0.1UF

C11

1

2

R8827.4

1/16W1%

28

18171312111087

27

431

56

26252423222019

31

142

29

33

394145475052

3840444649513436

48

54

16

53

937

43

55

32

5

30

35

15

2142

6

U10

1

2

3

4

5

7

6

8

9

J12

3,8FPGA_D1_MISO2

21R186

100

1/16W

5%

2

1

1%1/16W

DNPR184

1 2

5%1/16W

100

R187

2

1 C8

0.1UF10VX5R

FPGA_M13FPGA_M0_CMP_MISO3,8

SPIX4_CS_B8

2 1

H-1X2

J151

2

R154.7K

1/16W5%

2

1 C9

0.1UF10VX5R

2

1 C10

0.1UF10VX5R

1

2

R164.7K

1/16W5%

SPI_CS_B3,8

12

J14

H-1X2

4 FPGA_SUSPEND

1

2

4

3

SW2

2

1

5%1/16W

4.7KR18

NC

FPGA_CCLK 3,8

SPI_CS_B 3,8

FPGA_CMP_CS_B 3

FPGA_CMP_CLK 3

1

2

R134.7K

1/16W5%

2 FLASH_CE_B

2 FLASH_OE_B2 FLASH_WE_B

FLASH_D73FLASH_D63FLASH_D53FLASH_D43FLASH_D33FPGA_D2_MISO33,8FPGA_D1_MISO23,8

FLASH_A242FLASH_A232FLASH_A222FLASH_A212FLASH_A202FLASH_A192FLASH_A182FLASH_A172FLASH_A162FLASH_A152FLASH_A142FLASH_A132FLASH_A122FLASH_A112FLASH_A102FLASH_A92FLASH_A82FLASH_A72FLASH_A62FLASH_A52FLASH_A42FLASH_A32FLASH_A22FLASH_A12FLASH_A02

NC

NC

2

1

5%1/16W

4.7KR12

2 FPGA_AWAKE

NCNC

NCNCNCNC

12

LED-GRN-SMT

DS8

NCNCNCNCNCNC

NC

1

2

0805

6.3VX5R

10UF

C114

FPGA_MOSI_CSI_B_MISO0 3,8

1

2

5%1/16W

1.5KR195

2

1 R1961.5K

1/16W5%

2

1R191200

1/16W5%

3,8 FPGA_D0_DIN_MISO_MISO1

1

2

5%1/16W

1.8KR197

FPGA_D2_MISO33,8

Page 9: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC2V5

VCC1V8

P2

P1

P3

P4

Pushbutton

VCC3V3 VCC2V5

VCC1V8

VCC2V5

P2

P1

P3

P4

Pushbutton

VCC2V5

SDMX-4-X

VCC2V5VCC1V8

VCC1V8

VCC1V8

VCC2V5

P2

P1

P3

P4

Pushbutton

CON_SMA_ST

CON_SMA_ST

GND

OE

OUT

VCC

OSC

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

P2

P1

P3

P4

Pushbutton

VCC2V5

VCC2V5

SI500D

NCGND

VCCOUT_BOUT

OE

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

NCGND

VCCOUT_BOUT

200MHZ

OE

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

NC pins connected

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

SMA Differential Clock

Single Ended User Clock

Clocks, LEDs, Buttons, Switches

Clocks, LEDs, Buttons, Switches

Differential System Clock

(Alternate Package)

INIT_B = 0, LED: ONINIT_B = 1, LED: OFF

to line upoverlayed footprints

23

654

1U5

BF

04

3-17-2010_8:42

169

C

2,9SYSCLK_P2,9SYSCLK_N

2,9SYSCLK_P2,9SYSCLK_N2

3

654

1U20

DNP

FPGA_INIT_B3

2

1

1%1/16W

27.4R91 1

2

R9227.4

1/16W1%

1

2

R9427.4

1/16W1%

1

2

R8927.4

1/16W1%

1

2

R9027.4

1/16W1%

21

DS10

LED-RED-SMT

2

1

5%1/16W

4.7KR23

2 SMACLK_P

4

3

1

2

SW5

2

1

3

4

SW4

4

3

1

2

SW6

4

1

5

8

X2

110880

1

2 X5R10V

0.1UFC12

1

2

3

4

5

J7

5

4

3

2

1

J8

2

1 C130.1UF

10VX5R

4

3

1

2

SW7

2

1

5%1/16W

4.7KR29

2

1

5%1/16W

4.7KR27

1

2

R264.7K

1/16W5%

USER_CLOCK 3

2 SMACLK_N

FPGA_PROG_B3,8

1

2

R244.7K

1/16W5%

GPIO_LED_32

GPIO_LED_22

GPIO_LED_12

GPIO_LED_02

3 GPIO_BUTTON0

GPIO_BUTTON13

GPIO_BUTTON23

GPIO_BUTTON33

FPGA_DONE3

GPIO_SWITCH_33GPIO_SWITCH_22GPIO_SWITCH_12GPIO_SWITCH_02

21

DS11

LED-GRN-SMT

12

LED-GRN-SMT

DS12

21

DS13

LED-GRN-SMT

1

2

3

4 5

6

7

8

SW8

1

2

R194.7K

1/16W5%

1

2

R113332

1/16W1%

12

LED-GRN-SMT

DS14

1

2

R284.7K

1/16W5%

2

1

5%1/16W

4.7KR201

2

R214.7K

1/16W5%

2

1

5%1/16W

4.7KR22

21

DS9

LED-GRN-SMT

2

1

3

4

SW3

1

2

R32DNP

1/16W1%

2

1

5%1/16W

0R161

1

2

R254.7K

1/16W5%

1

2

R1884.7K

1/16W5%

4

3

1

2

SW9

CPU_RESET3

1

2

R9327.4

1/16W1%

Page 10: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC3V3

SCLSDA

A0A1A2

WP

VCCGND

VCC3V3

VCC2V5

REGIN

CN

R_G

ND

RT

S_O

_B

DT

R_O

_B

DC

D_I

_B

NC

1

NC10

NC

2

NC

3NC4

GPIO3

GPIO2

GPIO1

GPIO0

NC9R

ST

_B

RX

D_I

TX

D_O

SU

SP

EN

D

SU

SP

EN

D_B

DS

R_I

_B

VB

US

VDD

CT

R_G

ND

CT

S_I

_B

D+

D-

GND1

VIO

RI_I_B

VCC3V3

VCC3V3

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

Bridge

USB to RS232

UART, IIC Header/EEPROM, GPIO Headers

Mounting Holes Fiducials

CP2103 USB Self-Powered

(26mA max)

CP2103GM

The VIO voltage must match the appropriate bank IO voltage

IIC Address 0b1010100

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

UART, IIC Header/EEPROM,GPIO Headers

C

10 16

10-20-2009_14:56

04

BF

1 2

R20

40 5%

21

5%0R20

3

1

2

R3305%

2

1

1%1/16W

DNPR162

IIC_SDA_MAIN3,6,10

1

2

R21.0K

1/10W5%

2

1

5%1/10W

1.0KR3

12

J16

H-1X2

NC

5

9

1

2

3

678

4

J9

1

2 X5R10V

0.1UFC14

2

1C167

1UF6.3VX5R

1

2X5R6.3V1UF

C168

2

1C1660.1UF

10VX5R

USB_1_DATA_N

7

29

23

27

28

10

21

13

14

15

16

17

18

19

209

24

25

12

11

26

8

6

30

22

3

4

2

5

1

U4

CP2103GM

NC

1

2 3

4

X3

SP0503BAHT

225MW

1

M9

NC

1

M7

65

123

7

84

U7

M24C08-WDW6TP

1

12

23 45 67 89 10

11

J13

2GPIO_HDR6

GPIO_HDR7 3

12

5%

1/16W

200

R100

2 GPIO_HDR0

2 GPIO_HDR2

GPIO_HDR32

GPIO_HDR12

21R96

200

1/16W

5%

2GPIO_HDR4

GPIO_HDR5 2

21R98

200

1/16W

5%

21R97

200

1/16W

5%

2

1

5%1/16W

4.7KR30

2

1 C150.1UF

10VX5R

IIC_SCL_MAIN3,6,10 IIC_SDA_MAIN 3,6,10

1 2

5%

1/16W

200

R99

2 1R103

200

1/16W

5%

2 1R102

200

1/16W

5%

2 1R101

200

1/16W

5%

1

M1

1

M2

1

M3

1

M4

1

M8

NC NC

NCNC

1

M12

1

M11

NC

1

M10

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

USB_1_VBUS

USB_1_DATA_P

USB_1_TX 2

2USB_1_RX

3USB_1_RTS

3USB_1_CTS

NC

NC

IIC_SCL_MAIN3,6,10

Page 11: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

TP TP

VCC5

VCC5

VCC3V3 VCC2V5

VCC2V5

VCC3V3

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SGND

VCC2V5

SGND

SGND

VCC3V3VCC3V3

XXX

TP

TP

TP TP

VCC5

VCC5

XXX

XXX

XXX

LTM4616

VOUT1_12

VOUT1_11

VOUT1_10

RUN1

SGND1

VOUT1_8

VOUT1_7

VOUT1_6

VOUT1_5

ITHM1

PLLFLTR1

SVIN1

VOUT1_3

VOUT1_2

VOUT1_1

FB1

GND1_30

GND1_29

GND1_27

GND1_26

GND1_25

GND1_24

GND1_23

GND1_22

GND1_21

GND1_20

GND1_19

GND1_18

GND1_15

GND1_14

GND1_13

GND1_12

SW1

GND1_11

GND1_10

GND1_9

GND1_8

MGN1

PHMODE1

MODE1

CLKIN1

BSEL1

GND1_5

GND1_4

GND1_3

GND1_2

GND1_1

GND1_28

GND1_31

GND1_32

GND1_17

GND1_16

GND1_7

GND1_6

VIN1_1

VIN1_2

VIN1_3

VIN1_4

VIN1_5

VIN1_6

VIN1_7

VIN1_8

VIN1_9

VIN1_10

VIN1_11

VIN1_12

VOUT1_9

VOUT1_4

TRACK1

CLKOUT1

ITH1

PGOOD1

LTM4616

VOUT2_12

VOUT2_11

VOUT2_10

VOUT2_9

ITH2

RUN2

SGND2

VIN2_12

VIN2_11

VIN2_10

VIN2_9

VOUT2_8

VOUT2_7

VOUT2_6

VOUT2_5

TRACK2

ITHM2

PLLFLTR2

SVIN2

VIN2_8

VIN2_7

VIN2_6

VIN2_5

VOUT2_4

VOUT2_3

VOUT2_2

VOUT2_1

FB2

VIN2_4

VIN2_3

GND2_27

GND2_26

GND2_25

GND2_24

GND2_23

GND2_22

GND2_21

GND2_20

GND2_19

GND2_18

VIN2_2

VIN2_1

GND2_17

GND2_16

GND2_14

GND2_13

SW2

GND2_11

GND2_10

GND2_9

GND2_8

GND2_7

GND2_6

MGN2

PHMODE2

MODE2

CLKIN2

BSEL2

GND2_5

GND2_4

GND2_3

GND2_2

GND2_1

PGOOD2

CLKOUT2

GND2_32

GND2_31

GND2_30

GND2_29

GND2_28 GND2_12

GND2_15

TP

TP

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

3.3V @ 8A

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

and Switch5V Jack

2.5V @ 8A

Power Module, 3.3V, 2.5V

Power Module, 3.3V, 2.5V

Connect SGND to GND at a single point in the PCB with multiple vias

C

11 16

10-20-2009_14:56

04

BF

2

1

5%1/16W

0R2011

2

R165DNP

1/16W1%

2

1

1%1/16W

DNPR38

1

2

R1630

1/16W5%

LTC_PWR_GOOD11,12,13

SVIN1_3V3 11

2

1 C64

100UF6.3VX5R

1TP6

1TP5

M12

M11

M10

M9

M8

M6

M5

M4

M3

M2

M1

L12

L11

L10

L9

L8

L7

L6

L5

L4

L3

L2

L1

K12

K11

K10

K9

K8

K2

K1

J12

J11

J10

J9

J8

J7

J6

J5

J4

J3

J2

J1

H12

H11

H9

H8

H6

H5

H4

H3

H2

H1

G12

G10

G9

G8

G7

G6

G5

G4

G3

G2

G1

G11

M7

K7

K6

K5

K4

K3 H7

H10

U15

F12

F11

F10

F6

F5

E12

E11

E10

E9

E7

E6

E5

D11

D10

D9

D8

D5

D4

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

B10

B9

B8

B7

B6

B5

B4

B3

B2

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

D3

D6

D7

B12

B11

B1

A12

C1

C2

D1

D2

E1

E2

E3

E4

F1

F2

F3

F4

F9

D12

E8

F7

F8

A11

U15

21

C156

DNP

21

C155

DNP

21

C154

DNP

1

2

R35DNP

1/16W1%

123

SH1SH2

SW1

SPDT

1TP31 TP4

21

DS15

LED-GRN-SMT

1

2

R114560

1/16W5%

1TP11 TP2

1

2 3

J18

PWR_JACK

2

1C157

DNP

1

2

R40DNP

1/16W1%

1

2

R1083.0K

1/16W5%

1

2

R1772.2K

1/16W5%

SVIN2_2V5 11

SYNCCLK_90 11

SVIN2_2V5 11SVIN2_2V511

SYNCCLK_18012

SVIN1_3V311

2

1 C119

22UF

X5R10V

1

2DNP

C139

2

1 C138

DNP

1

2DNP

C140

2

1

5%1/16W

0R168 1

2

R1670

1/16W5%

2

1 C66

100UF6.3VX5R

2

1 C65

100UF6.3VX5R

1

2

R155100K

1/16W1%

2

1

1%1/16W

100KR154

1

2

R36DNP

1/16W1%

2

1

5%1/16W

0R164 1

2

R14220K

1/16W5%

1

2

R34DNP

1/16W1%

1

2

R11810K

1/16W5%

2

1C163

47PF50VNPO

NC

NC

NC

2

1

5%1/16W

10KR119

2

1

5%1/16W

20KR1431

2

R14520K

1/16W5%

1

2

R12010K

1/16W5%

1

2NPO50V47PF

C162

2

1

5%1/16W

0R166

2

1

5%1/16W

20KR144

2

1

1%1/16W

DNPR37 1

2

R1824.99K

1/16W1%

VCC5_TMP

2

1 C67

100UF6.3VX5R

2

1 C68

100UF6.3VX5R

2

1

1%1/16W

DNPR39

2

1 C141

DNP

1

2 10VX5R

22UF

C120

2

1 C121

22UF

X5R10V

1

2 10VX5R

22UF

C122

SYNCCLK_90 11NC

NC

SVIN1_3V311

1TP141 TP15

LTC_PWR_GOOD11,12,13

Page 12: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC3V3

VCC3V3

TP

VCC5VCC5

VCC5

TP

TP

XXX

SGND

VCC3V3

SGND ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

SGND

VCC1V8 VCCINT

VCCINT

VCCINTVCC1V8

TPXXX

VCC1V8

XXX

XXX

LTM4616

VOUT1_12

VOUT1_11

VOUT1_10

RUN1

SGND1

VOUT1_8

VOUT1_7

VOUT1_6

VOUT1_5

ITHM1

PLLFLTR1

SVIN1

VOUT1_3

VOUT1_2

VOUT1_1

FB1

GND1_30

GND1_29

GND1_27

GND1_26

GND1_25

GND1_24

GND1_23

GND1_22

GND1_21

GND1_20

GND1_19

GND1_18

GND1_15

GND1_14

GND1_13

GND1_12

SW1

GND1_11

GND1_10

GND1_9

GND1_8

MGN1

PHMODE1

MODE1

CLKIN1

BSEL1

GND1_5

GND1_4

GND1_3

GND1_2

GND1_1

GND1_28

GND1_31

GND1_32

GND1_17

GND1_16

GND1_7

GND1_6

VIN1_1

VIN1_2

VIN1_3

VIN1_4

VIN1_5

VIN1_6

VIN1_7

VIN1_8

VIN1_9

VIN1_10

VIN1_11

VIN1_12

VOUT1_9

VOUT1_4

TRACK1

CLKOUT1

ITH1

PGOOD1

LTM4616

VOUT2_12

VOUT2_11

VOUT2_10

VOUT2_9

ITH2

RUN2

SGND2

VIN2_12

VIN2_11

VIN2_10

VIN2_9

VOUT2_8

VOUT2_7

VOUT2_6

VOUT2_5

TRACK2

ITHM2

PLLFLTR2

SVIN2

VIN2_8

VIN2_7

VIN2_6

VIN2_5

VOUT2_4

VOUT2_3

VOUT2_2

VOUT2_1

FB2

VIN2_4

VIN2_3

GND2_27

GND2_26

GND2_25

GND2_24

GND2_23

GND2_22

GND2_21

GND2_20

GND2_19

GND2_18

VIN2_2

VIN2_1

GND2_17

GND2_16

GND2_14

GND2_13

SW2

GND2_11

GND2_10

GND2_9

GND2_8

GND2_7

GND2_6

MGN2

PHMODE2

MODE2

CLKIN2

BSEL2

GND2_5

GND2_4

GND2_3

GND2_2

GND2_1

PGOOD2

CLKOUT2

GND2_32

GND2_31

GND2_30

GND2_29

GND2_28 GND2_12

GND2_15

TP

TP

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

1.8V @ 8A 1.2V or 1.0V @ 8A

Power Module, 1.2V/1.0V, 1.8V

Power Module, 1.2V/1.0V, 1.8V

Connect SGND to GND at a single point in the PCB with multiple vias

Board Power Good LED

BF

04

10-20-2009_14:56

1612

C

2

1

5%1/16W

0R202

2

1

1%1/16W

DNPR173

2

1

1%1/16W

DNPR46

2

1

5%1/16W

0R170

12 SVIN2_1V2

1

2

R42DNP

1/16W1%

21

1%

1/16W

DNP

R199

21

5%

1/16W0

R200

1

2

R1690

1/16W5%

1

2

R41DNP

1/16W1%

11,12,13LTC_PWR_GOODLTC_PWR_GOOD

11,12,13

11,12,13 LTC_PWR_GOOD

1TP16

1TP9

M12

M11

M10

M9

M8

M6

M5

M4

M3

M2

M1

L12

L11

L10

L9

L8

L7

L6

L5

L4

L3

L2

L1

K12

K11

K10

K9

K8

K2

K1

J12

J11

J10

J9

J8

J7

J6

J5

J4

J3

J2

J1

H12

H11

H9

H8

H6

H5

H4

H3

H2

H1

G12

G10

G9

G8

G7

G6

G5

G4

G3

G2

G1

G11

M7

K7

K6

K5

K4

K3 H7

H10

U19

F12

F11

F10

F6

F5

E12

E11

E10

E9

E7

E6

E5

D11

D10

D9

D8

D5

D4

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

B10

B9

B8

B7

B6

B5

B4

B3

B2

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

D3

D6

D7

B12

B11

B1

A12

C1

C2

D1

D2

E1

E2

E3

E4

F1

F2

F3

F4

F9

D12

E8

F7

F8

A11

U19

1

2NPO50V47PF

C165

21

C161

DNP

SVIN1_1V812

2

1C160

DNP

21

C158

DNP

1TP7

1

2

R44DNP

1/16W1%

2

1

1%10KR58

1/16W

1

2

R5714.7K

1%1/16W

2

1C164

47PF50VNPO

1

2

R43DNP

1/16W1%

1

2

R564.87K

1/16W1%

SVIN2_1V2 12

SVIN2_1V2 12

SYNCCLK_270 12

SVIN1_1V8 12SVIN1_1V812

2

1 C144

DNP

1

2 10VX5R

22UF

C125

2

1 C124

22UF

X5R10V

1

2 10VX5R

22UF

C123

2

1

1%1/16W

DNPR45

2

1

5%1/16W

0R171

2

1 C71

100UF6.3VX5R

NC

1

2

R12210K

1/16W5%

1

2

R14920K

1/16W5%

2

1

5%1/16W

0R174

2

1

1%1/16W

DNPR47 1

2

R1834.99K

1/16W1%

1

2

R157100K

1/16W1%

1

2

R12310K

1/16W5%

2

1

5%1/16W

20KR148

2

1

1%1/16W

100KR156

1

2

R14720K

1/16W5%

2

1

5%1/16W

10KR121

2

1

5%1/16W

20KR146

NC

NC

2

1 C69

100UF6.3VX5R

2

1 C70

100UF6.3VX5R

2

1 C72

100UF6.3VX5R

2

1 C73

100UF6.3VX5R

1

2

R1720

1/16W5%

2

1 C142

DNP

1

2DNP

C143

2

1 C145

DNP

21

C159

DNP

2

1 C126

22UF

X5R10V

SYNCCLK_270 12SYNCCLK_18011

NC

1 TP8

1TP10

1 TP17

2

1

5%1/16W

10KR193

2

1 R192200

1/16W5%

3

21

Q2

21

LED-GRN-SMT

DS17

Page 13: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC5

VCC5

XX

VCC3V3 VTT_DDR2

VCC1V8

VCC12V_P

XX

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

XX

0.47UH

IHLP-2525CZ-01 0.47

VCC3V0

4.7UH

DO3316P-472

TP

TP

TP

LT1763CS8

BYP

GND3

GND6

GND7

OUT

ADJ

SHDN

IN

FB

GND

NFB SS

TABVC

VIN

VSW

LT1371CR

SVIN

PGOOD

ITH

VFB

RTVREF

RUN/SS

SGND

PVIN1

SW1

SW2

PGND1

PGND2

SWVFB

SW3PVIN2

TAP

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

0.9V @ 3A

12V @ 1A

Place near U13

3.0V @ 500mA

Power Supplies, 12V, 3.0V, 0.9V

Power Supplies, 12V, 3.0V, 0.9V

Connect SGND to PGND at a single point with multiple vias

04

BF

10-20-2009_14:56

1613

C

11,12 LTC_PWR_GOOD

1

2

C893.3UF

25VTANT

1

2

C11622UF

16VTANT

2

1C136

47UFX5R

6.3V

2

1 C63

2.2UF16VX5R

2

1 C137

47UF16VX5R

1

2

C11722UF

35VTANT

8

14

15

11

10

4

3

5

16

9

1

7

2

6

12

13

17

U18

LTC3413

2

4

3 6

81

7

5

U8

4

3

6

7

1

2

5

8U11

1TP11

1

2X5R6.3V100UF

C77

2

1 C76

100UF6.3VX5R

1

2X5R6.3V100UF

C75

1

2

R1750

1/16W5%

1TP13

1TP12

1 2

L2

12

L1

2 1

D1

MBRS330T3

30V3.0A

1

2

R5953.6K1%

VTT_SGND

1

24700PF

C147

1

2

R615.11K1%

1

2

R178300K

1/16W5%

2

1 C81

0.047UF16VX5R

VTT_SGND

1

2X5R6.3V100UF

C78

2

1 C146

100PF50VNPO

2

1 C132

2200PF50VXR7

2

1 C74

100UF6.3VX5R

1

2X5R6.3V100UF

C80

2

1 C79

100UF6.3VX5R

2

1 C88

330PF50VX7R

NC

2

1

1%1/16W

100KR158

2

1 R1042.0K

1/16W5%

2

1

1%6.19KR60

1

2 X5R10V

0.1UFC16

1

2

C11822UF

16VTANT

12

R49

38.3

21

R48

26.1

NC

Page 14: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

B1

E

P

B1

B1

B1

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

B1

B1

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

AGND

AVCC

BKPT

CLKOUT

CTL0_FLAGA

CTL1_FLAGB

CTL2_FLAGC

CTL3

CTL4

CTL5

D+

D-

IFCLK

INT4

NC1

NC2

NC3

PA0_INT0

PA1_INT1

PA2_SLOE

PA3_WU2

PA4_FIFOADR0

PA5_FIFOADR1

PA6_PKTEND

PA7_FLAGD

PB0_FD0

PB1_FD1

PB2_FD2

PB3_FD3

PB4_FD4

PB5_FD5

PB6_FD6

PB7_FD7

PC0_GPIFADR0

PC1_GPIFADR1

PC2_GPIFADR2

PC3_GPIFADR3

PC4_GPIFADR4

PC5_GPIFADR5

PC6_GPIFADR6

PC7_GPIFADR7

PD0_FD8

PD1_FD9

PD2_FD10

PD3_FD11

PD4_FD12

PD5_FD13

PD6_FD14

PD7_FD15

PE0_T0OUT

PE1_TIOUT

PE2_T2OUT

PE3_RXD0OUT

PE4_RXD1OUT

PE5_INT6

PE6_T2EX

PE7_GPIFADR8

RDY0

RDY1

RDY2

RDY3

RDY4

RDY5

RESERVED

RXD0

RXD1

SCL

SDA

T0

T1

T2

TXD0

TXD1

WAKEUP

XTALIN

XTALOUT

INT5

RD

RESET

WR

GND;2,19,21,39,48,50GND;65,75,94,99

PORT E

PORT A

PORT C

PORT D

PORT B

VCCINT

GPIF

GPIF

PORT E

PORT A

PORT E

VCC3V3

BIT_CLOCK

BUFFER_OE

BUS_ENABLE

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

CTRL1

CTRL2

DONE

DONE_INH

DONE_SM0

DONE_SM1

DONE_SM2

DOWN_CNT0

DOWN_CNT1

DOWN_CNT2

DOWN_CNT3

DOWN_CNT4

EXTEND

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

GPIF_D15

IDLE_FLAG

INIT_IN

INIT_OUT

JTP_CMD0

JTP_CMD1

JTP_CMD2

LAST_BIT

LAST_WORD

RDY1

RDY2

SHIFT_CLK

SPARE_COM

SPARE_P065

SPARE_P071

SPARE_P073

SPARE_P074

SPARE_P076

SPARE_P077

SPARE_P078

SPARE_P079

SPARE_P080

SPARE_P081

SPARE_P082

SPARE_P085

SPARE_P086

SPARE_P087

SPARE_P089

SPARE_P090

SPARE_P091

SPARE_P092

SPARE_P099

START

TAP_STATE0

TAP_STATE1

TAP_STATE2

TAP_STATE3

TCK

TCK_CCLK

TDI

TDI_DIN

TDO

TDO_B

TDO_SAMPLE_CLOCK

TMS

TMS_LEVEL

TMS_PROG

VERSION

GND;21,25,31,62GND;69,75,84,100

BANK 2

BANK 1

BANK 1

BANK 1

BANK 1

BANK 1

BANK 2

VCCINTVAUXVCCIO1VCCIO2

TAP

BANK 2

BANK 2

GND

SHLD4

VBUS

D_N

D_P

SHLD1

SHLD2

SHLD3

ID

USB_MINI_B

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

LEGEND:

COMPONENTS TO BE LOADED FOR THE PRODUCTION

ASSEMBLY VERSION ONLY.

LOCAL 2MM CABEL CONNECTOR J1.

OPTIONAL NETS ROUTED IN PARALLEL TO

AND/OR DIAGNOSTICS.

OPTIONAL COMPONENTS THAT SUPPORT DEBUG

SCHWEIGLER

USB

CONVERTER

6 PLACES

3 PLACES

USB CONTROLLER

CONNECTOR

PARALLEL TO SERIAL

NOTE: EMBEDDED VERSION

2 PLACES

N/CFROM JTAGTO

LAST DEVICE TDO

FIRST DEVICE TDI

TARGET INTERFACE CONNNECTIONS

3.3V INTERFACE TO LOCAL JTAG OR SLAVE-SERIAL DEVICE CHAIN.

AND EMBEDDED_TMS WITH LVDS BUFFERS.

14-JUNE-2006

IS NOT BUS POWERED

TCK ALL DEVICES

TMS ALL DEVICES

FOR LONG CHAINS OR TRACES, DISTRIBUTE EMBEDDED_TCK

OF THE NETS MARKED TO FACILITATE FASTER IN-CIRCUIT

RE-PROGRAMMING OF THE CPLD DURING BOARD TEST.

ASSEMBLY FOOTPRINT IS RECOMMENDED FOR THE PWB LAYOUT.

NOTE:

J1 DOES NOT NEED TO BE POPULATED DURING PRODUCTION, BUT THE

MAKE PARALLEL CONNECTIONS TO J1 (OPTION B) AT EACH

3 PLACES

FPGA_TMS

USB_HEADER_TDI

JTAG_TDO

EMBEDDED_INIT NO CONNECTION

FPGA_TCK

Embedded USB JTAG: USB Controller, CPLD

FPGA_TCK

USB TYPE BRECEPTACLE

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

0381242

04

14 1610-20-2009_14:56

C

5

9

1

2

3

678

4

J10

NC

NC

1

2

R1984.7K

1/16W5%

22

61

2

14

15

16

17

18

54

55

63

8

3

6

7

97

96

95

94

93

24

77

76

74

73

72

71

85

86

87

89

65

99

11

1

92

91

90

13

10

12

82

78

79

80

81

32

33

34

35

36

37

39

40

41

42

43

44

46

49

50

52

28

70

19

29

30

4

58

64

59

9

53

48

66

45

68

47

60

67

56

83

27

23

U9

PART_NUMBER=XC2C256

VCC3V3;20,38,51VCC3V3;88,98

VCC3V3;5VCC1V8;26,57

2USB_TMS

2USB_TCK

USB_TDI 2

1

2

R11510K

1/16W5%

1

2

R15220K

1/16W5%

21Y1

24MHZ

12

9

28

54

55

56

51

52

76

17

18

22

13

14

15

67

68

69

70

71

72

73

74

34

35

36

37

44

45

46

47

57

58

59

60

61

62

63

64

80

81

82

83

95

96

97

98

86

87

88

89

90

91

92

93

3

4

5

6

7

8

27

41

43

29

30

23

24

25

40

42

79

11

10

84

31

77

32

100

26

U12

PART_NUMBER=CY7C68013A

VCC3V3;1,16,20,33,38VCC3V3;49,53,66,78,85

NC

NC

NC

SPARE_COM

CPLD_TDO 15

CPLD_TDI 15

CPLD_TMS 15

CPLD_TCK 15

2

1 R12810K

1/16W5%

2

1 C17

0.1UF10VX5R

2

1 C82

3.3UF10V

1

2NPO50V11PF

C151

2

1 C150

11PF50VNPO

21R55

15

1/16W

5%

1 2

5%1/16W

15R54

21R53

15

1/16W

5%

USB_TD0 2

EMBEDDED_INIT

1

2

R13910K

1/16W5%

2

1 R12710K

1/16W5%

POR15

USB_SDA15

USB_SCL15

LED_GRN 15

LED_RED 15

SERIAL_NUMBER 15

NC

NC

NC

NC

NC

NC

NC

1

2

R15020K

1/16W5%

2

1 R13810K

1/16W5%

12

5%1/16W

10K

R133

2 1R136

10K

1/16W

5%

12

5%1/16W

10K

R135

2 1R132

10K

1/16W

5%

2

1 R13110K

1/16W5%

2

1 R13010K

1/16W5%

2 1R126

10K

1/16W

5%

12

R125

2 1R124

GPIF_DONE

GPIF_START

JTP_CMD3

VREF_DETECT

VERSION_REQUEST

TDO_SAMPLE_CLK

LAST_WORD

TMS_LEVEL

GPIF_D15

GPIF_D00

GPIF_D01

GPIF_D02

GPIF_D03

GPIF_D04

GPIF_D05

GPIF_D06

GPIF_D07

GPIF_D08

GPIF_D09

GPIF_D10

GPIF_D11

GPIF_D12

GPIF_D13

GPIF_D14

CTRL2

CTRL3

COUNT0

COUNT1

COUNT2

COUNT3

COUNT4

JTP_CMD0

JTP_CMD1

JTP_CMD2

RDY1

RDY2

BIT_CLOCK

1

2

5%1/16W

10KR129

2 1R134

10K

1/16W

5%

12

5%1/16W

10K

R137

2

1

5%1/16W

20KR151

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

2

1

5%1/16W

10KR140

NC

BUFFER_OE

Page 15: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

VCC3V3

GND

GND

GND

GND

GND

TDO

TDI

GND

TMS

VTST

VREF

TCK

INIT

GTST

E

E E

P

GR

A

B

C

D

1234

D

C

B

A

4 3 2 1

Drawing Number:

Date:

Sheet Size: D

Sheet of

Ver:

Rev:

Drawn By

E

F

G

H

E

F

G

H

5678

5678

LAST REVISION:

E

VCC3V3

VCC3V3

VCC3V3

VCC3V3 VCC1V8

VCC3V3

E

EGND

SCL

SDA

VCC

NC

NC

NC

NC

I/O

GND

VCC

DS2411

NC

NC

NC

VCC3V3

MAX6412UK22

GND

VCC

MR

RESET

SRT

SUPERVISORYPOWER

PCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

The Embedded USB JTAG Download circuit on this page is for reference only!This circuit should not be designed into an end customer product or solution.Xilinx will not provide support on this embedded USB JTAG Download circuit.

VENDOR ID

PRODUCT ID

DATA FIELD

I2C EEPROM

LED

SCHWEIGLER

STATUS

DEFAULT

CYPRESS

0x004B4

0x8613

0x03FD

XILINX

EMBEDDED

14-JUNE-2006

DEFAULT PID/VID EEPROM

POWER-ON RESET

BYPASS CAPACITORS

NOTE: PRODUCES 5MS POWER-ON RESET

STATUS LEDS (OPTION A)

PC4 JTAG CONNECTOR (OPTION B)

ELECTRONIC SERIAL NUMBER

0x000D

PROM PRIOR TO ASSEMBLY.

LOW POWER BOOT CONDITIONS

USE FILE 1080058 (HEX) TO PROGRAM THE I2C

Embedded USB JTAG: IIC, POR, Decoupling, LED, JTAG Header, Serial Number

0381242

161510-20-2009_14:56

04

C

1 2

R176 0

1/16W5%

USB_SDA 14

2

5

3

1

4

U14

1

2

C903.3UF

25VTANT

2

1

1%1/16W

100KR159

1

2 X7R16V

0.01UFC87

2

1 C149

1800PF50VX7R

5

3

42

1

6

U6

7

4

3 6

5

81

2

U1324LC00T-SN

2

1 R1062.0K

1/16W5%

USB_SCL 14

1

2

R15320K

1/16W5%

LED_RED14

LED_GRN14

SERIAL_NUMBER14

POR 14

1

2

R180270

1/16W5%

1

2

R179360

1/16W5%

2

1 C35

0.1UF10VX5R

2

1 C28

0.1UF10VX5R

1

2X5R10V0.1UF

C18 1

2X5R10V0.1UF

C25

2

1 C22

0.1UF10VX5R

1

2X5R10V0.1UF

C21

2

1 C19

0.1UF10VX5R

NC

2

1 R1072.0K

1/16W5%

2

1 R1052.0K

1/16W5%

1 2

3

DS16

SSL-LX15IGC

NC

NC

NC

NC

NC

NC

1

2X5R10V0.1UF

C20 1

2X5R10V0.1UF

C23

2

1 C24

0.1UF10VX5R

2

1 C26

0.1UF10VX5R

1

2X5R10V0.1UF

C27

1

2X5R10V0.1UF

C29

2

1 C31

0.1UF10VX5R

1

2X5R10V0.1UF

C30 1

2X5R10V0.1UF

C33

2

1 C32

0.1UF10VX5R

1

2X5R10V0.1UF

C34

1

10

11

12

13

14

2

3

4

5

6

7

8

9

DNP

J11

CPLD_TMS 14

CPLD_TCK 14

CPLD_TDO 14

14CPLD_TDI

NC

NC

Page 16: Xilinx XTP051 - SP601 Schematics XTP051 - SP601 Schematics

NUT_SS_4-40

NUT_SS_4-40

NUT_SS_4-40

RUBBER_BUMPER

RUBBER_BUMPER

RUBBER_BUMPER

RUBBER_BUMPER

ofSheet

Date:

Title:

Ver:A

B

C

D

1234

D

C

B

A

4 3 2 1

Sheet Size: B Rev:

Drawn By

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

MACHINE_SCREW_SS_PHILHD_4-40_X_3-8

NUT_SS_4-40

USB A

USB Mini-B Cable

USB Mini-B

OE

GND

VCC

OUT

OSC

JUMPER_BLOCK_2-PIN JUMPER_BLOCK_2-PIN

5v Power BrickPCB P/N: 0431512, 0431608SCH P/N: 0381290Test P/N: TSS0121ART P/N: 1280464

Half Size Oscillator

SCHEM, ROHS COMPLIANTSP601 EVALUATION PLATFORM

Mechanical Components

Mechanical Components

C

16 16

10-20-2009_14:56

04

BF

PB1

MJB2MJB1

1

4

8

5

MX1

MBHF2100H-27.000MHZVALUE=27MHZ

CBL1

MN1

MS4

MS3

MS2

MS1

MRB4

MRB2

MRB1

MRB3

MN4

MN2

MN3