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UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
R
SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006www.xilinx.com
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com
Revision History
SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006
The following table shows the revision history for this document..
Version Revision
11/23/05 1.0 Initial Xilinx release.
3/3/06 1.1 In USB Controller with Host and Peripheral Ports (25) section, added note indicating non-support for 2nd USB feature.
SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006www.xilinx.com
UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com
Table of Contents
About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SP305 Spartan-3 Development Platform User GuideIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Spartan-3 FPGA (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7AC Adapter and Input Power Switch/Jack (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Power Indicator LED (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8On-board Power Supplies (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Oscillator Sockets (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9DIP Switches (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9User LEDs (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10User Push Buttons (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10User Push Button LEDs (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10CPU Reset Button (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Program Switch (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11JTAG Configuration Port (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Configuration Address and Mode DIP Switches (13) . . . . . . . . . . . . . . . . . . . . . . . . . . 12FPGA HSWAP_EN (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Platform Flash Memory (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Platform Flash Configuration Select (16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Platform Flash Enable and Reset Control (17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Done and INIT LED (18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Error LEDs (Active High) (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13RS-232 Serial Port 1 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14RS-232 Serial Port 2 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14SPI (22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Character x 2-Line LCD (23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ROTARY ENCODER (24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15USB Controller with Host and Peripheral Ports (25) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610/100 SMSC Ethernet MAC/PHY (26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710/100 Intel Ethernet PHY (27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19A/D Converter (AD7928) (28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Stereo AC97 Audio Codec (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VGA Output (30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Differential Clock Input And Output With SMA Connectors (31) . . . . . . . . . . . . . . . . 22Expansion Headers (32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide www.xilinx.com
PS/2 Mouse and Keyboard Ports (33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27ChipScope (34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27CAN Controller (MCP2515 and MPC2551) (35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27DDR SDRAM (36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29ZBT Synchronous SRAM (37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Linear Flash Memory Chips (38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Expansion JTAG Jumper (39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Bank 3 Voltage selection (40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35IIC Bus with 4Kb EEPROM (41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35IFF (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SP305 Spartan-3 Development Platform User Guide www.xilinx.com 1UG216 (v1.1) March 3, 2006
Guide ContentsR
About This Guide
The Xilinx Development Platform allows designers to investigate and experiment with features of the Spartan™-3 family of Xilinx FPGAs. This document describes features and operation of the SP305 Development Platform.
Guide ContentsThis manual contains the following chapter:
• “SP305 Spartan-3 Development Platform User Guide.”
Additional ResourcesTo find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature/index/htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
ConventionsThis document uses the following conventions. An example illustrates each convention.
TypographicalThe following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier fontMessages, prompts, and program files that the system displays
speed grade: - 100
Courier boldLiteral commands that you enter in a syntactical statement ngdbuild design_name
Helvetica bold
Commands that you select from a menu File → Open
Keyboard shortcuts Ctrl+C
2 www.xilinx.com SP305 Spartan-3 Development Platform User GuideUG216 (v1.1) March 3, 2006
Chapter : About This GuideR
Online DocumentThe following conventions are used in this document:
Convention Meaning or Use Example
See the section “Additional Resources” for details.
Refer to “Title Formats” in Chapter 1 for details.
Italic font
Variables in a syntax statement for which you must supply values
ngdbuild design_name
References to other manualsSee the Development System Reference Guide for more information.
Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets [ ]
An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.
ngdbuild [option_name] design_name
Braces A list of items from which you must choose one or more lowpwr =on|off
Vertical bar | Separates items in a list of choices lowpwr =on|off
Vertical ellipsis . . .
Repetitive material that has been omitted
IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . .
Horizontal ellipsis . . . Repetitive material that has been omitted
allow block block_name loc1 loc2 ... locn;
Convention Meaning or Use Example
Blue textCross-reference link to a location in the current document
Red text Cross-reference link to a location in another document
See Figure 2-5 in the Virtex-II Handbook.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.
SP305 Spartan-3 Development Platform User Guide 3UG216 (v1.1) March 3, 2006 www.xilinx.com
IntroductionR
SP305 Spartan-3 Development Platform User Guide
IntroductionThe MicroBlaze™ development kit allows designers to investigate and experiment with features of the Spartan™-3 family of FPGAs. This document describes features and operation of the SP305 Development Platform.
Features• Spartan-3 FPGA (XC3S1500-FG676-10)
• 64MB DDR SDRAM, 32-bit interface running up to 266 MHz data rate
• One differential clock input pair and differential clock output pair with SMA connectors
• One 100 MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator socket
• General purpose DIP switches, LEDs, and push buttons
• Rotary Encoder with a push button shaft
• Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs, 14 spare I/O’s, power, JTAG chain expansion capability, and IIC bus expansion
• Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, and microphone-in (mono) jacks
• Two RS-232 serial port (one stand alone and one attached to the USB Chipset)
• 16-character x 2-line LCD display
• 4Kb IIC EEPROM
• VGA output with 50 MHz / 24-bit video DAC
• PS/2 mouse and keyboard connectors
• ZBT synchronous SRAM (9Mb) on 32-bit data bus with four parity bits
• Intel StrataFlash (or compatible) linear flash memory chips (8MB)
• 10/100 Ethernet Mac-PHY transceiver
• 10/100 Ethernet PHY transceiver
• USB interface chip (Cypress CY7C67300) with host and peripheral ports
• CAN and SPI interface ports
• IFF one wire encryption device
• Xilinx XCF32P Platform Flash configuration storage device
• JTAG configuration port for use with Parallel Cable III or Parallel Cable IV cable
4 SP305 Spartan-3 Development Platform User Guidewww.xilinx.com UG216 (v1.1) March 3, 2006
SP305 Spartan-3 Development Platform User GuideR
• Onboard power supplies for all necessary voltages
• 5V @ 3A AC adapter
• Power indicator LED
Package ContentsIf the user purchased part number HW-SP305-US (EU, UK)
• SP305 Board
• 5 Volt Power Supply
• Evaluation version of the Xilinx ISE and EDK development tools (60 day evaluation)
If the user purchased part number DO-SP305-DVLP-US (UE,UK)
• SP305 Board
• 5 Volt Power Supply
• Full version of the Xilinx ISE and EDK development tools (1 year time-based license)
• USB Download and Debug Cable
• RS232 Null Modem Cable
• RJ45 Ethernet Cable
• Xilinx Embedded Development Kit Reference CD
Additional InformationPlease visit the SP305 web site at http://www.xilinx.com/sp305 for more information about the SP305 Development Platform including:
• Current version of this user guide in PDF format
• Example design files for demonstration of Spartan-3 features and technology
• Demonstration hardware and software configuration files for the Platform Flash configuration storage device, and linear flash memory chips
• MicroBlaze EDK reference design files
• Full schematics in PDF format and ViewDraw schematic format
• PC board layout in Pads PCB format
• Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware Gerber file viewers available on the internet for viewing and printing these files)
• Additional documentation, errata, frequently asked questions, and the latest news
For information about the Spartan-3 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, visit the Spartan-3 web site at http://www.xilinx.com/spartan3.
Additional information is available from the data sheets and application notes supplied by the component manufacturers.
SP305 Spartan-3 Development Platform User Guide 5UG216 (v1.1) March 3, 2006 www.xilinx.com
IntroductionR
Block DiagramFigure 2-1 shows a block diagram of the board.
Figure 2-1: Spartan-3 SP-305 Development Platform Block Diagram
RotaryEncoder
GPIO(Button/LED/DIP Switch
100 MHz XTAL+ User
SMA(Differential In/
Out Clocks)
Dual PS/2
IFF
ChipscopeHigh Speed
Debug
SyncRAM
USBController
Spartan-3FPGA
I/O ExpansionHeader
IIC EEPROM
5V Brick 3A
PlatformFlash
Flash
Flash
SE
L M
AP
SLV
SE
RIA
L
JTA
G
MS
TR
SE
RIA
L
16 x 32Character LCD
CanController
SPI
AC97Audio CODEC
Line Out/Headphone
Video
Mic In/Line in
RS-232 XCVR
VGA
Host
PeripheralPeripheral
Serial
10/100/1000Enet Phy
10/100Enet Phy
DDRSDRAM
DDRSDRAM
32
16
RJ-45
PC
RJ-45
User IICBusJT
AG
JTA
G32
5V to USB and PS/2
TPS543103A SWIFT
TPS543106A SWIFT
TPS543103A SWIFT
TPS54310150mA LDO
12 V
5V
To FPGA Core
1.8 VTo PROM
TPS511003A DDR LDO
1.25 VTo VTT
3.3 VTo FPGA I/O Digital Supply
2.5 V to DDR SDRAM
ug216_01_101105
6 SP305 Spartan-3 Development Platform User Guidewww.xilinx.com UG216 (v1.1) March 3, 2006
SP305 Spartan-3 Development Platform User GuideR
Detailed DescriptionThe SP305 Development Platform is shown in Figure 2-2 (front) and Figure 2-3 (back). The features/components on the board are identified by numbered yellow balloons. These features/components are then detailed or described in respectively numbered sections in the subsequent sections of this document.
Figure 2-2: SP305 Development Platform (front view)
14143030
3232
2323
2626
1919
1818
2222
3434
3737
1010
1111
1212
1313 1717
1515
1616
3636
2424
29292828
2727
2020
2121
2525
3333
5
1
98
6 7
35b35b
35a35a
35e35e
35f35f
2
4
3
3131
UG216_02_101105
SP305 Spartan-3 Development Platform User Guide 7UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
Spartan-3 FPGA (1)A Xilinx XC3S1500-FG676-10 FPGA is installed on the development platform (the board). The FPGA is identified as component (1) in the heading above. The other features/components are numbered accordingly in the subsequent sections.
Configuration
The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP modes. See the “Configuration Options,” page 11 section for more information.
Figure 2-3: SP305 Development Platform (back view)
2
3030
2121
39394040
3333
3636
33334141
29292020
2626
2525
24241212
2525
4242
5
4
35d35d
35c35c
3838
3737
UG216_03_101105
8 SP305 Spartan-3 Development Platform User Guidewww.xilinx.com UG216 (v1.1) March 3, 2006
SP305 Spartan-3 Development Platform User GuideR
I/O Voltage Rails
The FPGA has 7 banks. The I/O voltage applied to each bank is summarized in Table 2-1.
FPGA Bank I/O Voltage Rail
3.3V
2.5V
2.5V
User selectable as 2.5V or 3.3V using jumper J29
3.3V
3.3V
3.3V
2.5V
AC Adapter and Input Power Switch/Jack (2)The SP-305 board ships with a 15W (5V @ 3A) AC adapter. The power connector is a 2.1mm x 5.5mm barrel type plug (center positive). For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter may be required. If a different AC adapter is used, its load regulation should be less than 10% or better than +/- 10%. The power switch turns the board on and off by controlling the supply of 5V to the board.
Power Indicator LED (3)The PWR Good LED lights when the 1.2V, 2.5V, and 3.3V power supplies are all at their nominal operating conditions. If the PWR Good LED is off, blinking, or glowing lightly, a fault condition, such as a short or overload condition, may exist.
On-board Power Supplies (4)Power supply circuitry on the board generates 1.2V, 1.25V, 1.8V, 2.5V, and 3.3V voltages to power the components on the board. The 1.2V, 2.5V, and 3.3V supplies are driven by switching power regulators. When these three switching regulators report they are running at their nominal voltages, the PWR Good LED is turned on.
The diagram in Figure 2-4 shows the power supply architecture and maximum current handling on each supply. Note that the typical operating currents are significantly below
Table 2-1: I/O Voltage Rail of FPGA Banks
0
1
2
3
4
5
6
7
SP305 Spartan-3 Development Platform User Guide 9UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
the maximum capable. The SP-305 board is normally shipped with a 15W power supply which should be sufficient for most applications.
Oscillator Sockets (5)On the back side, the SP305 Development Platform has two crystal oscillator sockets, each wired for standard LVTTL-type oscillators. (Note: A 100 MHz oscillator is pre-installed in the X1 SYSCLK socket.) These connect to the FPGA clock pins as shown in Table 2-2. The oscillator sockets accept half-sized oscillators and are powered by the 3.3V supply.
Label Clock Name FPGA Pin
SYSCLK
USERCLK
DIP Switches (6)There are eight general purpose (active-high) DIP switches connected to the user I/O pins of the FPGA. See Table 2-3 for a summary of these connections.
SW1 FPGA Pin SW1 FPGA Pin
Figure 2-4: Power Supply Diagram
TPS543103A SWIFT
TPS543106A SWIFT
TPS511003A DDR LDO
TPS73118150mA LDO
TPS543103A SWIFT
5V Brick3A
1.25V
to VTT
1.2V
5V
5V to USB and PS/2
2.5V to DDR SDRAM
to FPGA Core
3.3V
to FPGA I/O. Digital Supply
1.8V
to PROM UG216_04_101105
Table 2-2: Oscillator Socket Connections
X1 AD13
X6 AE14
Table 2-3: DIP Switches Connections (SW1)
1 AE8 5 AB9
2 AF8 6 AC9
3 Y9 7 AD9
4 AA9 8 AE9
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SP305 Spartan-3 Development Platform User GuideR
User LEDs (7)There are 4 green LEDs are general purpose LEDs arranged in a row. The LEDs are active high LEDs directly controllable by the FPGA:
Table 2-4 summarizes the LED definitions and connections
ReferenceDesignator
Label/Definition Color FPGA Pin
GPIO LED 0
GPIO LED 1
GPIO LED 2
GPIO LED 3
.
User Push Buttons (8)There are five active-high user push buttons available for general purpose usage and are arranged in a North-East-South-West-Center orientation (only the West one is cited in Figure 2-2, page 6). The user push button connections are summarized in Table 2-5.
ReferenceDesignator
Label/Definition FPGA Pin
GPIO Switch North
GPIO Switch South
GPIO Switch East
GPIO Switch West
GPIO Switch Center
User Push Button LEDs (9)There are 5 green LEDs positioned next to the North-East-South-West-Center oriented push buttons (only the Center one is called out in Figure 2-2, page 6). The LEDs are active high and are directly controllable by the FPGA:
Table 2-6 summarizes the LED definitions and connections.
Table 2-4: User LED Connections
DS15 Green J3
DS4 Green J4
DS5 Green D22
DS6 Green E22
Table 2-5: User Push Button Connections
SW3 H6
SW4 F3
SW5 G6
SW7 G4
SW6 F1
Table 2-6: User LED Connections
ReferenceDesignator
Label/Definition Color FPGA Pin
DS14 LED North Green K6
DS3 LED South Green G5
DS11 LED East Green F4
SP305 Spartan-3 Development Platform User Guide 11UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
CPU Reset Button (10)The CPU reset button is an active low push button intended to be used as a system or user reset button. This button is wired to an FPGA I/O pin so it can also be used as a general purpose button (see Table 2-7).
ReferenceDesignator
Label/Definition FPGA Pin
FPGA CPU RESET
Program Switch (11)When pressed, this switch grounds the Program pin of the FPGA. This clears the FPGA.
JTAG Configuration Port (12)The JTAG configuration port for the board (J20) allows for device programming and FPGA debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products. Third-party configuration products may also be available. The JTAG chain may also be extended to an expansion board by setting jumper J26 accordingly. See the “Configuration Options,” page 11 section for more information.
Configuration Options
The FPGA on the SP-305 Development Platform can be configured through JTAG by 2 devices:
• Parallel Cable IV cable (JTAG)
• Platform Flash memory
The following section provides an overview of the possible ways the board can be configured.
DS13 LED West Green F2
DS12 LED Center Green H7
Table 2-6: User LED Connections (Continued)
ReferenceDesignator
Label/Definition Color FPGA Pin
Table 2-7: CPU Reset Connections
SW10 G2
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The FPGA and Platform Flash memory can be configured through the JTAG port. The JTAG chain of the board is illustrated in Figure 2-5.
The chain starts at the PC4 connector and goes through the Platform Flash memory, the FPGA, and an optional extension of the chain to the expansion card. Jumper J26 determines if the JTAG chain should be extended to the expansion card.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug. The JTAG chain is also used to program the Platform Flash memory.
The PC4 JTAG connection to the JTAG chain allows a host PC to download bitstreams to the FPGA using the iMPACT software tool. PC4 also allows debug tools such as the ChipScope™ Pro Analyzer or a software debugger to access the FPGA.
Configuration Address and Mode DIP Switches (13)This 3-position DIP switch controls the configuration address and FPGA configuration mode.
The three switches choose one of eight possible configuration addresses. It provides the The Platform Flash memory supports up to four different images.
The three rightmost DIP switches set the FPGA configuration mode pins M2, M1, and M0 as shown in Table 2-8.
M2 M1 M0 Mode
Master Serial
Slave Serial
Master Parallel (SelectMAP)
Slave Parallel (SelectMAP)
JTAG
FPGA HSWAP_EN (14)The default for the Spartan3 FPGA is to have an internal weak pull-up enabled on the HSWAP_EN FPGA pin. The jumper J37 is used to control if a weak pull-up is present on the user I/O during configuration. When there is no jumper on J37, a weak pull-up is applied to the HSWAP_EN pin. The effect will be to disable internal pull-ups on User I/O during configuration. If a jumper is placed on J37, the HSWAP_EN pin will be grounded.
Figure 2-5: JTAG Chain
PC4
TDI TDO TDI TDO
PlatFlash FPGA
TDI
TDO
Expansion
ug216_05_101105
Table 2-8: Configuration Mode DIP Switch Settings
0 0 0
1 1 1
0 1 1
1 1 0
1 0 1
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Detailed DescriptionR
This will cause the Spartan-3 FPGA to attach a weak pull-up to all the User I/O during configuration.
Platform Flash Memory (15)The Platform Flash memory can also be used to program the FPGA. The Platform Flash memory can hold up to four configuration images which are selectable by setting the jumpers on J25 and J31. By default, with out having any jumpers set, the Platform Flash is pointing to the first block of the configuration address space.
The board is wired up so the Platform Flash memory can download bitstreams in Master Serial, Slave Serial, Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes. Using the iMPACT tool to program the Platform Flash memory, the user has the option to select which of the four modes to use for programming the FPGA. The configuration mode DIP switches on the board must be set to match the programming method being used by the Platform Flash memory.
When set correctly, the Platform Flash memory will program the FPGA upon power-up or whenever the Prog button is pressed.
Platform Flash Configuration Select (16)The Platform Flash memory can hold up to four configuration images which are selectable by setting the jumpers on J25 and J31. By default, without having any jumpers set, the Platform Flash is pointing to the first block of the configuration address space.
Platform Flash Enable and Reset Control (17)When using the Platform Flash memory to configure the FPGA, the configuration selector jumper (J38) must be set to the FPGA_DONE (J38 1-2) or GND (J38 2-3). When set to FPGA_DONE, the FPGA Done signal will enable the Platform Flash during configuration and disable it when the Done pin goes high. This will also reset the Platform Flash Address counter. If it is set to GND, then the Platform Flash will be left in an enabled state, pointing to the next address after the current configuration data. This will allow the Platform Flash data space to be used for data storage other than configuration data, where additional memory will be available to be use as data after the FPGA has configured.
Done and INIT LED (18)The INIT LED lights upon power-up to indicate that the FPGA has successfully powered up and completed its internal power-on process.
The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted when the FPGA is successfully configured.
Error LEDs (Active High) (19)There are 2 red LEDs are intended to be used for signaling error conditions such as bus errors, but can be used for any other purpose. They are active high LEDs directly controllable by the FPGA:
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Table 2-9 summarizes the Error LED definitions and connections
ReferenceDesignator
Label/Definition Color FPGA Pin
Error 1
Error 2
.
RS-232 Serial Port 1 (20)The SP-305 board contains two male DB-9 RS-232 serial port to enable the FPGA to communicate with serial data devices. Because the serial port #1 is wired as a host (DCE) device, a null modem cable is normally required to connect the board to the serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip is used to shift the voltage level between FPGA and RS-232 signals.
Label FPGA Pin Description
UART_SOUT AA11 DB9- P3
UART_SIN Y11 DB9- P3
Note: Because the FPGA is only connected to the TX and RX data pins on the serial port, other RS-232 signals, including hardware flow control signals, are not utilized. Flow control should be disabled when communicating with a PC.
RS-232 Serial Port 2 (21)A secondary serial interface is available on the USB chip. By using header J32 and J33 the TX and RX can be selected between the USB debug port on the USB controller chip or the Second FPGA UART port. The USB debug port is selected by moving the jumper on J32 and J33 to the Pin 1,2 setting. The second FPGA UART RX and TX are selected by moving the jumper on J32 and J33 to the Pin 2,3 setting.
Because the serial port is wired as a host (DCE) device, a null modem cable is normally required to connect the board to the serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip is used to shift the voltage level between FPGA and RS-232 signals.
Label FPGA Pin Description
UART1_SOUT AC8 DB9- P1 -- J32 bottom (2,3)
UART1_SIN AB8 DB9- P1-- J33 bottom (2,3)
Note: Because the FPGA is only connected to the TX and RX data pins on the serial port, other RS-232 signals, including hardware flow control signals, are not utilized. Flow control should be disabled when communicating with a PC.
Table 2-9: User and Error LED Connections
DS205 Red AB11
DS206 Red F12
Table 2-10: RS232 FPGA Pin Connections
Table 2-11: RS232 FPGA Pin Connections
SP305 Spartan-3 Development Platform User Guide 15UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
SPI (22)The SP-305 board has a J22 connected to VCC, GND and 4 general purpose FPGA I/O. The intention is to use these as SPI bus signals, but they can be used for any I/O interface.
Label DESCRIPTION FPGA Pin Jumper
SPI_SCLK SPI CLOCK F8 J22-1
SPI_DIN SPI DATA IN E8 J22-2
SPI_DOUT SPI DATA OUT D8 J22-3
SPI_CS SPI CHIPSELECT C9 J22-4
GND GND GND J22-5
VCC 3.3 v 3.3 volts VCC 3.3v J22-6
Character x 2-Line LCD (23)The SP-305 board has a 16-character x 2-line LCD (Lumex LCM-S01602DTR/M) on the board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level translator chip is used to shift the voltage level between the FPGA and the LCD.
Label FPGA Pin Description
LCD_RS W13 REGISTER SELECT
LCD_RW AF12 READ/WRITE
LCD_E AA13 ENABLE
LCD_DB4 AE12 DATA 4
LCD_DB5 AD12 DATA 5
LCD_DB6 AB12 DATA 6
LCD_DB7 AA12 DATA 7
LCD_VEE N/A R1
Caution! Take care not to scratch or damage the surface of the LCD window. Do not remove the protective layer of tape on the top of the screen.
ROTARY ENCODER (24)The SP-305 board has a Rotary Encoder switch. The switch has encoder channel A and B as well as the interface to a momentary contact push button switch as part of the encoder shaft. Typically the FPGA I/O for this device must to be configured with a pull up on rot_enc A, B, as they are grounded at the encoder. The switch also has a Normally Open (NO) push button, where rot_enc_s1 and rot_enc_s2 are floating connections to the FPGA. It is recommended that either a pull up or pull down are configured on these FPGA I/O.
Table 2-12: SPI Pin Connections
Table 2-13: LCD FPFA Pin Connections
Label DESCRIPTION FPGA Pin
ROT_ENC_A Channel A F9
ROT_ENC_B Channel B E9
ROT_ENC_S1 Pole 1 of NO switch C9
ROT_ENC_S2 pole 2 of NO switch B9
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USB Controller with Host and Peripheral Ports (25)A Cypress CY7C67300 embedded USB host controller provides the USB connectivity for the board. The USB controller supports host and peripheral modes of operation. The USB controller has two serial interface engines (SIE) that can be used independently. SIE1 is connected to the USB Host 1 connector (J19) and the USB Peripheral 1 connector (J2). SIE2 is connected only to the USB Peripheral 2 connector.
Note: When using SIE1, the port can only be configured at boot-up to use either the host or peripheral connector, but not both at the same time.
The USB controller has an internal microprocessor to assist in processing USB commands. The firmware for this processor can be stored in its own dedicated IIC EEPROM (U17) or can be downloaded from a host computer via a peripheral connector. The serial port of the USB controller is connected to J32 and J33 through an RS-232 transceiver to assist with debug.
Note: This USB feature on this board has not been tested; therefore, it is not supported.
Table 2-14: ROT ENC Pin Connections
Table 2-15: USB Table
Label DESCRIPTION FPGA Pin
USB_D0 U3 USB Data Bus
USB_D1 U2 USB Data Bus
USB_D2 U1 USB Data Bus
USB_D3 T8 USB Data Bus
USB_D4 T7 USB Data Bus
USB_D5 T6 USB Data Bus
USB_D6 T5 USB Data Bus
USB_D7 T2 USB Data Bus
USB_D8 T1 USB Data Bus
USB_D9 R8 USB Data Bus
USB_D10 R7 USB Data Bus
USB_D11 R6 USB Data Bus
USB_D12 R5 USB Data Bus
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Detailed DescriptionR
10/100 SMSC Ethernet MAC/PHY (26)The SP-305 Development Platform contains a SMSC 91C111 Dual-Speed Fast Ethernet PHY Transceiver at 10/100 Mbps. A 25-MHz crystal supplies the clock signal to the PHY. (See Table 2-16). These settings may be overwritten via software.
Note: The EPROM and External Phy MII interface is not used or connected.
USB_D13 T4 USB Data Bus
USB_D14 R3 USB Data Bus
USB_D15 R2 USB Data Bus
USB_A0 R1 USB Address or Chip Select
USB_A1 P8 USB Address or Chip Select
USB_CS_N Y13 USB Chip Select
USB_WR_N P7 USB Write
USB_RD_N P6 USB Read
USB_RESET G7 USB Reset
USB_INT AE11 USB Int, IORDY, IRQ0
Table 2-15: USB Table (Continued)
Label DESCRIPTION FPGA Pin
Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY
Label FPGA Pin Description
ENET_SD0 U4 Ethernet Data 0
ENET_SD1 U5 Ethernet Data 1
ENET_SD2 U6 Ethernet Data 2
ENET_SD3 V2 Ethernet Data 3
ENET_SD4 V3 Ethernet Data 4
ENET_SD5 V4 Ethernet Data 5
ENET_SD6 V5 Ethernet Data 6
ENET_SD7 U7 Ethernet Data 7
ENET_SD8 V7 Ethernet Data 8
ENET_SD9 W1 Ethernet Data 9
ENET_SD10 W2 Ethernet Data 10
ENET_SD11 W3 Ethernet Data 11
ENET_SD12 W4 Ethernet Data 12
ENET_SD13 W5 Ethernet Data 13
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ENET_SD14 V6 Ethernet Data 14
ENET_SD15 W6 Ethernet Data 15
ENET_SD16 -SD31 Not Connected Ethernet Data 16 -31
ENET_AEN W7 Address Enable
ENET_SA1 Y1 Ethernet Address 1
ENET_SA2 Y2 Ethernet Address 2
ENET_SA3 AA1 Ethernet Address 3
ENET_SA4 AA2 Ethernet Address 4
ENET_SA5 Y4 Ethernet Address 5
ENET_SA6 Y5 Ethernet Address 6
ENET_SA7 AA3 Ethernet Address 7
ENET_SA8 AA4 Ethernet Address 8
ENET_SA9 Y6 Ethernet Address 9
ENET_SA10 Y7 Ethernet Address 10
ENET_SA11 AB1 Ethernet Address 11
ENET_SA12 AB2 Ethernet Address 12
ENET_SA13 AC1 Ethernet Address 13
ENET_SA14 AC2 Ethernet Address 14
ENET_SA15 AB3 Ethernet Address 15
ENET_BE0_N AA7 Byte Enable 0
ENET_BE1_N AF6 Byte Enable 1
ENET_BE2_N Pulled up to 3.3v N/A
ENET_BE3_N Pulled up to 3.3v N/A
ENET_RESET AE4 RESET
ENET_ADS_N Y8
ENET_LCLK_N AB7 CLOCK
ENET_LCLK_N B14 FEEDBACK
ENET_ARDY_N AA8
ENET_SRDY_N AD6
ENET_RDTRTN_N AF4
ENET_IRQ AB4 Interrupt
ENET_LDEV_N AE6
Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY (Continued)
Label FPGA Pin Description
SP305 Spartan-3 Development Platform User Guide 19UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
10/100 Intel Ethernet PHY (27)The SP-305 Development Platform contains an Intel ® LXT971A 3.3V Dual-Speed Fast Ethernet PHY Transceiver at 10/100 Mbps. A 25-MHz crystal supplies the clock signal to the PHY. The PHY is configured to default at power-on or reset.
ENET_RD_N AA6
ENET_WR_N AB14
ENET_DATACS_N Pulled up to 3.3v
ENET_CYCLE_N AC6
ENET_RD_WR AD4
ENET_VLBUS_N A12 VLBUS
XTAL1 N/A 25MHz Crystal inputs
XTAL2 N/A 25MHz Crystal inputs
ENET_X25OUT AC7 25 MHz Clock Output
ENET_TPOP N/A RJ45 connector U1
ENET_TPON N/A RJ45 connector U1
ENET_TPIP N/A RJ45 connector U1
ENET_TPIN N/A RJ45 connector U1
ENET_LNK_N N/C
ENET_LBK N/C
ENET_CNTRL_N N/A RJ45 connector U1
ENET_RBIAS Pulled down to GND
ENET_LEDA_N N/A RJ45 connector U1
ENET_LEDS_N N/A RJ45 connector U1
Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY (Continued)
Label FPGA Pin Description
Table 2-17: 10/100 Intel Ethernet Clock Signals to PHY
Label FPGA Pin Description
PHY_TXD0 N1
PHY_TXD1 N2
PHY_TXD2 N3
PHY_TXD3 N5
PHY_TX_EN N8
PHY_TX_ER N7
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A/D Converter (AD7928) (28)There are eight ADC input signals. For more information see the board schematic and data sheet for the AD7928 ADC device.
ReferenceDesignator
Label/Definition J34 Pin
ADC IN Channel 1
ADC IN Channel 2
ADC IN Channel 3
ADC IN Channel 4
ADC IN Channel 5
ADC IN Channel 6
ADC IN Channel 7
ADC IN Channel 8
Stereo AC97 Audio Codec (29)The SP-305 Development Platform has an AC97 audio codec (U14) to permit audio processing. The National Semiconductor LM4550 Audio Codec supports stereo 16-bit
PHY_RXD0 M1
PHY_RXD1 M2
PHY_RXD2 M6
PHY_RXD3 M5
PHY_RX_DV L6
PHY_RX_ER L5
PHY_MDINT N4
PHY_MDIO N6
PHY_CRS L7
PHY_MDC M3
PHY_SLW0 M8
PHY_SLW1 M7
PHY_RESET L1
PHY_COL L2
Table 2-17: 10/100 Intel Ethernet Clock Signals to PHY
Label FPGA Pin Description
Table 2-18: (Updated) ADC Connections
ADC_VIN1 2-1
ADC_VIN2 2-2
ADC_VIN3 2-3
ADC_VIN4 2-4
ADC_VIN5 2-5
ADC_VIN6 2-6
ADC_VIN7 2-7
ADC_VIN8 2-8
SP305 Spartan-3 Development Platform User Guide 21UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
audio with up to 48-kHz sampling. The sampling rate for record and playback can be different. Table 2-19 lists the FPGA pins.
Label FPGA Pin Description
AUDIO CLOCK
DATA IN
DATA OUT
SYNC
RESET
Note: The reset for the AC97 codec is shared with the reset signal for the flash memory chips and is designed to be asserted at power-on or upon system reset.
Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All jacks are stereo except for Microphone jack. The Headphone jack is driven by the audio codec's internal 50-mW amplifier. Table 2-20 summarizes the audio jacks.
Reference Designator
Function Stereo/Mono
VGA Output (30)A VGA output port (P2) is present on the board to support an external video monitor. The VGA circuitry utilizes a 50-MHz, 24-bit color video DAC (Analog Devices ADV7125KST50). Table 2-21 defines the VGA FPGA pins.
Note: The VGA connector does not support plug and play protocol via ID0/ID1 pins.
Note: The VGA connector does support the IIC port where ID1 is connected to IIC_SDA_VGA. NC3 is connected to IIC_SCL_VGA. Both IIC_SDA_VGA and IIC SCL_VGA are connected respectively to IIC SDA and IIC SCL through a Zero ohm resistors R159 and R160.
Table 2-19: AC97 FPGA Pin Connections
AUDIO_BIT_CLK AE13
AUDIO_SDATA_IN AC13
AUDIO_SDATA_OUT D2
AUDIO_SYNC E3
FLASH_AUDIO_RESET_N AB13
Table 2-20: SP305 Audio Jacks
J11 Microphone - In Mono
J12 Analog Line - In Stereo
J13 Analog Line - Out Stereo
J14 Headphone - Out Stereo
Table 2-21: VGA FPGA Pins
Label FPGA Pin Description
VGA_B0 D11 4.7K to GND
VGA_B1 B11 4.7K to GND
VGA_B2 A11 4.7K to GND
VGA_B3 L8 Blue 3
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Differential Clock Input And Output With SMA Connectors (31)High-precision clock signals can be input to the FPGA using differential clock signals brought in through 50Ω SMA connectors, thereby allowing an external function generator or other clock source to drive the differential clock inputs that directly feed the global clock input pins of the FPGA. The FPGA can be configured to present a 100Ω termination impedance.
VGA_B4 K1 Blue 4
VGA_B5 K2 Blue 5
VGA_B6 K3 Blue 6
VGA_B7 K4 Blue 7
VGA_R0 H11 4.7K to GND
VGA_R1 B10 4.7K to GND
VGA_R2 A10 4.7K to GND
VGA_R3 H3 Red 3
VGA_R4 H4 Red 4
VGA_R5 J6 Red 5
VGA_R6 H5 Red 6
VGA_R7 G1 Red 7
VGA_G0 G11 4.7K to GND
VGA_G1 F11 4.7K to GND
VGA_G2 E11 4.7K to GND
VGA_G3 J5 Green 3
VGA_G4 K7 Green 4
VGA_G5 J7 Green 5
VGA_G6 H1 Green 6
VGA_G7 H2 Green 7
VGA_BLANK_N H12 Blank
VGA_PSAVE_N G12 Psave
VGA_SYNC_N H13 Sync
VGA_VSYNC_N D1 Vsync
VGA_HSYNC_N E4 Hsync
VGA_CLK F6 VGA clock
Table 2-21: VGA FPGA Pins
Label FPGA Pin Description
SP305 Spartan-3 Development Platform User Guide 23UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
A differential clock output from the FPGA is driven out through a second pair of SMA connectors; thereby allowing the FPGA to drive a precision clock to an external device such as a piece of test equipment. Table 2-22 summarizes the differential SMA clock pin connections.
Label Clock Name FPGA Pin
SMA_DIFF_CLK_IN_N
SMA_DIFF_CLK_IN_P
SMA_DIFF_CLK_OUT_N
SMA_DIFF_CLK_OUT_P
Expansion Headers (32)The board contains expansion headers for easy expansion or adaptation of the board for other applications. The expansion connectors use standard 0.1" headers. The expansion connectors contain connections to single-ended and differential FPGA I/Os, ground, 2.5V/3.3V/5V power, JTAG chain, and the IIC bus.
Differential Expansion I/O Connectors
Header J5 contains 16 pairs of differential signal connections to the FPGA I/Os. This permits the signals on this connector to carry high-speed differential signals such as LVDS data. All differential signals are routed with 100Ω differential trace impedance. Matched length traces are used across all differential signals. Because the differential signals connect to the FPGA I/O, they may also be used as independent single-ended nets. The VCCIO of these signals can be set to 2.5V or 3.3V by setting jumper J16. Table 2-23 summarizes the differential connections on this expansion I/O connector.
Table 2-22: Differential SMA Clock Connections
J10 B13
J7 A13
J8 E1
J9 E2
Table 2-23: Expansion I/O Differential Connections (J5)
Header Pin(Diff Pair
Neg)
Label (Diff Pair
Neg)
FPGA Pin(Diff Pair
Neg)
Header Pin(Diff Pair
Pos)
FPGA Pin(Diff Pair
Pos)
Label(Diff Pair
Pos)
J5, Pin 2 HDR2_2 U20 J5, Pin 4 V20 HDR2_4
J5, Pin 6 HDR2_6 V21 J5, Pin 8 W22 HDR2_8
J5, Pin 10 HDR2_10 W26 J5, Pin 12 W25 HDR2_12
J5, Pin 14 HDR2_14 T20 J5, Pin 16 T19 HDR2_16
J5, Pin 18 HDR2_18 P22 J5, Pin 20 P21 HDR2_20
J5, Pin 22 HDR2_22 AC26 J5, Pin 24 AC25 HDR2_24
J5, Pin 26 HDR2_26 Y21 J5, Pin 28 Y20 HDR2_28
J5, Pin 30 HDR2_30 AB26 J5, Pin 32 AB25 HDR2_32
J5, Pin 34 HDR2_34 W21 J5, Pin 36 W20 HDR2_36
J5, Pin 38 HDR2_38 AA22 J5, Pin 40 AA21 HDR2_40
J5, Pin 42 HDR2_42 AB24 J5, Pin 44 AB23 HDR2_44
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Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os; thereby permitting the signals on this connector to carry high-speed single-ended data. All single-ended signals on connector J6 are matched length traces. The VCCIO of these signals can be set to 2.5V or 3.3V by setting jumper J29. Table 2-24 summarizes the single-ended connections on this expansion I/O connector.
J5, Pin 46 HDR2_46 AA24 J5, Pin 48 AA23 HDR2_48
J5, Pin 50 HDR2_50 W24 J5, Pin 52 W23 HDR2_52
J5, Pin 54 HDR2_54 Y23 J5, Pin 56 Y22 HDR2_56
J5, Pin 58 HDR2_58 Y26 J5, Pin 60 Y25 HDR2_60
J5, Pin 62 HDR2_62 AA26 J5, Pin 64 AA25 HDR2_64
Table 2-23: Expansion I/O Differential Connections (J5) (Continued)
Header Pin(Diff Pair
Neg)
Label (Diff Pair
Neg)
FPGA Pin(Diff Pair
Neg)
Header Pin(Diff Pair
Pos)
FPGA Pin(Diff Pair
Pos)
Label(Diff Pair
Pos)
Table 2-24: Expansion I/O Single-Ended Connections (J6)
Header Pin Label FPGA Pin
J6, Pin 2 HDR1_2 R21
J6, Pin 4 HDR1_4 T22
J6, Pin 6 HDR1_6 T23
J6, Pin 8 HDR1_8 V2S
J6, Pin 10 HDR1_10 U23
J6, Pin 12 HDR1_12 R19
J6, Pin 14 HDR1_14 R22
J6, Pin 16 HDR1_16 P25
J6, Pin 18 HDR1_18 U24
J6, Pin 20 HDR1_20 T26
J6, Pin 22 HDR1_22 T25
J6, Pin 24 HDR1_24 R26
J6, Pin 26 HDR1_26 P26
J6, Pin 28 HDR1_28 V24
J6, Pin 30 HDR1_30 R25
J6, Pin 32 HDR1_32 V23
J6, Pin 34 HDR1_34 R20
J6, Pin 36 HDR1_36 V22
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Detailed DescriptionR
Other Expansion I/O Connectors
In addition to the high speed I/O paths, additional I/O signals and power connections are available to support expansion cards plugged into SP305 board. The 14 I/O pins from the general purpose FPGA I/O are connected to expansion connector J3. This arrangement permits additional I/O’s to be connected to the expansion connector.
The expansion connector also allows the board's JTAG chain to be extended onto the expansion card by setting jumper J26 accordingly.
The IIC bus on the board is also extended onto the expansion connector to allow additional IIC devices to be bused together. If the expansion IIC bus is to be utilized, the user must have the IIC pull-up resistors present on the expansion card. Bi-directional level shifting transistors allow the expansion card to utilize 2.5V to 5V signaling on the IIC bus.
Power supply connections to the expansion connectors provide ground, 2.5V, 3.3V, and 5V power pins. If the expansion card draws significant power from the SP-305 board, the user must ensure that the total power draw can be supplied by the board.
The SP-305 expansion connector is backward compatible with the expansion connectors on the ML320, ML321, and ML323 boards, thereby allowing their daughter cards to be used with the SP-305 Development Platform. Table 2-25 summarizes the additional expansion I/O connections.
J6, Pin 38 HDR1_38 R24
J6, Pin 40 HDR1_40 P20
J6, Pin 42 HDR1_42 P23
J6, Pin 44 HDR1_44 U22
J6, Pin 46 HDR1_46 U21
J6, Pin 48 HDR1_48 U26
J6, Pin 50 HDR1_50 P19
J6, Pin 52 HDR1_52 P24
J6, Pin 54 HDR1_54 U25
J6, Pin 56 HDR1_56 T21
J6, Pin 58 HDR1_58 N23
J6, Pin 60 HDR1_60 N24
J6, Pin 62 HDR1_62 N25
J6, Pin 64 HDR1_64 N26
Table 2-24: Expansion I/O Single-Ended Connections (J6) (Continued)
Header Pin Label FPGA Pin
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Table 2-25: Additional Expansion I/O Connections
Header Pin Label FPGA Pin Description
J3, Pin 1 VCC5 N/A 5V Power Supply
J3, Pin 2 VCC5 N/A 5V Power Supply
J3, Pin 3 VCC5 N/A 5V Power Supply
J3, Pin 4 VCC5 N/A 5V Power Supply
J3, Pin 5 HR3_5 B3 FPGA I/O
J3, Pin 6 VCC3V3 N/A 3.3V Power Supply
J3, Pin 7 VCC3V3 N/A 3.3V Power Supply
J3, Pin 8 VCC3V3 N/A 3.3V Power Supply
J3, Pin 9 VCC3V3 N/A 3.3V Power Supply
J3, Pin 10 HR3_10 A7 FPGA I/O
J3, Pin 11 FPGA_PROM_TMS N/A Expansion TMS
J3, Pin 12 FPGA_PROM_TCK N/A Expansion TCK
J3, Pin 13 EXPANSION_TDO N/A Expansion TDO
J3, Pin 14 FPGA_TDO N/A Expansion TDI
J3, Pin 15 HR3_15 G8 FPGA I/O
J3, Pin 16 HR3_16 B8 FPGA I/O
J3, Pin 17 HR3_17 A8 FPGA I/O
J3, Pin 18 HR3_18 G9 FPGA I/O
J3, Pin 19 HR3_19 D9 FPGA I/O
J3, Pin 20 HR3_20 G10 FPGA I/O
J3, Pin 21 HR3_21 F10 FPGA I/O
J3, Pin 22 HR3_22 E10 FPGA I/O
J3, Pin 23 HR3_23 D10 FPGA I/O
J3, Pin 24 HR3_24 C10 FPGA I/O
J3, Pin 25 HR3_25 E13 FPGA I/O
J3, Pin 26 HR3_26 D13 FPGA I/O
J3, Pin 27 HR3_27 C13 FPGA I/O
J3, Pin 28 HR3_28 A21 FPGA I/O
J3, Pin 29 HR3_29 A22 FPGA I/O
J3, Pin 30 HR3_30 B23 FPGA I/O
SP305 Spartan-3 Development Platform User Guide 27UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
PS/2 Mouse and Keyboard Ports (33)The SP-305 Development Platform contains two PS/2 ports: one for a mouse (J17) and the other for a keyboard (J18). Bi-directional level shifting transistors allow the FPGA's 2.5V I/O to interface with the 5V I/O of the PS/2 ports. The PS/2 ports on the board are powered directly by the main 5V power jack which also powers the rest of the board.
Caution! Care must be taken to ensure that the power load of any attached PS/2 devices does not overload the AC adapter.
ChipScope (34)ChipScope debug port.
CAN Controller (MCP2515 and MPC2551) (35)The SP305 board has the option to drive the CAN Phy (MPC2551) directly from FPGA I/O pins, or communicate to a CAM MAC device (MPC2515).
CAN MAC (MCP2515) (35a)
When using both the CAN MAC and PHY devices, the communication channel to the MCP2515 is through an SPI port. See section 35B to set the jumpers in the right position to select either the CAN MAC/PHY or just the CAN PHY.
Note: When using the CAN controller, There is an option to use the CAN “MAC” device or have the CAN “MAC” implemented in the FPGA. To have the FOPGA drive the CAN PHY RX and TX signals that connect to the MPC2551 CAN PHY device, set the jumper on J35 and J36. When the jumpers are set on Pins 1,2 the CAn PHY is connected to the CAN MPC2515 “MAC” and when connected to the pins 2,3 it is connected the FPGA I/O for the CAN RX and TX.
J3, Pin 31 IIC_SCL D14 Expansion IIC SCL
J3, Pin 32 IIC_SDA E14 Expansion IIC SDA
Table 2-25: Additional Expansion I/O Connections (Continued)
Header Pin Label FPGA Pin Description
Table 2-26: PS2 Mouse & Keyboard
Label FPGA Pin Description
KEYBOARD_CLK L4 KEYBOARD CLOCK
KEYBOARD_DATA K5 KEYBOARD DATA
MOUSE_CLK A14 MOUSE CLOCK
MOUSE_DATA F14 MOUSE DATA
Table 2-27: MPC 2551 MAC Connections
ReferenceDesignator
Label/Definition FPGA Pin
FPGA_CAN_RXCAN D7
FPGA_CAN_TXCAN E7
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Selecting an FPGA CAN MAC or the CAN MPC2551 MAC device (35b)
The Jumper J35 will select between the FPGA_CAN_TXCAN and the CAN_TXCAN_MAC. Jumper J36 will select between the FPGA_CAN_RXCAN and the CAN_RXCAN_MAC
ReferenceDesignator
Jumper Pin
CAN 16 Mhz Oscillator Socket (35c)
The SP305 has a Oscillator socket for a 16Mhz Oscillator.
CAN_CLK B7
CAN_SOF E6
CAN_TX0RTS D6
CAN_TX1RTS C6
CAN_TX2RTS B6
CAN_CS A3
CAN_SO C4
CAN_SI B4
CAN_SCK A4
CAN_INT C4
CAN_RESET A6
CAN_RX0BF B5
CAN_RX1BF A5
Table 2-27: MPC 2551 MAC Connections
ReferenceDesignator
Label/Definition FPGA Pin
Table 2-28: FPGA and CAN Jumper Pins
CAN_TXCAN_MAC J35-1,2 (JUMPER)
CAN_RXCAN_MAC J36-1,2 (JUMPER)
FPGA_CAN_TXCAN J35-2,3 (JUMPER)
FPGA_CAN_RXCAN J36-2,3 (JUMPER)
SP305 Spartan-3 Development Platform User Guide 29UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
Selecting an FPGA CAN Clock or the 16 MHz Oscillator (35d)
The Jumper J27, on the back of the SP305 board, will select between the FPGA_CAN_CLK and the 16 MHz Oscillator.
ReferenceDesignator
FPGA Pin
Selecting the Vref and Termination for the CAN PHY (35e)
The Jumper J23 will add the CAN bus termination Resistor. The Jumper J16 will let the user connect the CAN Vref pin to GND.
ReferenceDesignator
Label/Definition FPGA Pin
CAN Termination
CAN Bus Header (35f)
The Header J15 is the CAN Bus pins. CANH is on Pin 1 and CANL is on Pin 2.
ReferenceDesignator
Label/Definition FPGA Pin
DDR SDRAM (36)The board contains 64MB of DDR SDRAM using two Infineon HYB25D256160BT-7 (or compatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit data bus capable of running up to 266 MHz. All DDR SDRAM signals are terminated through 47Ω resistors to a 1.25V VTT reference voltage. The board is designed for matched length traces across all DDR control and data signals except clocks and the DDR Loop trace. See the “DDR Clock Signal” and the “DDR Loop Signal” sections.
The board can support up to 256MB of total DDR SDRAM memory if larger chips are installed. An extra address pin is present on the board to support up to 1-Gb DDR chips.
DDR Clock Signal
The DDR clock signal is broadcast from the FPGA as a single differential pair that drives both DDR chips. The delay on the clock trace is designed to match the delay of the other DDR control and data signals. The DDR clock is also fed back to the FPGA to allow for clock de-skew using Spartan-3 DCMs. The board is designed so that the DDR clock signal reaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips.
CAN_CLK J27-1,2 (JUMPER)
16 MHz CLK J27-2,3 (JUMPER)
R75 J23-1 (JUMPER TO GND)
VREF J16-1 (JUMPER TO GND)
CANH
CANL
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DDR Loop Signal
The DDR loop signal is a trace driven and then received back at the FPGA with a delay equal to the sum of the trace delays of the clock and DQS signals. This looped trace can be used in high-speed memory controllers to help compensate for the physical trace delays between the FPGA and DDR chips.
ZBT Synchronous SRAM (37)The ZBT synchronous SRAM (Cypress CY7C1354B) provides high-speed, low-latency external memory to the FPGA. The memory is organized as 256K x 36 bits, thereby providing for a 32-bit data bus with support for four parity bits.
Note: The SRAM and FLASH memory share the same data bus.
Table 2-29: SRAM
Label FPGA Pin Description
SRAM_FLASH_D0 AD25
SRAM_FLASH_D1 AB22
SRAM_FLASH_D2 AC22
SRAM_FLASH_D3 AE24
SRAM_FLASH_D4 AF24
SRAM_FLASH_D5 AD23
SRAM_FLASH_D6 AE23
SRAM_FLASH_D7 AF23
SRAM_FLASH_D8 AD22
SRAM_FLASH_D9 AE22
SRAM_FLASH_D10 AF22
SRAM_FLASH_D11 AB21
SRAM_FLASH_D12 AC21
SRAM_FLASH_D13 AD21
SRAM_FLASH_D14 AE21
SRAM_FLASH_D15 AF21
SRAM_FLASH_D16 AB20
SRAM_FLASH_D17 AC20
SRAM_FLASH_D18 AE20
SRAM_FLASH_D19 AF20
SRAM_FLASH_D20 AA20
SRAM_FLASH_D21 Y19
SRAM_FLASH_D22 AA19
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Detailed DescriptionR
SRAM_FLASH_D23 AB19
SRAM_FLASH_D24 AC19
SRAM_FLASH_D25 AD19
SRAM_FLASH_D26 AE19
SRAM_FLASH_D27 AF19
SRAM_FLASH_D28 Y18
SRAM_FLASH_D29 AA18
SRAM_FLASH_D30 AB18
SRAM_FLASH_D31 AC18
SRAM_FLASH_A0 AE15
SRAM_FLASH_A1 AF15
SRAM_FLASH_A2 AB16
SRAM_FLASH_A3 AC16
SRAM_FLASH_A4 AE17
SRAM_FLASH_A5 AA17
SRAM_FLASH_A6 AD17
SRAM_FLASH_A7 AD18
SRAM_FLASH_A8 AE18
SRAM_FLASH_A9 Y17
SRAM_FLASH_A10 AC17
SRAM_FLASH_A11 Y12
SRAM_FLASH_A12 AA14
SRAM_FLASH_A13 Y14
SRAM_FLASH_A14 AB15
SRAM_FLASH_A15 AD15
SRAM_FLASH_A16 AF17
SRAM_FLASH_A17 Y16
SRAM_FLASH_A18 AA16
SRAM_FLASH_A19 AB17
SRAM_FLASH_A20 W16
SRAM_FLASH_A21 AC10
SRAM_FLASH_A22 AB10
Table 2-29: SRAM (Continued)
Label FPGA Pin Description
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Linear Flash Memory Chips (38)Two 32Mb linear flash memory chips (Micron MT28F320J3RG-11 ET) are installed on the board for a total of 8MB of flash memory. These flash memory chips are Intel StrataFlash compatible. This memory provides non-volatile storage of data or Embedded Processor software. Each flash chip is 16 bits wide and together forms a 32-bit data bus that is shared with SRAM.
The reset for the AC97 Codec is shared with the reset signal for the flash memory chips and is designed to be asserted at power-on or upon system reset.
Note: The SRAM and FLASH memory share the same data bus.
SRAM_BW0 AF16
SRAM_BW1 AE16
SRAM_BW2 AA15
SRAM_BW3 W15
SRAM_AVD_LD_N W12
SRAM_CE1_N AC11
SRAM_FLASH_WE_N W11
SRAM_OE_N AF10
SRAM_ZZ AE10
SRAM_MODE AD10
SRAM_DQP0 AF5
SRAM_DQP1 AE5
SRAM_DQP2 AD5
SRAM_DQP3 AB6
SRAM_CLK AF13
SRAM_CLK AF14 FEEDBACK
Table 2-29: SRAM (Continued)
Label FPGA Pin Description
Table 2-30: Flash
Label FPGA Pin Description
SRAM_FLASH_D0 AD25
SRAM_FLASH_D1 AB22
SRAM_FLASH_D2 AC22
SRAM_FLASH_D3 AE24
SRAM_FLASH_D4 AF24
SP305 Spartan-3 Development Platform User Guide 33UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
SRAM_FLASH_D5 AD23
SRAM_FLASH_D6 AE23
SRAM_FLASH_D7 AF23
SRAM_FLASH_D8 AD22
SRAM_FLASH_D9 AE22
SRAM_FLASH_D10 AF22
SRAM_FLASH_D11 AB21
SRAM_FLASH_D12 AC21
SRAM_FLASH_D13 AD21
SRAM_FLASH_D14 AE21
SRAM_FLASH_D15 AF21
SRAM_FLASH_D16 AB20
SRAM_FLASH_D17 AC20
SRAM_FLASH_D18 AE20
SRAM_FLASH_D19 AF20
SRAM_FLASH_D20 AA20
SRAM_FLASH_D21 Y19
SRAM_FLASH_D22 AA19
SRAM_FLASH_D23 AB19
SRAM_FLASH_D24 AC19
SRAM_FLASH_D25 AD19
SRAM_FLASH_D26 AE19
SRAM_FLASH_D27 AF19
SRAM_FLASH_D28 Y18
SRAM_FLASH_D29 AA18
SRAM_FLASH_D30 AB18
SRAM_FLASH_D31 AC18
FLASH_A0 AA10 Connected to Flash A0
SRAM_FLASH_A0 AE15 Connected to Flash A1
SRAM_FLASH_A1 AF15
SRAM_FLASH_A2 AB16
SRAM_FLASH_A3 AC16
Table 2-30: Flash
Label FPGA Pin Description
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SRAM_FLASH_A4 AE17
SRAM_FLASH_A5 AA17
SRAM_FLASH_A6 AD17
SRAM_FLASH_A7 AD18
SRAM_FLASH_A8 AE18
SRAM_FLASH_A9 Y17
SRAM_FLASH_A10 AC17
SRAM_FLASH_A11 Y12
SRAM_FLASH_A12 AA14
SRAM_FLASH_A13 Y14
SRAM_FLASH_A14 AB15
SRAM_FLASH_A15 AD15
SRAM_FLASH_A16 AF17
SRAM_FLASH_A17 Y16
SRAM_FLASH_A18 AA16
SRAM_FLASH_A19 AB17
SRAM_FLASH_A20 W16
SRAM_FLASH_A21 AC10
SRAM_FLASH_A22 AB10 Connected to Flash A23
FLASH_A23 Y10 Connected to Flash A24
FLASH_CE2 AF11
SRAM_FLASH_WE_N W11
FLASH_OE_N J2
FLASH_BYTE_N AD8
FLASH_AUDIO_RESET_N AB13
Table 2-30: Flash
Label FPGA Pin Description
SP305 Spartan-3 Development Platform User Guide 35UG216 (v1.1) March 3, 2006 www.xilinx.com
Detailed DescriptionR
Expansion JTAG Jumper (39)The J26 Jumper connects the Expansion header to the JTAG chain.
Label DESCRIPTION Jumper Pin
FPGA_TDO to TDO No Expansion Header in JTAG Chain
J26 1,2
EPANSION_TDO to TDO Expansion Header in JTAG Chain
J26 2,3
Bank 3 Voltage selection (40)The J29 Jumper connects 3.3 0r 2.5 volts to the FPGA I/O Bank 3. The I/O it controls are the Expansion Header 3 and 6.
Label DESCRIPTION Jumper Pin
2.5 Volts 2.5 Volts on Bank 3 J29 1,2
3.3Volts 3.3 Volts on Bank 3 J29 2,3
IIC Bus with 4Kb EEPROM (41)An IIC EEPROM (Microchip Technology 24LC04B-I/ST) is provided on the SP-305 board to store non-volatile data such as an Ethernet MAC address. The EEPROM write protect is tied off on the board to disable its hardware write protect. The IIC bus utilizes 2.5V signaling and can operate at up to 400 kHz. IIC bus pull-up resistors are provided on the board.
The IIC bus is extended to the expansion connector so that the user may add additional IIC devices and share the IIC controller in the FPGA. If the expansion IIC bus is to be utilized, the user must have additional IIC pull-up resistors present on the expansion card. Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5V signaling on IIC.
Label FPGA Pin Description
IIC_SCL D14 IIC clock
IIC_SDA E14 IIC Data
Table 2-31: Expansion JTAG Jumper Connections
Table 2-32: Bank 3 I/O Voltage Selection
Table 2-33: IIC FPGA Pins
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IFF (42)The SP-305 board has an IFF Encryption device connected to an FPGA I/O pin. This IFF device can be interfaced to an FPGA design in such a way that the functionality of the design can be licensed or enabled by the authentication with the IFF device.
Label Description FPGA Pin
IFF_FPGA One Wire Interface F7
Table 2-34: SPI Pin Connections
Item Jumper Description
35b J36 2,3 Selects between the FPGA and CAN MAC device for TXCAN
35b J35 2,3 Selects between the FPGA and the CAN MAC device for RXCAN
35d J27 2,3 Selects FPGA as CAN Clock
35e J23 Connects Can Termination Resistor
35e J16 Connects Can Vref to GND
16 J25 Platform Flash Select 0
16 J31 Platform Flash Select 1
17 J38 2,3 Platform Flash Enable and Reset Control
39 J26 1,2 Selects JTAG Connection Chain to Expansion Header (default no header in JTAG Chain)
25 J28 Connects Auxiliary Power to USB Port
21 J32 2,3 Selects between the USB Debug UART port and the UART1 SOUT
21 J33 2,3 Selects between the USB Debug UART port and the UART1 SIN
SP305 Spartan-3 Development Platform User Guide 37UG216 (v1.1) March 3, 2006 www.xilinx.com
Default Jumper SettingsR
Default Jumper Settings
Table 2-35: Default Jumper Settings