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High Performance Clocking with the Xilinx® 7 Series

Copyright © 2011. Avnet, Inc. All rights reserved. Follow @avnetxfest | Tweet this event: #avtxfest

3Course Objectives

Survey aspects of robust, system-level clock design

Understand criteria for choosing proper external clock generators and view recommended solutions

Examine the 7 series clock management features that address demanding clock requirements

Explore real-world example designs


4Agenda

System-Level Clocking Challenges

Xilinx 7 series FPGA Clocking Resources

Case Studies

– Wireless Software Define Radio

– DDR3

– Motor Control

Closing Comments


5Agenda



Case Studies


– DDR3

– Motor Control

Closing Comments


6Clocking the FPGA

Virtex™-7 2000T– 2 million logic cells– 6.8 billion transistors capable of > 3.8GHz switching– DSP48E1 slices clocked with 741MHz global clock– 12.5Gb/s serial transceivers– 1066MHz Fmax analog PLLs

Zynq-7000 EPP– ARM® dual-core Cortex™-A9 MPCore™– DDR3 interface at 1066Mbps– Gigabit Ethernet, USB2.0, SDIO, CAN

6


7Clocking the Interfaces

PCI Express Gen3– 8Gb/s– System jitter budget allows 1ps (Rj)*

HD-SDI Video– 1.485 Gb/s with 673 ps period– 100’s of picoseconds jitter is intolerable

Wireless Software Defined Radio– IF sample DAC @ 1.25Gsps– Requires 100fs clock to achieve 16-bits performance– Network synchronization

7

* PCI Express® 3.0 PHY Electrical Layer Requirements, 2008, Dan Froelich, Intel Corp. 2008


8Clocking the System

Industrial Control Systems– Precision Timing Protocol (IEEE1588)– Sub-microsecond network clock synchronization

Wireless Backhaul– Redundancy often required– Holdover mechanism to maintain output clock when

reference is lost– System synchronization

Broadcast Video– Synchronization to “house” clock– Genlocking

8


9Clocking is Crucial – Choose Wisely!

Clocks inside the FPGA must have…– Sophisticated clock management– Multifaceted frequency & phase control– Intuitive methods to implement your design

System clocks outside of the FPGA must have…– Flexible, multi-output “all-in-one” options for low cost

applications– Precision clock generation & distribution in high

performance applications– Multiple outputs with programmable frequency– Features for network interface & synchronization

9


10Agenda



Case Studies


– DDR3

– PCI Express

– Motor Control

Closing Comments


117 Series Clocking Overview

Based on established Virtex-6 FPGA clocking structure– Same Scalable Optimized Architecture in all 7 series

Low-skew clock distribution– Multiple paths for driving clocks to and from locations

Multiple clock buffers– High fanout buffers connect clocks routing resources

Clock regions– Device divided into clock regions with dedicated resources

Clock Management Tile (CMT)– One Mixed-Mode Clock Manager (MMCM) and one PLL

per CMT– Up to 24 CMTs per device

Global clock routing is approximately 50% lower power than previous generations


127 Series FPGA Layout

Similar Floorplan to Virtex-6 FPGAs– Easy migration to 7 series FPGAs

CMT columns moved from center of device to adjacent to I/O columns– No more inner vs. outer column

performance difference– Higher performance interfaces

Only one I/O column per half device– Uniform skew from center of device

Gigabit Serial Transceiver (GT) columns replace I/O and CMT in smaller devices

I/O Columns

CMT Columns

Clock Routing

CLB, BRAM, DSP Columns

GT Columns


137 Series Clock Region

Uniform height clock regions

Each region has its own resources

All regions can share the available global resources

Clock region is 50 CLB rows tall 25 rows above and 25 rows below the

central horizontal clocking row (HROW) All clock regions span from global vertical

clock column to the left or right edge of the device

Clock regions have their own dedicated resources


14BUFG (Global Clock Buffer)For Driving the Global Clock Spine

Global buffer for distributing clock signals across the height of the device

32 BUFG per device located in the centerof the vertical clock spine

16 BUFG driven by resources in north, 16 driven by south

Same primitive as previous generations

Glitch-less switching between clock sources

Clock Enable for clock gating

14

BUFG(CTRL)

O

S1

S0

IGNORE0

IGNORE1

CE0

CE1

I1

I0

Global buffers drive the height of the device


15BUFH (Horizontal Clock Buffer)

For Driving Horizontal Clock Spine Entry point for clock signals on vertical

spine to access clock regions

12 BUFH per clock region

Similar to Virtex-6 FPGA BUFH

Clock enable provides the ability to turn off clocks within a clock region

Can be used within region without the need to access BUFG or global spine

Additional capability of asynchronous CE

BUFH(CE)

I

CE

O

Regional clock gating for fine control of power


16BUFR (Regional Clock Buffer)

For Driving Logic Within Clock Regions

Regional buffer with divide capability

4 BUFR per clock region

Similar to Virtex-6 BUFR

Removal of multi-region capability

Use in conjunction with BUFIO for capturing serial data in the parallel domain

BUFR

÷

CLR

I O

CE

Regional buffers with flexible divide capability


17BUFIO (IO Clock Buffer)

Dedicated clock buffer within the I/O columns

4 BUFIO per clock region

Same as Virtex-6 BUFIO

Intended for clocking high speed I/O logic and can only drive I/O logic, not fabric logic

BUFIO

I O

BUFIO routes signals within I/O columns


18

TBD TI / 4 DSP / Pierrick

Texas Instruments Zynq SDR Kit Clocking

FMC30RF

FPGA

BUFG BUFR IBUFDS


19BUFMR (Multi-Region Clock Buffer)

New to 7 Series FPGA architecture

Located in the CMT columns

Method by which clock signals are driven into multiple regions via I/O clocking backbone

– I/O clocking backbone is a set of clock routes running the height of the device located in the CMT columns

BUFMR drives BUFIO and BUFR in region above and region below

Synchronous or asynchronous clock enable capability

I O

CE

BUFMR(CE)

Efficient clocking across multiple regions


20Clock Resource Performance

Artix-7 Kintex-7 Virtex-7BUFG 600/540/450 741/710/625 741/710/625BUFH 600/540/450 741/710/625 741/710/625BUFR 420/375/315 600/540/450 600/540/450

BUFIO 680/680/600 800/800/710 800/800/710MMCM Fout_max 800/800/800 1066/933/800 1066/933/800

PLL Fout_max 800/800/800 1066/933/800 1066/933/800


21MMCM and PLL Functions

MMCM• Functionally similar to Virtex-6 MMCM• Seven output counters plus feedback• Powerdown mode• Input Clock Switching• Fractional Divide on OUT0 and FBOUT• Dynamic Phase Shift• True and Complement outputs (O0-O3)• Spread Spectrum Clock Generation

PLL• Subset of MMCM functions• Six output counters plus feedback• Powerdown mode• Input Clock Switching• Phaser In/Out blocks for high-speed DDR memory interface • Required by MIG


227 Series Clock Architecture Detail


23Xilinx Clocking Wizard

Enter input & output clock parameters

Estimates PLL output jitter (pk-to-pk)

Automatically creates custom IP block for integration in ISE Design Suite

23


24Intelligent Clock Gating – Power Reduction

Fine-grain Clock Gating eliminates unnecessary clock activity while maintaining functionality and performance– Power = α x fclk x CL x V2– Clock and Logic Gating reduces switching activity α

Average of 11% dynamic power reduction– Synthesis independent logic reorganization


25Agenda



Case Studies


– DDR3

– Motor Control

Closing Comments


26Software Define Radio Clock Requirements

VGA VGA

Clock Generator /

Sync

Clock Distribution

Freq. Synthesizer

AD9548 AD9523-1ADF4351

FMC

Connector

Slave Clock InSync In

DAC

1000MbpsModulator400 – 6000MHz

GAIN

ADC

250MSPS Demodulator400 – 6000MHz

Output: 1 – 1000MHzInput: 1 Hz - 750MHz

Output: 35 - 4400MHz

Freq. Synthesizer

500MHz DDR

125MHz DDR

1 LVDSPair

50MHz Ref Clock

SPI SPI SPI

SPI

2

2 Reference inputs down to 1Hz Network synchronization Multiple outputs at different frequencies LO frequency synthesis 400MHz to +4GHz High quality ADC/DAC clocks up to 1GHz

AD-FMCCOMMS1-EBZ16

14 How much jitter is acceptable?


27

30405060708090

100110120130

1 10 100 1000

SN

RIN

dB

16 BITS

14 BITS

12 BITS

0.125 ps0.25 ps

2 ps

0.5 ps1 ps

RMS JITTER

SNR = 20log 101

2 f t jSNR = 20log 101

2 f t j

10 BITS

EN

OB

TOTAL JITTER = t j (RMS)

FULL-SCALE ANALOG INPUT FREQUENCY IN MHz

Analog Devices

ADCAnalog Devices

ADCAnalog InputAnalog Input

Sampling ClockSampling Clock

SNRSNR

Digital OutputDigital Output

Analog Devices

ADCAnalog Input

Sampling Clock

SNR

Digital Output

Effects of Jitter in a Sampling System

High performance sampling requires very low jitter clocking!

f = 20MHztj = 2ps SNR ~ 75dB


28AD9523-1 14 Output Dual Loop Clock Generator

1st stage PLL cleans jitter 2nd stage PLL performs

upconversion <150 fs rms jitter at

122.88MHz HSTL/LVPECL/LVDS/

CMOS 2 selectable inputs Auto switchover Auto Holdover Serial port programming EEPROM Zero Delay

AD9523-1

Applications: Clocking high speed ADCs, DACs LTE and multicarrier GSM base stations Wireless and broadband infrastructure SONET, 10Ge, 10G FC


29AD9548 Network Clock Generator/Synchronizer

Input reference frequencies from 1 Hz to 750 MHz Output frequencies up to 450 MHz 30-bit integer / 10-bit fractional programmable feedback divider Stratum 2 stability in holdover mode Supports hitless reference switchover 4 input / 4 output pairs, configured as single-end or differential

AD9548


30ADF4351 Wideband Synthesizer with Integrated VCO

Output frequency range: 35 MHz to 4400 MHz

Fractional-N synthesizer and integer-N synthesizer

Integrated Low phase noise VCO

Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output

Typical rms jitter: 0.3 psrms

3-wire serial interface

ADF4351


31High Performance SDR with Wide Flexibility

VGA VGA

Clock Generator /

Sync

Clock Distribution

Freq. Synthesizer

AD9548 AD9523-1ADF4351

FMC

Connector

Slave Clock InSync In

DAC

1000MbpsModulator400 – 6000MHz

GAIN

ADC

250MSPS Demodulator400 – 6000MHz

Output: 1 – 1000MHzInput: 1 Hz - 750MHz

Output: 35 - 4400MHz

Freq. Synthesizer

500MHz DDR

125MHz DDR

1 LVDSPair

50MHz Ref Clock

SPI SPI SPI

SPI

2

2

AD-FMCCOMMS1-EBZ16

14

See this SDR demonstration at the exhibit area!


32Can We Use FPGA PLLs to Clock Data Converters?

Xilinx 7 series FPGA PLLs– Max input frequency = 1066MHz– Min input frequency = 10MHz*– Have jitter cleaning capability– Dynamic phase shifting– Fractional frequency output dividers– Multiple per device

Possibility to reduce system BOM by using PLL integrated into the FPGA

Let’s analyze a real application…*MMCM only. PLL FINMIN = 19MHz


33TI FMC30RF SDR Module

RF Switch

DAC

DAC

CDCE62005

ADC2 lvds

2 lvds

2 lvds90

0

TRF3765400 MHz - 4.8GHz

ADC2 lvds

0 /90

Clock Generation

PLL VCO

PLL VCO

FMC

Connector

Dual 12-bit ADC @ 125Msps Dual 12-bit DAC @ 250Msps Suppose we used an FPGA PLL to clock them …

Up to 30MHz IF bandwidth


34Xilinx Clocking Wizard Quickly Creates Custom IP Blocks

(0.01UI) * (1/200MHz) = 50ps (Pk-to-Pk)

Lower jitter with faster PLL frequency


35Converting Peak-to-Peak to RMS Jitter

Pk-to-pk jitter (Jp-p) = clock uncertainty in timing budgets RMS jitter (JRMS) = SNR degradation in data converters Convert Jp-p JRMS at a specified bit-error-rate (BER)

Ex: BER target = 10-10

Jpp = 94psFrom erfc table find α = 12.723 JRMS = Jp-p / α

= 7 ps

PDF of Gaussian distribution with variance of 1

Normalized Standard Deviation

2*22

1BER erfc

Jpk-pkBER

/Jrms Jpp


36TI ADC/DAC Clocking Solutions

36

FPGA PLL 7ps RMS jitter too high for this application!


37CDCE62005 Dual VCO Jitter Cleaner / Clock Generator

Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter

Fully Configurable Outputs Including Frequency, Output Format, and Skew

Smart Input Multiplexer Automatically Switches Between One of Three References

Integrated EEPROM Determines Device Configuration at Power-up

0.35 ps RMS (10 kHz to 20 MHz) Output Jitter

Low Output Phase Noise: –130 dBc/Hz at 1MHz offset, Fc = 491.52 MHz

Output Frequency Ranges From 4.25 MHz to 1.175 GHz in Synthesizer Mode

Independent Output Dividers Support Divide Ratios from 1–80, Non-Continuous Values Supported

Clock Generator Mode Using Crystal Input

Data Converter and Data Aggregation Clocking Wireless Infrastructure Switches and Routers Industrial Medical Clock Generation and Jitter Cleaning High Speed Serial Interfaces

Multi-Ca


38TI High Performance Clock Generation and Frequency Synthesis Devices

RF Switch

DAC

DAC

CDCE62005

ADC2 lvds

2 lvds

2 lvds90

0

TRF3765400 MHz - 4.8GHz

ADC2 lvds

0 /90

Clock Generation

PLL VCO

PLL VCO

FMC

Connector See this SDR

demonstration at the exhibit area!


39LMK04800 – Precision Clock Jitter Cleaners

Dual Loop PLL Architecture for ultra low jitter cleaning using low cost VCXO

Total RMS Jitter 112 fs RMS jitter (12 kHz to 20 MHz) @ 245.76MHz

Phase Noise –145dBc/Hz (800 kHz offset) @ 245.76MHz

Programmable Digital Delay, Analog Delay and 0-delay mode

Holdover mode when input clock is lost Output Clock rates of up to 3 GHz 12 LVPECL, LVDS or LVCMOS

programmable outputs

3x clock output rate than closest competitor Lowest jitter and phase noise clock cleaner in

the industry Ultra-low phase noise enables MC – GSM in

macro cell BTS Ultra-low jitter clocks enables

High sensitivity radios – Improves overall wireless coverage radius

Higher throughput of high speed SERDES –Improves the maximum data rate

Multi-Carrier GSM, WCDMA, LTE Base Stations

Optical Transport Networks Video Broadcast Servers Clocking High Speed Data Converters

PLL

Dist

PLL


4040

-136

Converting Phase Noise to RMS

Angular frequency

of clockSample instant = phase 0

phase noise

Phase noise in region =(-100 – 126)/2+ 10log10(1000 - 100)

f122.88 MHz

Ex: fclk = 122.88 MHz

…

-100-200-300-400-500-600-700-800

1 KHz 10 KHz 100 KHz 1 MHz 10 MHz

-127

-153-158

Frequency offset

from fclk

-126

-100

Noi

se p

ower

(dB

c / H

z)

clk

noise

T fRMSJ

2102 10/

0x

6

-5.62

1088.1222102

xxx

= 283 fs

Total Phase noise estimate in integration bandwidth from 100 Hz … 20 MHz = -76.88 dBc

Deviation from center frequency– Ex. 122.88 MHz

Evaluated with a spectrum analyzer Measured in dBc/Hz


4141

More Reading …

Analog Devices Application Note AN-756

“Sampled Systems and the Effects of Clock Phase Noise and Jitter”

Author: Brad Brannon


42Agenda



Case Studies


– DDR3

– Motor Control

Closing Comments


43HD Video Demands Stringent Clocking

Typical video processing system with multiple frame buffers created in DDR3 memory

For 1080x1920 with 75fps, each stream requires 622MB/s (~5Gb/s) of memory bandwidth!

DDR3 clocks must run at 800MHz with low peak-to-peak jitter for maximum timing budget

DDR3 @ 800MHz (1600Mb/s)


44New 7 Series Phaser for High Performance DDR3 Memory Interface

PHASER IN– VT stable circuit for

read data capture PHASER OUT

– VT stable circuit generates clocking for data writes

IOSERDES– reduce data rate /4– FPGA fabric clock

@ 200MHz Clean clock required

to maximize < 5ns timing budget

44

How do we choose a proper input clock?


45Xilinx Timing Analyzer

Calculates effects of jitter in timing analysis Reported as “clock uncertainty” in timing reports Automatically calculated for PLL/MMCM circuits

Use SYSTEM_JITTER to over-constrain margin on all clocks

Use INPUT_JITTER to specify jitter on one clock domain

45


46XAPP741 Timing Report Example

110ps clock uncertainty (lower is better) Need clean system clock for maximum timing margin

46


47

Features:• Low Jitter : 0.6 ps RMS Jitter • Frequencies from : 50 to 690 MHz• Supports LVDS & LVPECL outputs• Has Frequency Margining Feature • Package option: 8-TSSOP, 6-LCC• Both Xtal inside(6 LCC) & Xtal

outside(8 TSSOP) device available

CYPRESS FLEXO

• App Notes: AN62914, AN52133• Programming Kits: CY3672, CY3675• Software: CyClocks™, CyClockWizard 1.0• Brochure: Timing Brochure, FleXO Overview

Collateral

• FleXO helps generate low jitter clock signals for 10G Ethernet cards

• With FleXO frequency margining feature, Customer saves cost and test times

• FleXO has better cost to performance ratio over SAW or Overtone crystal oscillators

Advantages

PROGRAMMABLE FREQUENCY

Cypress FleXOSave cost and time with the world’s most flexible high-performance clock

XO

XOChip A

Chip A

Pin or I²C

FREQUENCY MARGINING

• Routers• Switches• Blade Servers• Wireless Basestation• Storage Server• Datacom/Telecom/Networking• Any application that needs clean clock in the

supported frequency range

Applications


48

Programming Kits Consist of1.Main Programming kit 2.Socket adapters

Three Steps for Programming1. Create the JEDEC file (using software )2. Set up the Programming Kit3. Program the device using the JEDEC

Overview of Programming

1. CY3675 CyClockProgrammer Kit 2. CY3672-USB Developer Kit3. Clock Programmer Guide4. Configuring FleXO5. Programming using CyberClocks and CY3672-USB

User Guide and Videos

Cypress Clock Programming Kitsoffers Flexible Field Programmability

Supported Devices

CY3675 Programming Kit

• Programmable Crystal Oscillators : CY25701/CY25702• Crystal Inside FleXO : CY2X0*, CY2XF*• 4 PLL SSCG – CY254*

CY3672-USB Developer Kit

• EMI reduction clocks - CY25100, CY22050/150, CY25200• Multiclock - CY22392/3/4/5, CY22381• Other Devices : CY2077( 1 o/p CG), CY25701( Programmable

XO),CY23FP12(Field Programmable ZDB)

1. CyberClocks2. CyClockWizard 1.03. CyberClocksOnline

Configuration/Programming Software


49Zynq-7000 EPP Simplifies System Clocking

Processor Subsystem (PS) requires a single reference clock PS_CLK must be 30-60 MHz Nominal PS_CLK = 33.333MHz

DDR PLL = 1066 MHz CPU PLL = 1333 MHz I/O PLL = 1500 MHz

Each has a PLL source selection multiplexer and programmable divider Four general-purpose clock outputs are generated for the PL

Con

trol

Reg

iste

rs


50Zynq Clocking Wizard in XPS

50

Zynq pocessor PLLs automatically configured


51Agenda



Case Studies


– DDR3

– Motor Control

Closing Comments


52Never Say Never – FPGAs Clocking Data Converter Case Study

Spartan-6 FPGA Motor Control Kit Example

Quad 16-bit Sigma-Delta modulator 10MHz modulator clock 80kHz BW of interest Suppose we used an FPGA PLL to clock them …


53Clocking Data Converters With FPGAs

16-bit, 10Msps data converter with 10MHz input clock Analog input bandwidth of interest ~80kHz Can we use the Xilinx PLL for the sampling clock?

Xilinx clocking wizard calculates PLL output jitter– Input clock: 100MHz oscillator @ .001UI jitter (Pk-Pk)– Output clock: 20Msps @ 130ps jitter (Pk-Pk)

Calculate RMS from Pk-Pk jitter assuming 10-10 BER– RMS jitter calculation ~10ps– Best achievable SNR 99dB ~ 16.2 ENOB

…. FPGA PLL is not a limiting factor in ENOB!


54Low BW of Interest Allows Data Converter Clocking with FPGA PLL

Spartan-6 FPGA Motor Control Kit Example

PLL set for minimum output jitter

DDR clock forwarding for minimum skew


55Agenda



Case Studies


– DDR3

– Motor Control

Closing Comments


56Next Steps

Attend Xilinx ATP 2 day courses– Designing for Performance (2 day) – Designing with the Xilinx 7 Series Families

Download clock selector & analysis tools from ADI, Cypress, and TI

Experiment with Xilinx Clocking Wizard Visit clocking experts at partner booths Observe Avnet & Xilinx demonstration booths

– Analog Devices ZedBoard SDR Kit– Texas Instruments ZedBoard SDR Kit– Spartan-6 FPGA Motor Control Kit– Avnet Kintex™-7 Mini-Module Plus (MMP) PCIe


Thank YouPlease Visit the Demo Area


APPENDIX


5959

Period Jitter JT0RMS– Deviation in clock period (from ideal T0) over many samples

toti

1i

20i

tot0 T-T

i1RMSJT

toti

1i

2i-1i

tot

T-Ti1RMSJCC

Ti-1 Ti

Histogram

Average differencein period

# of times aperiod is observedJRMS

Clock Jitter

Cycle-to-Cycle Jitter JccRMS– Difference in two consecutive periods (over many samples of

consecutive periods) Equivalent to standard deviationσ of Gaussian distribution

TiT0


607 Series PCIe Clocking

7 series PCIe block requires a 100MHz or 250MHz system clock input– The clock frequency used must match the clock frequency selection in

the CORE Generator™ GUI– In a typical PCIe system, the Endpoint device PCIe reference clock input

is a 100MHz clock provided by the PCIe edge connector• Some Endpoint devices require an external PLL

Artix-7 Kintex-7 Virtex-7

Gen 1 100 MHz 100 MHz 100 MHz

Gen 2 100 MHz 100 MHz 100 MHz

Gen 3 Hard IP

N/A N/A 250 MHz

Gen 3 Soft IP

N/A 250 MHz 250 MHz

Reference Clock Input


61PCIe jitter specs

GEN3– RMS jitter of 1ps (per Virtex™-7 MGT spec)– Xilinx design may require 250 MHz clock– Robust designs implement PLL jitter cleaner with

spread spectrum tolerance and programmable output GEN2

– RMS jitter 3.1ps– Jitter cleaner recommended

GEN1– Route 100MHz reference from connector to FPGA

61


XILINX


63Xilinx 7 Series MIG PLL/MMCM Requirement

Design Advisory MIG 7 Series - Addition of MMCM to clocking structure starting with v1.5 (available with ISE Design Suite 14.1)

Both PLL and MMCM required. MMCM used to remove BUFG skew over VT Answer Record #47043

http://www.xilinx.com/support/answers/47043.htm


TEXAS INSTRUMENTS


65TI Clocking for PCI Express

USB

USB

3.0

PCI

PCI E

xpre

ss G

en1

PCI E

xpre

ss G

en2

PCI E

xpre

ss G

en3

CPR

I

OBS

AI

Eth

erne

t

Gig

abit

Ethe

rnet

10G

Eth

erne

t

XAU

I

SRIO

OC

48

OC

3

OC

12

OC

192

XTA

L In

put

Fibe

r Cha

nnel


66

Traditional Approach TI Approach

• Multiple VCSOs required for generating unique reference clocks

• Typical VCSO RMS jitter 300 fs• Larger Board Area• Higher BOM Cost

• LMK03806/CDCM6208 generates multiple reference clocks (multi format/freq)

• Best Jitter - LMK03806 RMS jitter < 150 fs (typical, in XO mode)

• Good Jitter, Low Power, Flexible: CDCM6208: RMS Jitter 300 fs (typical, in XTAL mode), 0.5W

• Smaller Board area

Conventional Approach

10GEthernet

10GEthernet

Processor

FPGA

Backplane

156.25 MHz

LVPECL

LVPECL

33.33 MHz

125 MHz

227.27 MHz

Wireline Clocking SolutionsTI Approach, One Resonator many frequencies/any form


67

Ultra-low jitter: Sub-150 fs rms jitter at 156.25 MHz

output frequency (12 kHz – 20 MHz) with XO as reference input

Sub-250 fs rms jitter at 156.25 MHz output frequency (12 kHz – 20 MHz) with low cost crystal reference input

Integrated VCO with programmable divider 14 outputs, programmable as LVDS, LVPECL,

LVCMOS Generates up to 7 different ultra low jitter

clocks from 2.3 MHz to 2.6 GHz

Improves overall bit error rate and carrier-to-noise ratio performance

Simplifies timing design by simultaneously generating multiple reference clocks for SerDes, FPGA, ASICs, DSPs etc.

Eliminates need for external level translators and fanout buffers

Replaces multiple XO, VCXO, VCSO, Clock Generators and reduces BOM cost by 50%

LMK03806 – Ultra-Low Jitter Clock Generator

Multi-gigabit Ethernet, SONET/SDH, Fibre Channel Line Cards, OLT and ONU for GPON

Clocking high performance data converters Test and Measurements


68

1-Jun-12 68

CDCM6208Ultra Low Power, Clock Generator / Jitter Cleaner

• Networking, Wireless, and Computing– SRIO, XAUI, PCIe Gen3, Infiniband

• Medical Imaging• BBU clocking• Perfect for TI-DSP Clocking (Keystone DSP)• Storage Server, Portable Test Equipment

• Low Jitter improves link performance.• Fractional dividers eliminate crystal oscillators and other

clock generators.• Innovative architecture achieves many common

communications frequencies simultaneously (derived from one reference)

• Good PSRR simplifies power supply requirements and reduces cost.

• Mixed mode LVCMOS outputs eliminates logic level translation reducing cost and saving board space.

• Simple pin configuration and software GUI accelerates clock tree designs.

• Low Noise– 300 fs typ in synthesizer mode (800fs max)– 2.0ps-rms max in jitter cleaner mode.

• Integer Dividers generate low noise clocks• Fractional Dividers generate any clock frequency with

< 1ppm additive error• Device configuration via pins or host interface (I2C or

SPI)– Pin configurations for many common

communications and computing frequencies.• Internally regulated supplies (supports 1.8V, 2.5V,

and/or 3.3V operation and I/O).• Support for LVPECL-like, LVDS-like, CML, HCSL, and

CMOS I/O• Very low power consumption (< 500 mW typ)

Samples April 2012


69

69

On-Chip VCXO

PLL+

Clock Buffer

Fan-outBuffer

Low EMI, Low Power, 0-ppm error Frequency Generator

PLL+

VCOVCO

Vctrl

On the Fly Customization

PLL+

VCO

I2CControl

lines

AVR, Mobile, Audio, MCU application coverage

Distributed clock system configuration

Wide input frequency

tuning range

High flexibility Total device

re-configurability

ADDED VALUE

Many Options in One Device – CDCE9xx


70Clock Generator Portfolio


ANALOG DEVICES

72

AD9522, Lowest jitter LVDS/CMOS24-Output Clock Generators with Integrated VCO

Critical Functions: On-Chip VCOs ranging from 1.5 – 2.95 GHz

Option to connect external VCO/VCXO

Low phase noise, Broadband Jitter <0.5 ps rms

12/24 LVDS/CMOS outputs

EEPROM for User defined startup

Zero Delay Mode

Part# On-Chip VCOAD9522-0 2.53 - 2.95 GHzAD9522-1 2.27 - 2.65 GHzAD9522-2 2.02 - 2.335 GHzAD9522-3 1.72 - 2.25 GHzAD9522-4 1.40 – 1.80 GHz

Temperature GradesPackage

Product Status

-40 to +85 °C64 LFCSP

Released to ProductionRecommended for new designs

OPTIONAL REF1

REF2

CLK

LF

SW

ITC

HO

VE

RA

ND

MO

NIT

OR

PLL

DIVIDERAND MUXES

ZERODELAY

CP

VCO

STATUSMONITOR

SPI/I2C CONTROLPORT AND

DIGITAL LOGICEEPROM AD9522

OUT0OUT1OUT2

DIV/Φ

OUT3OUT4OUT5

DIV/Φ

OUT6OUT7OUT8

DIV/Φ

OUT9OUT10OUT11

DIV/Φ

LVDS/CMOS

REFIN

REFIN

0721

9-00

1

73

AD9957Features

Generates Direct I/F to 450 MHz 1.2 W at full speed Fast 18-bit parallel I/Q data port Improved Reference Clock multiplier Optional inverse sin(x)/x filter 8 Programmable profile registers Multi-device Synchronization Easy interface to Blackfin® DSP 100 pin TQFP

Applications Communications Infrastructure WiMAX Transmit xCDMA Transmit GSM/EDGE Transmit Cable modems

Alternate Technology to TxDAC topologyModulation done in digital domain

Yields perfect quadrature

AD955x Selection table

74

DeviceRTS date

Application Inputs / Outputs Output logic# active

PLL Channels

Jitter Package

AD9550Released

- xDSL / Gb Ethernet- Oscillator replacement- Low cost SONET/SDH

1 Input Channel or crystal reference8kHz - 200 MHz2 output channelsUp to 800 MHz

Programmable LVPECL or LVDS or CMOS

1RMS jitter: 1.2ps[12kHz – 20MHz] 5x5 32 LFCSP

AD9551Released

- Line Cards-SONET/SDH/10 GbE/FC

+ key FEC rates.

2 Input Channels104 MHz - 806 MHz2 Output Channels10 MHz - 900 MHz

LVPECL, LVDS,Or CMOS

1 RMS jitter: 0.6ps[50kHz – 80MHz]

6x6 40 LFCSP

AD9552Released

- Oscillator replacement- SONET/SDH /10 GbE/FC

Single Input or Crystal reference6.6 MHz – 112.5 MHz2 output channelsUp to 900 MHz

LVPECL, LVDS,Or CMOS

1RMS jitter: 0.5ps[12kHz – 20MHz]

5x5 32 LFCSP

AD9553Released

- GPON- Oscillator replacement- Low cost SONET/SDH/GE

2 Input Channels or crystal reference8kHz - 200 MHz2 output channelsUp to 800 MHz

Programmable LVPECL or LVDS or CMOS


5x5 32 LFCSP

AD9557/8Released

-Line Cards-Stratum 3 compatible SONET/SDH-Synchronous Ethernet-10 GbE/FC + key FEC rates-OTN Mapping/De-mapping-TDM over Ethernet

2/4 Input channels2kHz- 1.25 GHz]2/6 Output channels1.5MHz- 1.25 GHz

Programmable HSTL or LVDS or CMOS


AD9557:6x6 40 LFCSPAD9558:9x9 64 LFCSP

AD9559Sampling

-Line cards-Stratum 3 compatible SONET/SDH-Synchronous Ethernet-10 GbE/ FC-OTN Mapping/De-mapping-TDM over Ethernet

2 Input channels2kHz - 1.25 GHz IN

2 output channels1.5MHz to 1.25GHz

Programmable HSTL or LVDS or CMOS


10x10 72 LFCSP

AD9557: Multi-protocol Clock TranslatorTranslates between all primary network standard frequencies, supports FEC ratios

Stratum 3 compatible SONET/SDH, Synchronous Ethernet, 10GbE

Status

ReleasedPackage 40 pin LFCSP

75 —Analog Devices Confidential Information—

Crystal or Reference Clock Input

Digital PLL+ Analog PLL

Clock Distribution

/Q

/Q

Ref

eren

ce In

puts

Mon

itorin

g, M

ux

Reference Input/Crystal Oscillator

CLKIN1

CLKIN2

CLKOUT1

CLKOUT2

Differential Outputs-360 kHz TO 1.25 GHzSingle Ended CMOS- 360 kHz TO 250 MHZ

Differential Inputs2 kHz-1.25GHzSingle Ended CMOS2 kHz-250 MHZ

EEPROMSPI/I2CInterface

Pin ControlN

Pin Control/Monitor-LOL/LOR/OOL Alarms-Man/Auto Switchover-Fsync Align-Clock Config/Select

VDD(1.8V) GND

2 differential or 2 single-ended reference inputs : 2 kHz – 1.25GHz for differential On-Chip Reference MonitorsSwitchover Holdover (Stability dependent on Reference) Stratum 3 Phase build out

<5ns phase change on output Programmable Digital Loop Filter

Supports Loop bandwidths from 0.1 Hz to 2kHz

2 differential Clock OutputsLVDS / HSTL / LVPECL compatibleCMOS (Configurable to four single ended outputs)

Output frequency range360kHz - 1.25 GHz

Low Jitter: 300fs (12kHz – 20MHz)Low Spurious: <-70dbc Adaptive Clock Generation for OTN mappingGapped Clock supportEEPROM based Non-volatile preset

AD9558More In/Out

AD9559Dual

76

AD9550 : Pin programmable Multi-purpose Integer-N Clock Translator

Package

5x5 32LFCSP

Status

Released

Output frequencyPin selectable from 1.3MHz to 800MHz LVDS, LVPECLAnd from 1.3MHz - 200 MHz CMOS

Input frequency range

Pin selectable up to 250 MHz CMOS

KEY BENEFITS & FEATURES 1 CMOS inputs with options on : 8 kHz – 200MHz 2 differential Clock Outputs (LVDS/LVPECL) or 4 single-ended CMOSOutput frequency with options on : 1.3 MHz- 800 MHzLoop bandwidth down to 100HzMax RMS Jitter : 1.2ps (12kHz – 20MHz)Pin programmable mode supporting most standard needed frequency translations.Low power: <450 mW (under most conditions)

Applications:

Oscillator replacementxDSL Network Processor clockingExtremely flexible frequency translation for SONET/SDH, Gb Ethernet, Fibre ChannelWireless infrastructureTest and measurement (including handheld devices)

Cost effective

77

ADCLK944 Fanout BufferECL Clock Distribution

KEY BENEFITS & FEATURESUp to 4 outputs50 fs rms jitter160 ps propagation delay100 ps output rise/fall times20 ps output-output skew 50 ps device-device skewOn chip input terminations2.5V - 3.3 V power supply

Operating Freq

7 GHz

Output Logic

ECL, PECL, LVPECL

Package

3x3 16-LFCSPStatus

RTS

ADCLK944

Primary Competition IDT, MicrelAdvantagesBetter Timing performance

Lowest Jitter Lowest skew

Small package

///

////

DAC

ADC

Common BTSarchitecture

Technical Challenges:• Interference between PLLs• Output to output spur coupling• Noise imposed outside chip

AD9523 family

“De-Integrating”Going back to the future

ADF435xAD9557/8/9AD9549

DAC

ADC

/

/

AD9516 familyAD9525

Technical relief:• Separating PLLs for less coupling• Moving divider to converters helps coupling, dampens noise from routing

All outputs at same frequency addresses o-o coupling concerns

Synchronizers for the BBU

Part I / O Min ref

Max out (MHz)

Min LF Notable Features

AD9549 2 / 1+1 8 kHz ~ 800 1 Hz Manual or auto Holdover and Hitless switchover

AD9548 4(8) / 4(8)

1 PPS ~ 400 1 mHz Manual or auto Holdover and Hitless switchover

AD9547 2(4) / 2(4)

2 kHz ~ 400 1 mHz Manual or auto Holdover and Hitless switchover

BSC

Synchronicity enables smooth and glitch-free handoffs

Clock Generation & Distribution options

Part Outputs Notable FeaturesAD9516 6 LVPECL +

4 LVDS/8 CMOSFine tune delay on LVDS/CMOS channels

AD9517 4 LVPECL + 4 LVDS/8 CMOS

Fine tune delay on LVDS/CMOS channels

AD9518 6 LVPECL Fine tune delay on LVDS/CMOS channels

AD9520 12 LVPECL/24 CMOS EEPROM

AD9522 12 LVDS/24 CMOS EEPROM

AD9571 3 diff + 7 CMOS Pin programmed, easy to use if frequency plan fits

AD9572 5 diff + 2 CMOS Pin programmed, easy to use if frequency plan fits

AD9577 4 diff/8 CMOS + 1 CMOS

Dual loop (parallel) supports two distinct frequency domains from one chipSpread Spectrum Clocking


CYPRESS


82MULTICLOCKReduce your BOM and Solve EMI problems with programmable spread spectrum clo

Features• Patented Spread Spectrum technology• Optional VCXO functionality• Up to 9 outputs : Integrate more BOM components • Output frequency: upto 200 Mhz• Programmability: I2C• Commercial and Industrial Operating Temperature Range

CY MPN(s): CY2239X/CY254X/CY228X/CY2238X/CY25701

Cypress Multiclock

• App Notes: AN1110, AN1109, AN45324• Programming Kits: CY3672, CY3675• Software: CyClocks™, CyClockWizard 1.0• Brochure: Timing Brochure

Collateral

• Integrate multiple crystal and crystal oscillators on the board leading to saving in the board space

• Solve EMI issues by using Cypress patented Spread Spectrum giving you upto 10 dB of peak reduction

• Reduces overall BOM cost by reducing components and shielding on the board with upto 50% savings

Advantages

Value Proposition

Osc

Osc

Buffer

48 MHz

27 MHz

125 MHz

66.66 MHz

48 MHz

27 MHz

125 MHz

66.66 MHz

1st order, low-costCrystal EMI Test PASS EMI Test PASS

Shielding with Ferrite beads, coils, chokes

CHALLENGE: Potential EMI failure Extra components added at the last

minute

CYPRESS SOLUTION: Integrate Multiple components & use

Programmable spread % for Optimum EMI reduction

No need for extra BOM components

• Multi Function Printers• Home Gateways• Digital Televisions• Router/Switch• Datacom/Telecom/Networking• Any application that needs clean clock in the

supported frequency range

Applications

Xilinx Confidential © Copyright 2011 Xilinx

Comparison to competition for Additive Phase Jitter

Measurement Conditions• All measurements taken under identical conditions• Input: Wenzel OCXO 156.25MHz (12fs phase jitter)• Output: 156.25MHz • LVPECL (Vcc=3.3V; 800mV p-p); LVDS (Vcc=2V; Vee=1.3V)• All phase jitter measurements across 12kHz to 20MHz offset range

Features:• Family of high performance non-PLL clock distribution

solutions• High frequency: up to 1.5 GHz• Ultra low jitter: 42 fs typical additive phase jitter*• Multiple configurations: 2, 4, or 10 outputs; LVPECL,

LVDS, or CML• Voltage translation: LVDS→LVPECL; LVPECL→CML;

LVCMOS→LVPECL

CY MPN(s): CY2DP15X/CY2DL15X/CY2CP1504

CYPRESS HPB

• Timing Uncertainty in High Performance Clock Distribution • Brochure: Timing Brochure

Collateral

• Industry’s lowest additive phase jitter ensures maximum system timing margin

• Fast signal rise/fall times meets the requirements of the latest high-speed applications

• High Performance Buffer family offers best price-performance, with proven Cypress support and quality

Advantages

High Performance BufferBest in class buffer to meet every requirement

• Switches and routers• Wireless base stations• Optical networking (PON, MSTP, etc.)• Blade servers

• High-speed interfaces: Gigabit/10-Gigabit Ethernet (GbE, 10GbE), PCI-Express, FibreChannel, SONET/SDH, CPRI

Applications

Best-In-Class Phase Jitter

Documents

xfest12 ppt clocking v1 2 - eetrend.comxilinx.eetrend.com/files-eetrend-xilinx/download/... · – Precision clock generation & distribution in high ... Intended for clocking high