Www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx COM181 Computer Hardware Lecture 4: The MIPs CPU "Adapted from Computer Organization and

www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx

COM181 Computer Hardware

Lecture 4: The MIPs CPU

"Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2008.” This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders.

Also drawn from the work of Mary Jane Irwin ( www.cse.psu.edu/~mji )

You should read the MIPs handout after this lecture, also we will revisit the MIP instruction set in tutorials and the next lecture

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http://www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx

http://www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx

http://www.cse.psu.edu/~mji


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Assembly language

High-level language e.g a = b + c;Machine language e.g 000000 01000 01001 01010 00000 100001

Assembly language is between high-level and machine

Each statement defines one machine operation

Directly represents architectureSo if the hardware chip can’t multiply then there will be no multiply statement (you can multiply by successive addition!)

MIPs has very limited, simple, instructions.It has 32 registers and can add, subtract, and, or, ex-or and shift

There is one instruction to move (copy) 32 bit data from memory to a register and one instruction to move(copy) 32 bit data to memory(i.e you can’t just add the contents of a memory location to another – they have to be brought into registers to do the addition)Assembler program translates to machine language


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INSTRUCTION SET ARCHITECTURES (ISA): TypesCISC: complex instruction set computer: Traditional computer architecture

Unique instructions for as many operations as possible

RISC: reduced instruction set computer: Look at actual instruction use, focus on most frequent ones

Advantages Disadvantages

Each instruction can do more work More complex hardware circuits

Programs use less memory More expensive to develop and build

Easier to program directly or to write compilers Usually slower

Advantages Disadvantages

Easier to learn Larger, more complex programs

Simpler circuits Harder to program

Cheaper and more reliable to design and build Depends on compiler for optimization

Faster, quicker to implement when foundry improves silicon processes


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Stored programStored program conceptInstructions and data are stored in the same memoryInstructions are simply another kind of dataInstructions are executed sequentially unless branch elsewhere or stop

Fetch-execute cycle- Instruction fetch

Get the next instruction from memory- Decode

Figure out what operation to perform on which operands

- Operand fetchGet the operand values

- ExecutePerform the operation

- Store resultRepeat until done


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InstructionsAny instruction set must perform a basic set of operationsMay have more complex combinations or special operations as wellTypes of operations

Data transfer: load, store

Arithmetic: add, subtract, multiply, divideLogic: and, or, xor, complement

Compare: equal, not equal, greater than, less than

Branch/jump: change execution order


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MIPSMIPS

"Microcomputer without interlocked pipeline stages"Name is pun on acronym for "millions of instructions per second"

RISC architecture developed in middle '80'sExtended through several versions - current: MIPS IV

Used in many "embedded" applicationsGame machines: Sony, NintendoTV set top boxes: LSI Logic shipped 7 million in 2001Routers: CiscoLaser printersPDAs

High-performance workstations: Silicon Graphics (Lord of the Rings, other films)"Over 100 million sold"


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MIPS: machine model notesMain memorydata: 32-bit address: range from 0x00000000 to 0xFFFFFFFF (upper half of range reserved )Processor32 registers ($r0 to $r31, though $r0 is readonly and holds zero: these store data to perform operations to and from themselves - faster than main memory

load-store architecture: access memory only through load, store instructionsload: register <--- data from memory (ld instruction)store: register ---> data to memory (sw instruction)amount of data in bytes (1, 2, 4, 8) depends on instruction (we’ll stick to 32bit (4 bytes@a time))all other operations use only registers or immediate values (contained in instruction)

Design Principle #2: "Smaller is faster."16 floating point registers (ignore these)ALU: arithmetic-logic unitperforms operations on values in registerscontrol: determines how operations executed ("computer within computer")


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MIPS: instructionsALU performs arithmetic and logical operations (instructions)

Instruction specifies

1. The operation to perform.

2. The first operand (usually in a register).

3. The second operand (usually in a register).

4. The register that receives the result. (we call the MIPs a 3-address machine)

MIPS has about 111 different instructions (we will look at about a dozen)all 32 bits, 3 different formats (r-type, i-type and j-type)

r-types all have three register addresses for 2,3 and 4 abovei-types have 2 registers and a 16bit constant (number).j-type (there is only one instruction!) is a simple JUMP instruction, with a 26bit address built in to the 32 bit instruction.


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MIPS: instruction exampleExample: add unsigned

addu $r10,$r8,$r9 # add 2 numbers this is assemblerSyntax3-operand instructions: all arithmetic/logical operationsoperands separated by commas. Design principle #1: "Simplicity favors regularity."one operation per instruction, one instruction per line

operation: adduregisters

sources : $r8, $r9target : $r10

comment: # add 2 numbers (Comments starts with #, ends with end of line)

Semantics$r10 = $r8 + $r9;

What humans understandR[10] <-- R[8] + R[9]

Alternative way of what

humans understand (RTL)Machine code

hex: 0x01095021

or 0000 0001 0000 1001 0101 0000 0010 0001 in binary!


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0000 0001 0000 1001 0101 0000 0010 0001

MIPS: instruction fields

R-types use three registers, their format is always the same. The 32 bits is split into 6 fields of varying lengths – 6 bit, then 4 x 5 bit then another 6 bit. (i-types have 4 fields, 6,5,5,16)

addu $r10,$r8,$r9 # add 2 numbershex: 0x01095021

0 1 0 9 5 0 2 1

binary: 0000 0001 0000 1001 0101 0000 0010 0001

fields: 000000 01000 01001 01010 00000 100001

b31-26 b25-21 b20-16 b15-11

b10-6 b5-0

opcode $rs $rt $rd shamt function

R-types all have an opcode of six zeroes and the actual function code listed in the rightmost 6 bits. (i-types use the opcode field and have no function field)


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Diagram of MIPS – some parts not shown!!!

View from 30,000 Feet

www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx 15

PCSrc

ReadAddress

InstructionMemory

Add

PC

4

0

1

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

16 32

ALU1

0

Shiftleft 2

Add

DataMemory

Address

Write Data

ReadData

1

0

IF/ID

SignExtend

ID/EXEX/MEM

MEM/WB

Control

0

1

ALUcntrl

Branch

ForwardUnit

IF/ID.RegisterRs

IF/ID.RegisterRt

EX/MEM.RegisterRd

MEM/WB.RegisterRd

The MIPs CPU is described in the textbook, note how the diagram below relates to lecture 3

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Often you must deal with the management of complexity, and use abstraction and partition to reduce systems to sizes that the human brain can cope with...

When programming a MIPs CPU it is enough to maintain a “Programmer’s Model” of the CPU.

The CPU is designed as a RISC (Reduced Instruction Set Computer) machine, this suits implementing the hardware but not necessarily suits humans programming it!

Software tools help

A RISC machine has a fixed length instruction (32 bits in the simple MIPs)A RISC machine has a limited number of addressing modesA RISC machine has a limited number of operations (small instrucution set)A RISC machine has, typically, a register bank and uses load/store instructions (only) to access main memory.

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MIPs machines have three types of Instruction; R-type for arithmetic instructions – using Registers, I-type where the number needed is available immediately and J-type for conditional/control, jumps etc (there are also a few others...)

Example of some MIPS assembly language arithmetic statementsadd $t0, $s1, $s2sub $t0, $s1, $s2

Each arithmetic instruction performs only one operationEach arithmetic instruction specifies exactly three operands

destination source1 op source2Operand order is fixed (the destination is specified first)The operands are contained in the datapath’s register file ($t0, $s1, $s2)

The registers above have been given symbolic names, the actual numbered registers Run from $0 to $31. We use software to convert the statements above to a 32 bit instruction. The ASSEMBLER program can also convert symbols into numbers

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MIPS Register File

Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file

Thirty-two 32-bit registers

Two read ports

One write port

Register File

src1 addr

src2 addr

dst addr

write data

32 bits

src1data

src2data

32locations

325

32

5

5

32

Registers are Fast

- Smaller is faster & Make the common case fast Easy for a compiler to use

- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order Improves code density

- Since register are named with fewer bits than a memory location

Register addresses are indicated by using $

25 =

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0 $zero constant 0 (Hdware)

1 $at reserved for assembler

2 $v0 expression evaluation &

3 $v1 function results

4 $a0 arguments

5 $a1

6 $a2

7 $a3

8 $t0 temporary: caller saves

. . . (callee can clobber)

15 $t7

Naming Conventions for Registers

16 $s0 callee saves

. . . (caller can clobber)

23 $s7

24 $t8 temporary (cont’d)

25 $t9

26 $k0 reserved for OS kernel

27 $k1

28 $gp pointer to global area

29 $sp stack pointer

30 $fp frame pointer

31 $ra return address (Hdware)

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Registers vs. Memory Arithmetic instructions operands must be in registers

only thirty-two registers are provided

Compiler associates variables with registers

What about programs with lots of variables?

Processor

Control

Datapath

Memory

Devices

Input

Output

Network

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Registers vs. Memory Arithmetic instructions operands must be in registers

only thirty-two registers are provided

Compiler associates variables with registers

Processor

Control

Datapath

Memory

Devices

Input

Output

Network

What about programs with lots of variables?08/08/13 www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx

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Memory is a large, single-dimensional array

An address acts as the index into the memory array

Processor – Memory Interconnections

Processor

Memory

32 bits

?locations

read addr/write addr

read data

write data

110110

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Memory is a large, single-dimensional array

An address acts as the index into the memory array

Processor – Memory Interconnections

Processor

Memory

32 bits

?locations

read addr/write addr

read data

write data

32

32

32 232 Bytes (4 GB) 230

Words (1 GW)

= 4 Bytes = 1 Word

110110

048

The data stored in the memory

The word address of the

data



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MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)

lw$t0, 4($s3) #load word from memory

sw$t0, 8($s3) #store word to memory

The data transfer instruction must specify

where in memory to read from (load) or write to (store) – memory address

where in the register file to write to (load) or read from (store) – register destination (source)

The memory address is formed by summing the constant portion of the instruction and the contents of the second register

Accessing Memory

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MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)

lw$t0, 4($s3) #load word from memory

sw$t0, 8($s3) #store word to memory

The data transfer instruction must specify

where in memory to read from (load) or write to (store) – memory address

where in the register file to write to (load) or read from (store) – register destination (source)

The memory address is formed by summing the constant portion of the instruction and the contents of the second register

Accessing Memory

28

32

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Compiling with Loads and Stores Assuming variable b is stored in $s2 and that

the base address of array A is in $s3, what is the MIPS assembly code for the C statement

A[8] = A[2] - b

$s3

$s3+4

$s3+8

$s3+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

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Compiling with Loads and Stores Assuming variable b is stored in $s2 and that

the base address of array A is in $s3, what is the MIPS assembly code for the C statement

A[8] = A[2] - b

$s3

$s3+4

$s3+8

$s3+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]lw $t0, 8($s3)

sub $t0, $t0, $s2

sw $t0, 32($s3)

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Compiling with a Variable Array Index Assuming that the base address of

array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement

c = A[i] - b

add $t1, $s3, $s3 #array index i is in $s3

add $t1, $t1, $t1 #temp reg $t1 holds 4*i

$s4

$s4+4

$s4+8

$s4+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

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Compiling with a Variable Array Index Assuming that the base address of

array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement

c = A[i] - b

add $t1, $s3, $s3 #array index i is in $s3

add $t1, $t1, $t1 #temp reg $t1 holds 4*i

$s4

$s4+4

$s4+8

$s4+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

add $t1, $t1, $s4 #addr of A[i] now in $t1

lw $t0, 0($t1)

sub $s2, $t0, $s1

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Small constants are used quite frequently (50% of operands in many common programs)e.g., A = A + 5;

B = B + 1;C = C - 18;

Solutions? Why not? Put “typical constants” in memory and load them

Create hard-wired registers (like $zero) for constants like 1, 2, 4, 10, …

Dealing with Constants

How do we make this work? How do we Make the common case fast !

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Include constants inside arithmetic instructions

Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself)

MIPS immediate instructions

addi $s3, $s3, 4 #$s3 = $s3 + 4

Constant (or Immediate) Operands

There is no subi instruction, can you guess why not?

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MIPS Instructions, so far

Category Instr Example Meaning

Arithmetic add add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate

addi $s1, $s2, 4 $s1 = $s2 + 4

Datatransfer

load word lw $s1, 32($s2) $s1 = Memory($s2+32)

store word sw $s1, 32($s2) Memory($s2+32) = $s1

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Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2

registers have numbers $t0=$8,$s1=$17,$s2=$18

Instruction Format:

Can you guess what the field names stand for?

Machine Language - Arithmetic Instruction

op rs rt rd shamt funct

000000 10001 10010 01000 00000 100000

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Instructions, like registers and words of data, are also 32 bits long

Example: add $t0, $s1, $s2

registers have numbers $t0=$8,$s1=$17,$s2=$18

Instruction Format:

Machine Language - Arithmetic Instruction


000000 10001 10010 01000 00000 100000

Can you guess what the field names stand for?

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MIPS Instruction Fields

op

rs

rt

rd

shamt

funct


6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits

opcode indicating operation to be performed

address of the first register source operand

address of the second register source operand

the register destination address

shift amount (for shift instructions)

function code that selects the specific variant of the operation specified in the opcode field

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Consider the load-word and store-word instr’s

What would the regularity principle have us do?

But . . . Good design demands compromise Introduce a new type of instruction format

I-type for data transfer instructions (previous format was R-type for register)

Example: lw $t0, 24($s2)

Where's the compromise?

Machine Language - Load Instruction

op rs rt 16 bit number

23hex 18 8 24

100011 10010 01000 0000000000011000

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Consider the load-word and store-word instr’s

What would the regularity principle have us do?

But . . . Good design demands compromise Introduce a new type of instruction format

I-type for data transfer instructions (previous format was R-type for register)

Example: lw $t0, 24($s2)

Machine Language - Load Instruction


23hex 18 8 24

100011 10010 01000 0000000000011000

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Memory Address Location Example: lw $t0, 24($s2)

Memory

data word address (hex)

0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s2 0x12004094

0x00000002

2410 + $s2 =

Note that the offset can be positive or negative

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Memory Address Location Example: lw $t0, 24($s2)

Memory

data word address (hex)

0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s2 0x12004094

0x00000002

2410 + $s2 =

Note that the offset can be positive or negative

. . . 1001 0100+ . . . 0001 1000 . . . 1010 1100 = 0x120040ac

0x120040ac

$t0

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Example: sw $t0, 24($s2)

A 16-bit offset means access is limited to memory locations within a range of +213-1 to -213 (~8,192) words (+215-1 to -215 (~32,768) bytes) of the address in the base register $s2 2’s complement (1 sign bit + 15 magnitude bits)

Machine Language - Store Instruction


43 18 8 24

101011 10010 01000 0000000000011000

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Example: sw $t0, 24($s2)

A 16-bit offset means access is limited to memory locations within a range of +213-1 to -213 (~8,192) words (+215-1 to -215 (~32,768) bytes) of the address in the base register $s2 2’s complement (1 sign bit + 15 magnitude bits)

Machine Language - Store Instruction


43 18 8 24

101011 10010 01000 0000000000011000

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What instruction format is used for the addi ?addi $s3, $s3, 4 #$s3 = $s3 +

4

Machine format:

Machine Language – Immediate Instructions

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What instruction format is used for the addi ?addi $s3, $s3, 4 #$s3 = $s3 + 4

Machine format:

Machine Language – Immediate Instructions

op rs rt 16 bit immediate I format

8 19 19 4

The constant is kept inside the instruction itself! So must use the I format – Immediate format Limits immediate values to the range +215–1 to -215

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Instruction Format Encoding Can reduce the complexity with multiple formats

by keeping them as similar as possible First three fields are the same in R-type and I-type

Each format has a distinct set of values in the op fieldInstr Frmt op rs rt rd shamt funct address

add R 0 reg reg reg 0 32ten NA

sub R 0 reg reg reg 0 34ten NA

addi I 8ten reg reg NA NA NA constant

lw I 35ten reg reg NA NA NA address

sw I 43ten reg reg NA NA NA address


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Assembling Code Remember the assembler code we compiled last lecture for the C

statement

A[8] = A[2] - b

lw $t0, 8($s3) #load A[2] into $t0

sub $t0, $t0, $s2 #subtract b from A[2]

sw $t0, 32($s3) #store result in A[8]

Assemble the MIPS object code for these three instructions (decimal is fine)

lw

sw

sub

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Assembling Code Remember the assembler code we compiled last lecture for the C

statement

A[8] = A[2] - b

lw $t0, 8($s3) #load A[2] into $t0

sub $t0, $t0, $s2 #subtract b from A[2]

sw $t0, 32($s3) #store result in A[8]

Assemble the MIPS object code for these three instructions (decimal is fine)

35lw 19 8 8

43sw 19 8 32

0sub 8 18 8 0 34

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Review: MIPS Instructions, so farCategory Instr Op

CodeExample Meaning

Arithmetic(R format)

add 0 & 32

add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 & 34

sub $s1, $s2, $s3 $s1 = $s2 - $s3

Arithmetic(I format)

add immediate

8 addi $s1, $s2, 4 $s1 = $s2 + 4

Datatransfer(I format)

load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1

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MIPS Operand Addressing Modes Summary Register addressing – operand is in a register

Base (displacement) addressing – operand’s address in memory is the sum of a register and a 16-bit constant contained within the instruction

Immediate addressing – operand is a 16-bit constant contained within the instruction

1. Register addressingop rs rt rd funct Register

word operand

op rs rt offset

2. Base addressing

base register

Memoryword or byte operand

3. Immediate addressingop rs rt operand

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MIPS Instruction Addressing Modes Summary

PC-relative addressing – instruction’s address in memory is the sum of the PC and a 16-bit constant contained within the instruction

Pseudo-direct addressing – instruction’s address in memory is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC

4. PC-relative addressingop rs rt offset

Program Counter (PC)

Memorybranch destination instruction

5. Pseudo-direct addressingop jump address

Program Counter (PC)

Memoryjump destination instruction||

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Review: MIPS Instructions, so farCategory Instr OpC Example Meaning

Arithmetic(R & I format)

add 0 & 20 add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 & 22 sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate 8 addi $s1, $s2, 4 $s1 = $s2 + 4

shift left logical 0 & 00 sll $s1, $s2, 4 $s1 = $s2 << 4

shift right logical 0 & 02 srl $s1, $s2, 4 $s1 = $s2 >> 4 (fill with zeros)

shift right arithmetic

0 & 03 sra $s1, $s2, 4 $s1 = $s2 >> 4 (fill with sign bit)

and 0 & 24 and $s1, $s2, $s3 $s1 = $s2 & $s3

or 0 & 25 or $s1, $s2, $s3 $s1 = $s2 | $s3

nor 0 & 27 nor $s1, $s2, $s3 $s1 = not ($s2 | $s3)

and immediate c and $s1, $s2, ff00 $s1 = $s2 & 0xff00

or immediate d or $s1, $s2, ff00 $s1 = $s2 | 0xff00

load upper immediate

f lui $s1, 0xffff $s1 = 0xffff0000

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Review: MIPS Instructions, so farCategory Instr OpC Example Meaning

Datatransfer(I format)

load word 23 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 2b sw $s1, 100($s2) Memory($s2+100) = $s1

load byte 20 lb $s1, 101($s2) $s1 = Memory($s2+101)

store byte 28 sb $s1, 101($s2) Memory($s2+101) = $s1

load half 21 lh $s1, 101($s2) $s1 = Memory($s2+102)

store half 29 sh $s1, 101($s2) Memory($s2+102) = $s1

Cond. branch(I & R format)

br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L

br on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L

set on less than immediate

a slti $s1, $s2, 100 if ($s2<100) $s1=1; else $s1=0

set on less than 0 & 2a slt $s1, $s2, $s3 if ($s2<$s3) $s1=1; else $s1=0

Uncond. jump

jump 2 j 2500 go to 10000

jump register 0 & 08 jr $t1 go to $t1

jump and link 3 jal 2500 go to 10000; $ra=PC+408/08/13


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Review: MIPS R3000 ISA Instruction Categories

Load/Store

Computational

Jump and Branch

Floating Point

coprocessor

Memory Management

Special

3 Instruction Formats: all 32 bits wide

R0 - R31

PC

HI

LO

OP rs rt rd shamt funct

OP rs rt 16 bit number

OP 26 bit jump target

Registers

R format

I format

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

J format

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RISC Design Principles Review Simplicity favors regularity

fixed size instructions – 32-bits

small number of instruction formats

Smaller is faster

limited instruction set

limited number of registers in register file

limited number of addressing modes

Good design demands good compromises

three instruction formats

Make the common case fast

arithmetic operands from the register file (load-store machine)

allow instructions to contain immediate operands

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The Code Translation HierarchyC program

compiler

assembly code

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Compiler

Transforms the C program into an assembly language program

Advantages of high-level languages many fewer lines of code

easier to understand and debug

…

Today’s optimizing compilers can produce assembly code nearly as good as an assembly language programming expert and often better for large programs smaller code size, faster execution

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compiler

assembly code

assembler

object code

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Does a syntactic check of the code (i.e., did you type it in correctly) and then transforms the symbolic assembler code into object (machine) code

Advantages of assembler

much easier than remembering instr’s binary codes

can use labels for addresses – and let the assembler do the arithmetic

can use pseudo-instructions

e.g., “move $t0, $t1” exists only in assembler (would be implemented using “add $t0,$t1,$zero”)

When considering performance, you should count instructions executed, not code size

Assembler


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1. Builds a symbol table which holds the symbolic names (labels) and their corresponding addresses A label is local if it is used only within the file where its

defined. Labels are local by default.

A label is external (global) if it refers to code or data in another file or if it is referenced from another file. Global labels must be explicitly declared global (e.g., .globl main)

2. Translates each assembly language statement into object (machine) code by “assembling” the numeric equivalents of the opcodes, register specifiers, shift amounts, and jump/branch targets/offsets

The Two Main Tasks of the Assembler


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MIPS (spim) Memory AllocationMemory

230

words

0000 0000

f f f f f f f c

TextSegment

Reserved

Static data

Mem Map I/O

0040 0000

1000 00001000 8000

7f f f f f fcStack

Dynamic data

$sp

$gp

PC

Kernel Code & Data

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Other Tasks of the Assembler Converts pseudo-instr’s to legal assembly code

register $at is reserved for the assembler to do this

Converts branches to far away locations into a branch followed by a jump

Converts instructions with large immediates into a lui followed by an ori

Converts numbers specified in decimal and hexidecimal into their binary equivalents and characters into their ASCII equivalents

Deals with data layout directives (e.g., .asciiz)

Expands macros (frequently used sequences of instructions)

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Typical Object File Pieces Object file header: size and position of the following pieces of the file

Text (code) segment (.text) : assembled object (machine) code

Data segment (.data) : data accompanying the code

static data - allocated throughout the program

dynamic data - grows and shrinks as needed

Relocation information: identifies instructions (data) that use (are located at) absolute addresses – not relative to a register (including the PC)

on MIPS only j, jal, and some loads and stores (e.g., lw $t1, 100($zero) ) use absolute addresses

Symbol table: global labels with their addresses (if defined in this code segment) or without (if defined external to this code segment)

Debugging information

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An Example.data.align 0

str: .asciiz "The answer is "cr: .asciiz "\n"

.text

.align 2

.globl main

.globl printfmain: ori $2, $0, 5

syscallmove $8, $2

loop: beq $8, $9, doneblt $8, $9, brncsub $8, $8, $9j loop

brnc: sub $9, $9, $8j loop

done: jal printf

Gbl? Symbol Addressstr 1000 0000

cr 1000 000b

yes main 0040 0000

loop 0040 000c

brnc 0040 001c

done 0040 0024

yes printf ???? ????

Relocation Info

Address Data/Instr1000 0000 str

1000 000b cr

0040 0018 j loop

0040 0020 j loop

0040 0024 jal printf


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compiler

assembly code

assembler

object code library routines

executable

linker

machine code

main text segment

printf text segment

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LinkerTakes all of the independently assembled code segments and “stitches” (links) them

together

Faster to recompile and reassemble a patched segment, than it is to recompile and reassemble the entire program

1. Decides on memory allocation pattern for the code and data segments of each module

Remember, modules were assembled in isolation so each has assumed its code’s starting location is 0x0040 0000 and its static data starting location is 0x1000 0000

2. Relocates absolute addresses to reflect the new starting location of the code segment and its data segment

3. Uses the symbol tables information to resolve all remaining undefined labels

branches, jumps, and data addresses to/in external modules

Linker produces an executable file

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Linker Code Schematic

printf: . . .

main: . . . jal ????

call, printf

Linker

Object file

C library

Relocation info

main: . . . jal printfprintf: . . .

Executable file

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Linking Two Object FilesH

dr

T

xtse

g

D

seg

R

eloc

S

mtb

l D

bg

File 1

Hdr

T

xtse

g

Dse

g

Rel

oc S

mtb

l D

bg

File 2

+

Executable

Hdr

T

xtse

g

Dse

g

R

eloc

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compiler

assembly code

assembler

object code library routines

executable

linker

loader

memory

machine code



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Loader Loads (copies) the executable code now stored on disk into

memory at the starting address specified by the operating system

Copies the parameters (if any) to the main routine onto the stack

Initializes the machine registers and sets the stack pointer to the first free location (0x7fff fffc)

Jumps to a start-up routine (at PC addr 0x0040 0000 on xspim) that copies the parameters into the argument registers and then calls the main routine of the program with a jal main

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Dynamically Linked Libraries Statically linking libraries mean that the library becomes part

of the executable code

It loads the whole library even if only a small part is used (e.g., standard C library is 2.5 MB)

What if a new version of the library is released ?

(Lazy) dynamically linked libraries (DLL) – library routines are not linked and loaded until a routine is called during execution

The first time the library routine called, a dynamic linker-loader must

find the desired routine, remap it, and “link” it to the calling routine (see book for more details)

DLLs require extra space for dynamic linking information, but do not require the whole library to be copied or linked

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Documents

Www.eej.ulster.ac.uk/~ian/modules/COM181/files/COM181_L4.pptx COM181 Computer Hardware Lecture 4: The MIPs CPU "Adapted from Computer Organization and