WRR ARBITER Mid-term Presentation

WRR ARBITERMid-term Presentation

Students: Ofer SobelGuy Marcus

Supervisor: Moshe Porian 11/1/11

Project Goal

Implementing a WRR ARBITER on an FPGA

Implementation will be to Altera Cyclone® II 2C35 FPGA located on an Altera DE2 board

Project steps

Determining specificationsArchitecture characterization Conceptual design• VHDL implementation• Verification• Synthesis• Real-Time testing

Top level design

RX

TX

UART _ RECEIVER

UART _ TRANSMITTER

MSG _ DECODER

FIFOREGISTER

BUSMASTER

MSG _ ENCODER

FIFO

ARBITER MODULE

REQUESTS

GRANTS

FILT

ER

EXT_CLOCK

EXT_RESET

PLL

RESET_BLOCK

SYS_CLK

SYS_RST

CONTROLLER

CRC

CRCWRR ARBITER

HOST

REG

ISTE

R B

US

RX PATH – detailed view

RX

rx_data

rx_valid

8

rx_ack

rx_e

rror

UART_ RECEIVER

MESSAGE_DEC

dec_error

dec_

crc_

inde

c_cr

c_in

_en

8

dec_

crc_

rese

t

dec_

crc_

out

8

dec_

wr_

data

8de

c_w

r_en

dec_

fifo_

flush

dec_

crc_

valid

REGISTER BUS

MASTER

reg_cs

reg_rd_en

reg_rd_data8

3

dec_frame_okdec_typedec_addr

dec_rd_data 8

reg_bus_error

dec_len

dec_rd_valid

reg_addr

reg_wr_en

reg_wr_data 8

5

enc_type

enc_len

controller_rd_reqtick_rd_req

8

8

8

8

8

enc_wr_dataenc_wr_en

8

enc_frame_done

enc_frame_ok

enc_addr 8

dec_frame_done

reg_rd_valid

dec_rd_enFIFOfifo_error

CRC

REG

ISTE

R B

US

MESSAGE_ENC +FIFO

TX PATH – detailed view

TX UART_ TRANSMITTER

tx_data

tx_valid

8

tx_ackMESSAGE

_ENC

enc_

crc_

inen

c_cr

c_in

_en

8 enc_

crc_

rese

t

enc_

crc_

out

8

enc_

rd_d

ata

8 enc_

rd_v

alid

enc_error

enc_

rd_e

nen

c_cr

c_va

lid

CRC

FIFOfifo_errorREGISTER

BUS MASTER

reg_cs

reg_rd_en

reg_rd_data8

3

reg_bus_error

reg_addr

reg_wr_en

reg_wr_data 8

5

enc_type

enc_len

controller_rd_reqtick_rd_req

8

8

enc_wr_dataenc_wr_en

8

enc_frame_done

enc_frame_ok

enc_addr 8

reg_rd_valid

REG

ISTE

R B

USMESSAGE_

DEC +FIFO

dec_frame_okdec_typedec_addr

dec_rd_data 8

dec_len

dec_rd_valid

8

8

8

dec_frame_done

dec_rd_en

CONTROLLER MODULE– detailed view

reg_cs

reg_rd_en

reg_rd_data8

reg_addr

reg_wr_en

reg_wr_data8

5

reg_rd_valid

REGISTER_INTERFACE

CONTROLLERint_rst

controller_rd_reqblk_errors

status

error_handling_cfg

REG

ISTE

R B

US

ext_rst RST BLOCKsys_rst

lock

ext_clkPLL

sys_clk

CONTROLLER_MODULE

host_command

ARBITER MODULE– detailed view

arbiter_tickARBITER_

COMPONENTgrants4

ext_requests 4

grant_switch TICK_GENERATOR

tick_rd_req

REGISTER_INTERFACE

weights32

arb_tick_valuesmsg_tick_values

internal_requests4

mode8

GRANT_HISTORYgrants

history_vector4

external_requests 4

FILTER

ARBITER_MODULE

reg_cs

reg_rd_en

reg_rd_data8

reg_addr

reg_wr_en

reg_wr_data8

5

reg_rd_valid

REG

ISTE

R B

US

MUXING

req 4

Arbitration FSM

NO_GRANT

sys_rst = ’0' ||arbiter_en = ‘0’

1

2

4

3

Req(1) = ‘1’

Req(1) = ‘0’ &Req(2) = ‘1’

Req(1) = ‘0’ &Req(2) = ‘0’ &Req(3) = ‘1’

Req(1) = ‘0’ &Req(2) = ‘0’ &Req(3) = ‘0’ &Req(4) = ‘1’

sys_rst = ’0' ||arbiter_en = ‘0’ ||

OR(Req) = ‘0’A

B

C D

E

Arbitration FSM

NO_GRANT

1

2

4

3

Sys_rst = ‘0’ ||Arbiter_en = ‘0’ ||

OR(Req) = ‘0’

Keep_client = ‘0’ &Req(2) = ‘1’

Keep_client = ‘0’ &Req(2) = ‘0’ &Req(3) = ‘1’

Keep_client = ‘0’ &Req(2) = ‘0’ &Req(3) = ‘0’ &Req(4) = ‘1’

Keep_client = ‘1’

A

B

C

D

E

Arbitration FSM

NO_GRANT

1

2

4

3


OR(Req) = ‘0’





A

B

C

D

E

Arbitration FSMNO_GRANT

1

2

4

3


OR(Req) = ‘0’





A

B

CD

E

Arbitration FSM

NO_GRANT

1

2

4

3


OR(Req) = ‘0’


Keep_client = ‘0’ &Req(1) = ‘0’ &Req(2) = ‘1’ Keep_client = ‘0’ &

Req(1) = ‘0’ &Req(2) = ‘0’ &Req(3) = ‘1’


A

BC

D E

Arbitration - wave

• Tick time: every 5 clocks• Weights:

• Filtered requests

4 3 2 1 Client

17 20 1 3 Weight

sys_clk

arb_tick

arb_state 0 1 2 3 1

requests 0111 0011

5 x sys_clk

3 x arb_ticks 1 x arb_ticks

arbiter_en

keep_client

Arbiter features

• External/ internal request muxing• Grant history tracking• Status message initiation

TestabilityTested modules:

• RX Path• TX Path• Controller and Peripherals• Arbiter module• Top

Simulation environment

ModuleTest Bench

Module under test

Input file

Output Log

ArbitrationGolden Model

REG BUS Model

Host Model


Input file:


Output Log:

Test Plan (Arbiter Module)• Reset and registers test• Steady state arbitration test• Dynamic arbitration test• Mode test• Filter test• Configuration switch test• Random arbitration test• Functional test

Schedule

ID Task Name Start Finish Duration 2010 2011 2010 2011

27/212/12 16/121/11 19/12 26/1228/11 2/15/12 20/223/1 30/1

1 0w16/11/201016/11/2010Determining Specifications

6 3w06/12/201016/11/2010Conceptual design

9 14w01/03/201124/11/2010VHDL implementation

10 9.57w01/04/201125/01/2011Verification

12 2w19/04/201105/04/2011Real time testing

2 0w16/11/201016/11/2010Architecture chracterization

11 .5w05/04/201102/04/2011Synthesis

3 2.71w30/12/201012/12/2010

4 .57w15/12/201012/12/2010

2011

9/1 13/26/2

8 0w11/01/201111/01/2011Mid-term presentation

7 1w07/01/201101/01/2011Writing mid-term presentation

13 1w14/04/201108/04/2011Writing final presentation

14 0w19/04/201119/04/2011Final presentation

5 4.29w22/02/201124/01/2011)(

6/3 13/3 20/3 27/3

2011

3/4 10/4 17/4

Documents

WRR ARBITER Mid-term Presentation