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Writing Engineering Abstracts(1)
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:(+)
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(1 of 2)(+) Consumer demand for hard discbandwidth has
significantly increased in recent years owing tothe large size of
files and increased disc size. However, theconventional interface
for hard discs cannot easily support sucha high bandwidth and
demands many pin counts to comply with
such a requirement. Therefore, this work describes anovel
connecting interface for hard discs for supporting up to 150MHz
bandwidth requirements and minimizing the number of pinsto four.
This novel connecting interface with serialtransmitting and
receiving lines is used to facilitatecommunication between the
system and hard disc. The serial
interfaces are then used to eliminate the cross talk
betweentransmitted and received data, discovered in
conventionalinterfaces, and could easily support bandwidths of up
to 150MHz. Next, the minimal pin requirement is satisfied using
theserial interfaces.
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(2 of 2)Analytical results indicate that the novelserial
interface can facilitate robust communicationbetween system and
hard disc and easily support up to 150MHz bandwidth requirements.
Moreover, the proposed interface can allow chipset
vendors to integrate more functions into one chip than theydid
before. In addition to making a high performance harddisc
commercially feasible, the proposed interface can beeasily upgraded
in the future.
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(1 of 2) (+ ) In h igh-speed opt ica lcommunications, the clock
and data recovery (CDR) circuit islargely responsible for recovery
of the clock used to sample thedata bits. The signal stream in
point-to-point communicationsystems such as SONET is continuous;
otherwise, during the
idle time, some synchronization bits are transmitted to
maintainthe bit-level synchronization between the transmitter and
thereceiver. In these systems, CDR based on Phase Lock Loop(PLL)
design is widely recognized as the optimal solution. PLL-based CDR
has been increasingly studied to remain apace ofhigher data rate
system requirements. Time division multiplexing
(TDM) passive optical network (PON) is a promising means
ofresolving bottlenecks in broadband access. Among thestandards
specified and the most widely accepted ones includeEthernet PON and
Gigabit PON standardized by IEEE and ITUT-T, respectively. In these
TDM PON systems, the upstream trafficaggregating to the optical
line terminal consists of bursts from
various optical network units.
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(2 of 2)Therefore, recovering a clock in a relatively short time
toincrease efficiency is problematic given that the burst length
inconventional PON systems is no longer than thousands of
bits.Applying the conventionally adopted PLL CDR to PON systemsis
also problematic given its relatively long recovery time.
Therefore, this work presents a novel CDR scheme, capable
ofrecovering a clock efficiently to increase the pocket efficiency
ofPON systems. A hybrid phase and delay lock looparchitecture is
derived, consisting of a VCO, voltage controlleddelay line, phase
detector, charge pump and low pass filter.HSPICE is then simulated.
Next, a prototype is designed to
demonstrate the effectiveness of the CDR scheme. Analysis
results indicate that the proposed monolithicscheme can acquire the
sampling phase well within 50 ns in a2.5 Gbps system such as PON.
Inaddition to averting frequency jittering greater than 6MHz,
i.e.4800ppm, the proposed CDR scheme can facilitate a more
aggressive design, with an even lower loop gain.
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Further details can be found at
http://www.chineseowl.idv.tw
http://www.chineseowl.idv.tw/http://www.chineseowl.idv.tw/
