IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 11, NOVEMBER 1979 1853

cycle of the PMOS shift register. Using this scheme, fourteen parallel samples are available every clock cycle. The maximum shift register clock rate is 5 MHz resulting in an access time (in- tegration time) of 2 ps . To obtain large charge-handling capac- ity, the size of a photodiode pixel is 12 pm by 360 pm. Dark current, however, is not a problem because of the short inte- gration time. The pixel elements are masked by an aperture shield to 20 pm to avoid spurious response due to scattered and reflected light from the optical waveguide. The dynamic range, defined here as the ratio of maximum charge-handing capacity to rms noise electrons with an SNR equal to one, is 50 dB. Pixel-to-pixel electrical crosstalk is minimized by fabri- cating the photodiodes in an isolation tub. In this way, pho- tons absorbed below the tub-substrate junction depth are not collected as signal. The resulting effect is a decrease in quan- tum efficiency but an increase in pixel-to-pixel isolation.

The sensor chip is mechanically butt-coupled at an angle to the edge of the lithium niobate substrate. This technique is used rather than normal incidence butt coupling to minimize spurious signals due to reentrant light reflected from the sur- faces of the photodiode array. The array is antireflection coated using layers of SiSN4 and Si02. However, substantial light can be reflected from the sensor because of the nonplanar structure of the photodiodes.

WP-A1 Redistribution of Chromium Upon Post-Implant An- nealing of Selenium-Implanted GaAs-C. A. Evans, Jr., and V. R. Deline, Charles Evans and Associates, San Mateo, CA 94402, T. W. Sigmon, Standard Electronics Laboratory, Stan- ford University, Stanford, CA 94305, and Alexander Lidow, International Rectifier Corporation, El Segundo, CA 90245.

Direct ion implantation of GaAs semi-insulating substrates has been the goal of a variety of researchers. This capability would provide better control of the channel behavior and eliminate time-consuming epitaxial growth and etching proce- dures. The major limitation of direct ion implantation is that high-temperature annealing is required in order to provide re- growth of the damaged material as well as to place the dopant on electrically active sites. Under these conditions, there has been uncontrolled-type conversion of substrate material and the production of anomalous electrical profiles which do not correspond to the expected as-implanted atomic profile. In a previous study, we reported on the atomic profiles of Se- implanted GaAs as a function of substrate temperature and post implant annealing using secondary ion mass spectrometry to provide the atomic profiles. It was speculated at that time that the observed difference between the atomic and electri- cally active profiles is related to the damage distribution as well as to the Cr distribution following the anneal.

With the recent availability of high-sensitivity SIMS instru- mentation, we have initiated a detailed study of the Cr distri- bution in thermally processed, Se-implanted GaAs. Using a I X 1015 at . cm2 Se implant into room temperature, 77 K, 500' GaAs substrates, we have found that indeed Cr does re- distribute upon thermal processing. As an intermediate anneal- ing stage, the Cr getters into the R, + AR, residual damage. This stage is followed by gettering into the near-surface region upon extended annealing. We propose that this latter stage of redistribution results from encapsulant stress-induced gettering. It is the conclusion of this study that the irreproducibilities of electrical behavior from laboratory to laboratory, the produc- tion of type conversion in annealed GaAs, and the apparent higher performance of hot substrate implants result from these redistribution behaviors.

WP-A2 Effects of Cr Redistribution on Device Characteristics in Ion-Implanted GaAs IC's Fabricated with Semi-Insulating GaAsl-P. Asbeck, J . Tandon, E. Babcock, and B. Welch, Rock- well International/Electronics Research Center, Thousand Oaks, CA 91360, and C. A. Evans, Jr., and V. R. Deline, Charles Evans and Associates, San Mateo, CA 94402.

It is shown with SIMS measurements that significant diffu- sion of Cr occurs when semi-insulating GaAs substrates are capped with reactively sputtered Si3N4 and annealed at tem- peratures required for the activation of ion-implanted layers. The resulting Cr profiles are consistent with a simple diffusion model with D lo-" cm2/s at 85OOC. Electrical measure- ments indicate that in a number of samples of semi-insulating GaAs, an n-type layer is formed in such an anneal, which may impair device isolation in a variety of planar GaAs integrated- circuit designs. Carrier-density profiles measured in these n- type layers correlate well with the results expected from the Cr motion. When FET's are fabricated using such semi- insulating GaAs substrates by direct ion-implantation, the devices display anomalously high values of pinchoff voltage and drain saturation current. In these cases, carrier-density profiles measured for the channel implant display an added component which may be understood on the basis of Cr diffusion.

A model is presented to explain the behavior of different substrates based on the relationship between the bulk Cr con- centration of the material and its residual donor concentra: tion. Several possible causes for the observed Cr migration are discussed. Experiments suggest that in addition to Cr deple- tion, other mechanisms may contribute to the added carrier density in some samples.

'This work was partially supported by the Advanced Research Pro- jects Agency of the Department of Defense and was monitored by the Air Force Office of Scientific Research under Contract F49620-77-C- 0087.

WP-A3 The Use of Si3N4 for GaAs Surface Passivation: Electrical Characteristics and Applications to Enhancement- Type MISFET's-B. Bayraktaroglu, W. M. Theis, and F. L. Schuermeyer, Air Force Avionics Laboratory, WPAFB, OH 45433.

In this paper we report on a new technique for the passiva- tion of GaAs and first encouraging results on the enhancement- type MISFET's produced using this technique. Instead of the commonly employed native oxide approach we have used low- oxygen content plasma-enhanced-deposited Si3N4 layers on relatively oxygen-free GaAs surfaces to achieve passivation. The insulator films always had < 1 at % oxygen and with proper surface treatment the oxygen content at the interface was also kept below 1 at %. Samples produced in this manner showed superior electrical characteristics compared to those containing more oxygen (>5 at %) at the interface.

We have used the variable frequency C-V, C-V, and transient photopulse techniques to characterize the interfacial proper- ties. The frequency response of the C-V curves of MIS devices produced on n-type GaAs was consistent with "freezing-out'' of surface states giving high-frequency curves for f> 500 kHz. G p / w versus log w plots were used to estimate the surface- state densities from mid-gap to the conduction-band minimum, The density of states was found to be of the order of 1O'O cm-2 . eV-' near the mid-gap increasing to 10'l cm-2 . eV-' range towards the conduction band edge. With the use of transient photopulse techniques, the variation of the surface