WMC8 – Thessaloniki, Greece Some Applications of Spiking Neural P Systems Mihai Ionescu 1 & Dragoş Sburlan 2 1 URV, Research Group on Mathematical Linguistics,

WMC8 – Thessaloniki, Greece

Some Applications of Spiking Neural P Systems

Mihai Ionescu1 & Dragoş Sburlan2

1 URV, Research Group on Mathematical Linguistics, Spain 2 Ovidius University, Faculty of Mathematics and Informatics, Romania


Outline

1. On Spiking Neural P Systems Definition. Example. Exhaustive use of the rules. Example.

2. Simulating Logical Gates and Circuits NOT gate Example of a circuit

3. A Sorting Algorithm Example


Definition1:

Π = (O, σ1, …, σm, syn, i0)

where:

1. O = { a } (the alphabet of objects contains only one object);

1. On Spiking Neural P Systems

2. σ1, …, σm are neurons, identified by tuples σi = (ni,Ri), 1 ≤ i ≤ m, where:

a) ni ≥ 0

a2 a

1 M. Ionescu, Gh. Paun, T. Yokomori, Spiking Neural P Systems, Fundamenta Informaticae, 71, 2-3(2006), 279-308.


a2 ab) Ri is a finite set of rules:

(1) E/ar → a; t, where E

is a regular expresion over O, r ≥ 1,

t ≥ 0;

(2) as → λ, for some

s ≥ 1, as ∉ L(E) for any rule of

type (1) from Ri

a2->a;0 (aa)*/a3->a;1

a->a;0

a2->λ


Definition (continued):Π = (O, σ1, …, σm, syn, i0)

...


a2 a


a2->a; 0 (aa)*/a3->a;1

a->a;0

a2->λ

Definition (continued):Π = (O, σ1, …, σm, syn, i0)

...

c) syn ⊆ {1, 2, … m} x {1, 2, … m}, with (i,i) ∉ syn, for 1≤ i ≤ m;

d) i0 € {1, 2, … m} indicates the output neuron

Spik2Pm(ruled, consp, forgq)


Example – Initial Configuration

a2

a2 → a;0 a → λ

a2

a2 → a;0 a2 → a;1

a2

a2 → a;0 a → λ

a2

a2 → a;0 a3 → λ

1

2

3

4



Example – Step 1 – used rules

SPIKE

a2

a2 → a;0 a → λ

a2

a2 → a;0 a2 → a;1

a2

a2 → a;0 a → λ

a2

a2 → a;0 a3 → λ

1

2

3

4



Example – Step 1 – result

a2a3

a2 → a;0 a → λ

a1a2

a2 → a;0 a2 → a;1

a1a3

a2 → a;0 a → λ

a1a2a3

a2 → a;0 a3 → λ

1

2

3

4




a2

a2 → a;0 a → λ

a2

a2 → a;0 a2 → a;1

a2

a2 → a;0 a → λ

a3

a2 → a;0 a3 → λ

1

2

3

4




a2

a2 → a;0 a → λ

a2 → a;0 a2 → a;1

a1

a2 → a;0 a → λ

a1a2

a2 → a;0 a3 → λ

1

2

3

4




SPIKE

aa2 → a;0

a → λ

a2 → a;0 a2 → a;1

aa2 → a;0

a → λ

a2

a2 → a;0 a3 → λ

1

2

3

4




a3

a2 → a;0 a → λ

a2 → a;0 a2 → a;1

a3

a2 → a;0 a → λ

a3

a2 → a;0 a3 → λ

1

2

3

4

3-1 = 2



Results:

NFIN = Spik2P1(rule*, cons1, forg0) = Spik2P1(rule*, cons*, forg*) = Spik2P2(rule*, cons*, forg*)

Spik2P*(rulek, consp, forgq) = NRE, for all k ≥ 2, p ≥ 3, q ≥ 3.

SLIN1 = Spik2P*(rulek, consp, forgq, bounds), for all k ≥ 3, p ≥ 3, q ≥ 3, and s ≥ 3

1. Spiking Neural P Systems


Exhaustive use of the rules. Example

a5

a(aa)*/a → a;0a(aa)*/a2 → a;0




a5

a(aa)*/a → a;0a(aa)*/a2 → a;0




a(aa)*/a → a;0a(aa)*/a2 → a;0


a5



a5

a(aa)*/a → a;0a(aa)*/a2 → a;0




a

a(aa)*/a → a;0a(aa)*/a2 → a;0


a2


2. Simulating Logical Gates and Circuits

Codification:

– Boolean value 1 : aa– Boolean value 0 : a



NOT Gate:

aa2/a → a;0

a3 → a;0

1

a/a → a;0 a2/a2 → a;0

2



NOT Gate: 1→0

aaaa2/a → a;0

a3 → a;0

1

a/a → a;0 a2/a2 → a;0

2



NOT Gate: 1→0

a2/a → a;0 a3 → a;0

1a

a/a → a;0 a2/a2 → a;0

2

a



NOT Gate: 0→1

aaa2/a → a;0

a3 → a;0

1

a/a → a;0 a2/a2 → a;0

2



NOT Gate: 0→1

a2/a → a;0 a3 → a;0

1aa

a/a → a;0 a2/a2 → a;0

2

aa



Lemma 1:– Boolean AND gate can be simulated by SN P systems

using one neuron and no delay on the rules, in one step.

Lemma 2:– Boolean OR gate can be simulated by SN P systems using

one neuron and no delay on the rules, in one step.

Lemma 3:– Boolean NOT gate can be simulated by SNP systems using

two neurons, no delay on the rules, in two steps.



Circuits.Example:

f:{0,1}4 → {0,1}

f(x1,x2,x3,x4)=(x1 Λ x2) V ¬(x3 Λ x4)



Circuits.Example:f:{0,1}4 → {0,1}

f(x1,x2,x3,x4)=(x1 Λ x2) V ¬(x3 Λ x4)

AND AND




f(x1,x2,x3,x4)=(x1 Λ x2) V ¬(x3 Λ x4)

AND AND

NOT




f(x1,x2,x3,x4)=(x1 Λ x2) V ¬(x3 Λ x4)

AND AND

NOTSYNC




f(x1,x2,x3,x4)=(x1 Λ x2) V ¬(x3 Λ x4)

AND AND

NOTSYNC

OR



Circuits.Example:

AND AND

NOTSYNC

OR



Theorem:

Every Boolean circuit α, whose underlying graph structure is a rooted tree, can be simulated by a SN P system, Πα, in linear time. Πα is constructed from SN P systems of type ΠAND, ΠOR and ΠNOT, by reproducing in the architecture of the neural structure, the structure of the tree associated to the circuit.


2. Simulating Logical Gates and Circuits – Further Ideas

Arbitrary circuits, hence not necessary rooted tree.


3. A (Simple) Sorting Algorithm

Example. 1,3,2 Initial configuration

a*/a→a;0 a*/a→a;0

a3→a;0a2→λa→λ

a*/a→a;0


a→a;0a2→λa3→λ

a a3 a2



Example. 1,3,2 Step 1

a*/a→a;0 a*/a→a;0


a*/a→a;0



a2 a

a3 a3 a3




a*/a→a;0 a*/a→a;0


a*/a→a;0



a

a2 a2 a2

a a a




a*/a→a;0 a*/a→a;0


a*/a→a;0



a a a

a a2 a2




a*/a→a;0 a*/a→a;0


a*/a→a;0



a a2 a3




a*/a→a;0 a*/a→a;0


a*/a→a;0



a a2 a3


2. A Sorting Algorithm

Theorem:SN P systems can sort a vector of natural numbers where each number is given as number of spikes introduced in the neural structure.

Remarks:

- time complexity: O(T), T is the magnitude of the numbers to be sorted - Further research: magnitude, improvements of time complexity,

number of neurons


Thank You !

Documents

WMC8 – Thessaloniki, Greece Some Applications of Spiking Neural P Systems Mihai Ionescu 1 & Dragoş Sburlan 2 1 URV, Research Group on Mathematical Linguistics,