WINSEM2015-16_CP1436_TB01_ECE301_VLSI_System_Design_lab_new.pdf

7/25/2019 WINSEM2015-16_CP1436_TB01_ECE301_VLSI_System_Design_lab_new.pdf

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VITU N I V E R S I T Y

(Estd. u/s 3 of UGC Act 1956)

SCHOOL OF ELECTRONICS ENGINEERING

B.Tech Electronics and Communication Engineering

ECE301 VLSI System Design Lab

Laboratory Reference Material

Compiled By

Prof. Jagannadha Naidu K

Asst. Prof.(Sr.)

SENSE

VIT University.


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List of Tasks:

Sl. No Name of the Task Reference

1 V - I Characteristics of PMOS and NMOS T1

Short Channel and Body effect of a N-MOSFET T1

2

Analysis of switching characteristics and power

consumption of a CMOS inverterT1

3

Analysis and design of CMOS NAND and NOR gates

(Complex CMOS gates)T1

CMOS implementation of a Boolean Expression

(optional)T1

4 Design an inverter chain to drive off-chip loads T1

5 Physical design and verification of Digital cells T1

6 D flip-flop setup and hold timing analysis T1


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Linux Basic Commands

mkdir directoryname--Creates a new directory.

cd xyz--Change directory to xyz

cp destination source --Copy files from source to destination

cp -r sourcefile targetfile --Copies recursively (includes subdirectories)

rm file--Removes file

rmr sourcefile-- Deletes recursively (includes subdirectories)

rmdir directoryname--Deletes the specified directory, provided it is already empty.

locate file1--A fast database driven file locator

find--The find command allows you to search for a file in a given directory

ls --List files

lsla-- List files with properties

pwd --Show the name of the current working directory


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Task No:1 Date:

VI Characteristics of PMOS and NMOSAim:

To plot the V-I characteristics of NMOS and PMOS transistors. Determine the region of

operation for the MOSFET. Calculate its threshold voltage and pinch-off voltage.

Tool:Cadence Virtuoso , ADE

Schematic diagram:

NMOS:

Fig1.

PMOS

Fig2.


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Procedure:

1. Invoke the Cadence Virtuoso2. Draw the schematic as shown in the Fig1 for NMOS and Fig2 for PMOS.

3. Invoke ADE XL for device simulation.

4.

Perform DC analysis and plot the transfer characteristics and outputcharacteristics.

Model graph:

NMOS IdsVs Vds

NMOS IdsVs Vgs


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PMOS IdsVs Vds

PMOS Ids Vs Vgs


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Calculation: (NMOS & PMOS)

Threshold Voltage = (measured from the graph)

Pinch-off Voltage= (measured from the graph)

Result and Inference


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Task No.:1(a) Date:

Short Channel and Body effect of a N-MOSFET

Aim:

To find the channel length modulation co-efficient ()and observe body bias effect

of N-Channel MOSFET.

Tool:

Cadence Virtuoso, ADE

Schematic diagram:

Channel length modulation:

Fig.1

Procedure:

Channel length modulation co-efficient:

1. Invoke Virtuoso

2. Draw the schematic of the Fig1.

3.

Invoke ADE for device simulation.4. Perform DC analysis, sweep the source drain voltage (Vds) from 0-1.8V and plot

the output current (ID).

5. Note down two values of ID1and ID2for two arbitrary values (Vds1and Vds2) ofVds in saturation region.

6. Calculate the Channel length modulation co-efficient () using the formula


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D2

D1

I

I=

2

DS1

1

1

DSV

V

7. Plot the output characteristics IdsVs Vgs, for different body bias voltage.

Model Graph:

Channel Length Modulation

Calculation:Calculate channel length modulation co efficient

Different Vthvalues for different VSB

Result and Inference:

ID1

ID2

VDS1 VDS2


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Task No:2 Date:

Analysis of Switching Characteristics and power consumption of a

CMOS Inverter

Aim:To determine the Voltage Transfer Characteristics (VTC) of CMOS inverter and measurenoise margin, propagation delay and power consumption.

Tool:

Cadence Virtuoso, ADE

Voltage Transfer Characteristics:

Circuit Diagram:

Fig.1


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Model Graph:

Voltage Transfer Characteristics:

Fig.2a

Gain Plot: (dvout/dvin)

Fig.2b

Procedure:

1) Invoke the Cadence Virtuoso

2) Draw the schematic of the CMOS inverter.

3) Invoke ADE XL for device simulation.


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4) Perform DC analysis, plot Voltage Transfer Characteristics.

5) Observe the voltage transfer characteristics of the inverter, for different aspect

ratio(W/L)

Calculation of Noise Margin:

1) From Fig2.b, find out VILand VIH(these are the operational points of the inverter

where dVout/dVin = -1).

2) Noise Margin High (NMH) = VOH(min)- VIH(min)where VOHis the minimum outputvoltage for logic high.

3) Noise Margin Low (NML) = VIL(max)VOL(max)where VOLis the maximum output

voltage for logic low.

Transient Analysis:

Circuit Diagram:


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Model Graph:

Procedure:

1) Perform Transient analysis and plot the output.

2) Plot .pwr signals at required nodes .

Calculation of Propagation Delay and Power Dissipation:

1) TP = ( TPLH + TPHL) / 2

Where

TPHL: Time delay between 50% transition of the raising input voltage and 50%

transition of falling output voltage.

TPLH: Time delay between 50% transition of the falling input voltage and 50%

transition of raising output voltage.

2) Calculate total power consumption.



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Task No:3 Date:

Analysis and design of CMOS NAND and NOR gates

Aim:

To examine the transient and DC Characteristics of CMOS NAND & NOR Gates fordifferent input transitions. Determine the propagation delays and power dissipationassociated with different input transitions.

Tool:

Cadence Virtuoso, ADE.

Schematic Diagram :

NAND Gate:

Output BAF .

Circuit DiagramInputs Output

A B F

0 0 1

0 1 1

1 0 1

1 1 0


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NOR Gate:

Output BAF

Circuit Diagram

Procedure:

1. Invoke the cadence Virtuoso

2. Draw the schematic of the CMOS NAND and NOR circuits

3. Invoke ADE for device simulation.4. Perform DC analysis and plot the transfer characteristics for different input

transitions as shown in model graph.

5. Perform the Transient analysis and calculate propagation delay of the circuit

Inputs Outputs

A B F0 0 1

0 1 0

1 0 0

1 1 0


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Model Graph

DC Characteristics:

NAND Gate:

NOR Gate:


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Transient Analysis:

Timing Diagram for NAND Gate:

Timing Diagram for NOR Gate:


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Tabulation:

NAND Gate:

NOR Gate:



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Task No:3(a) Date:

CMOS implementation of a Boolean Expression

Aim:

To implement a CMOS circuit for the given expression BACBAY .. and verifyits functionality.

Tool:Cadence Virtuoso, ADE.

Truth Table:

Input Output

A B C Y

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0


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Circuit Diagram:

Fig.1

Procedure:

1. Invoke the Cadence Virtuoso.

2. Draw the schematic of the Circuit shown in Fig.1.3. Invoke the Cadence ADE for device simulation.

4. Perform Transient analysis.

5. Verify the functionality of the circuit for the different input combinations.


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Model Graph:


V(A)

V(B)

V(C)

V(Y)


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Task No:4 Date:

Designing an inverter chain to drive off-chip loads

AIM:

To minimize the delay through an inverter chain


Circuit Diagram:

Fig.1

Procedure:

1. Invoke the Cadence Virtuoso.

2. Draw the schematic of the Circuit shown in Fig.1.3. Invoke the Cadence ADE for device simulation.

4.

Perform Transient analysis.5. Verify the functionality and calculate the delay.

Calculation:

If CLis given

How should the inverters be sized?

How many stages are needed to minimize the delay?

Design Challenges

Keep signal rise times < gate propagation delays.

good for performance and power consumption


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Keeping rise and fall times of the signals of approximately equal values

Determine the min. propagation delay.

Determine the number of inverters N.

What are the gate widths of each inverter in the chain?

Results and Inference:


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Task No:5 Date:

Physical Design of Digital Cells

AIM:

To use Cadence Virtuoso to create a CMOS layout for inverter, NAND and NOR.

a) Do pre-layout simulations using Spectre.

b) Layout a circuit using Cadence Virtuoso.

c) Use the Design Rule Checker to check for errors in the layout.

d) Perform extraction on the layout and use the Layout Vs. Schematic tool to verify thatthe layout matches the circuit schematic.

e) Use the extracted netlist of the layout to perform post-layout simulation.


Circuit Diagram

Inverter Schematic

Fig.1


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Inverter Layout

Fig.2

Procedure:

1. Invoke the Cadence Virtuoso.2. Draw the schematic of the Circuit shown in Fig.1.

3. Invoke the Cadence ADE for device simulation.

4. Perform Transient analysis.


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5. Verify the functionality and calculate the delay.

6. Invoke the Cadence Virtuoso Layout editor.

7. Draw the layout of the circuit shown in Fig.1.

8. Run the Design Rule Checker and make sure that you are not violating anyprocess design rules

9.

Check Layout Vs. Schematic (LVS)10.Extract the design, that generates a netlist based layout, including any parasiticcapacitances, and resistances.

11.Post-Layout Simulation With Spectre

Calculation of Propagation Delay and Power Dissipation:

1)TP = ( TPLH + TPHL) / 2

2) Calculate total power consumption.



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Task No:6 Date:

D flip-flop setup and hold timing analysis

Aim:

To implement a CMOS circuit for D-flip flop and perform the timing analysis andcalculate setup time and hold time.


Circuit Diagram:

Model Graph:


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Procedure:

1) Invoke the Cadence Virtuoso.2) Draw the schematic of the D-flip flop.

3) Invoke the Cadence ADE for device simulation.

4)

Perform Transient analysis.5) Plot the waveforms for input CLK (clock), D (input), Q (output) and observe the

waveforms and calculate the setup time and hold time.


1. Setup time of D flip flop = _________

2. Hold Time of D flip flop = _________

3. Clock to Q delay of D flip flop = ____

Output of the flip flop will be metastable state if setup and hold time of flip flop is not

met.

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WINSEM2015-16_CP1436_TB01_ECE301_VLSI_System_Design_lab_new.pdf