WILDSTAR A5 for VPX - Intel · Unless specifically indicated otherwise, references throughout this manual to “WILDSTAR A5 for Open-VPX” pertain to both the WILDSTAR A5 2PE for

WILDSTAR A5 for OpenVPX Hardware Reference Manual

Document No:15080-0000, Revision 3.0

Revision History

© Copyright 2014-2015 by Annapolis Micro Systems, Inc. All rights reserved. Printed and published in the United States of America. WILDFIRE, WILDFIRE-XL, WILDCHILD, WILDFORCE, WILDFORCE-XL, WILD-ONE, WILD-ONE-XL, WILDTIME, WILDCARD, WILDSTARFIRE, WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4/5/6/7, WILDSTAR A, WILDSTAR-E, WSDP, WILDWARE, WILD, C2WILD, CoreFire, and FIREBIRD are trademarks of Annapolis Micro Systems, Inc. All other trademarks and registered trademarks are owned by their respective owners. Patents Pending.

Release Date Version Edits Initial

July 7, 2015 2.8

• Updated Board Identification Numbers section.

• Updated Serial Board Configuration Utility

• Updated OpenVPX Flash Utility

• Added OpenVPX Board Restore Procedure

• Added OpenVPX Disk Sanitization Procedure

AML

October 7, 2015 3.0 • Added Security Enhanced Linux AML

This is the standard Annapolis Micro Systems, Inc. Shrink Wrap license which covers all Annapolis Hardware, VHDL Drivers, APIs, Examples, and Reference Designs. CoreFire Next is covered by a different shrinkwrap license.

If this license is included in a purchase order, it supersedes any and all other Terms and Conditions regarding licensing and technical rights that are found in the Purchase Order.

ANNAPOLIS MICRO SYSTEMS, INC. - LICENSE AGREEMENT

WILDSTAR, WILDSTAR-II, WILDSTAR-II PRO, WILDSTAR 4, WILDSTAR 5, WILDSTAR 6, WILDSTAR , WILDSTAR 5B, and WILDSTAR A5 Host Software, Device Drivers, Models, VHDL, Examples, Tools and PCI and FPGA-based Ethernet Controllers are supplied with a License Agreement. This License Agreement also covers the PLD designs, Reference designs, and Flash contents supplied with the board. Do not install or use this product and/or break the seal on the CD-ROM until you have read and agreed to the following terms and conditions. Should you choose not to be bound by the terms and conditions of this agreement, you should promptly return this product.

YOU ARE BOUND TO THE TERMS OF THIS AGREEMENT BY BREAKING THE SEAL ON THE CD-ROM

Under the terms of this License, you: • may make copies of the Licensed Product • may not transfer the Licensed Product to an unlicensed party • may modify the VHDL and the Examples • may not modify any other parts of the Licensed Product • may not decompile, reverse assemble or otherwise reverse engineer the Licensed Product • may run this product ONLY on an Annapolis Micro Systems, Inc. board• may run the FPGA vendor specific parts of this product ONLY on an Annapolis Micro Systems, Inc. board with FPGAs from that vendor

The Licensed Product is owned and copyrighted by Annapolis Micro Systems, Inc. You may not remove the copyright notice from the Licensed Product. You must use your best efforts to prevent any unauthorized copying of the Licensed Product.

The Licensed Product is provided “as is” without warranty of any kind including warranties for merchantability or fitness for a particular purpose. Annapolis Micro Systems, Inc. shall not be liable for any loss of profits, loss of use, interruption of business, nor for indirect, special, incidental or consequential damages of any kind whether under this agreement or otherwise.

Although Annapolis Micro Systems, Inc. does not warrant the functions contained in the Licensed Product, the medium on which the Licensed Product is furnished is warranted to be free from defects in materials and workmanship under normal use for a period of 90 days from date of delivery to you as evidenced by a copy of your receipt. Annapolis Micro Systems’ entire liability to you and your exclusive remedy shall be replacement of the Licensed Product if the medium on which the Licensed Product is furnished proves to be defective.

You understand that the Licensed Product may require a license from the US Department of Commerce or other government agency before it may be taken or sent outside of the United States. You agree to obtain any required licenses before taking or sending the Licensed Product out of the United States. You will not permit the re-export of the Licensed Product without obtaining required licenses or letter of further assurance.

Contents

Chapter 1: About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Key Words and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Chapter 2: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 About the WILDSTAR A5 for OpenVPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.1 WILDSTAR A5 2PE for OpenVPX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.2 WILDSTAR A5 3PE for OpenVPX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1.3 WILDSTAR A5 for OpenVPX Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 3: Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1 Unpacking and Inspecting the WILDSTAR A5 for OpenVPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.2 Board Illustrations and LED Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2.1 WILDSTAR A5 for OpenVPX Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2.1.1 Front Panel Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.2.1.1.1 HOT SWAP STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.2.1.1.2 STS: Board Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.2.1.1.2.1 Control Plane Status 283.2.1.1.2.2 Data Plane Status 283.2.1.1.2.3 Switch Status 283.2.1.1.3 FPGA User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2.1.2 Solder Side Debug Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2.2 WILDSTAR A5 for OpenVPX Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.2.2.1 DIP Switch Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.2.2.1.1 PCI Express Switch Configuration (REFDES: SW3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.2.2.1.2 Reserved Switches (REFDES: SW2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.2.2.1.3 PowerPC UART Selects (REFDES: SW4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2.2.1.4 MMC Configuration Selects (REFDES: SW1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Chapter 4: Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.1 WILDSTAR A5 for OpenVPX Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.2 WILDSTAR A5 for OpenVPX Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.3 Configure Backplane Slot Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.4 Power Up System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404.5 WILDSTAR A5 for OpenVPX Hot Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.5.1 WILDSTAR A5 for OpenVPX Hot Swap Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 5: Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.1 Board Identification Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 6: WILDSTAR A5 for OpenVPX Hardware Reference . . . . . . . . . . . . . . . . . . . 476.1 WILDSTAR A5 for OpenVPX Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.2 Thermal and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.2.1 WILDSTAR A5 for OpenVPX Heatsinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.2.2 Temperature Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516.3 Supported Backplane Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566.4.1 Front Panel Clock Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.4.1.1 Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 7: Host Module Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617.1 Host Module Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637.2 Host Module Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.2.1 PowerPC Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.2.2 VPX Maskable Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.2.3 VPX SYSRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.2.4 MMC Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647.3 Host Module MMC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Chapter 8: Serial Board Configuration Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Appedix A: WILDSTAR A5 and WILDSTAR 7 for OpenVPX 6U Backplane Pinout . . 75

Appedix B: OpenVPX Flash Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix C: Statement of Volatility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Appendix D: OpenVPX Board Restore Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Appendix E: OpenVPX Disk Sanitization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Appendix F: Security Enhanced Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

1WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 1: About This Manual

Chapter 1: About This Manual

2 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 1: About This Manual

15080-0000 Rev 3.0


This WILDSTAR A5 for OpenVPX Hardware Reference Manual is intended to help the user install, configure, and maintain the high performance product from Annapolis Micro Systems, Inc.

Note: Unless specifically indicated otherwise, references throughout this manual to “WILDSTAR A5 for Open-VPX” pertain to both the WILDSTAR A5 2PE for OpenVPX and the WILDSTAR A5 3PE for OpenVPX boards.

1.1 OverviewA brief description of each chapter appears below.

• Chapter 2: Introduction, discusses board architecture and performance features of the WILDSTAR A5 for OpenVPX.

• Chapter 3: Getting Started, describes unpacking and inspection procedures for your WILDSTAR A5 for OpenVPX, as well as LED and switch definitions and locations.

• Chapter 4: Installation describes host system requirements, installation instructions, reset options, and switch descriptions.

• Chapter 5: Technical Support provides information for contacting Annapolis Micro Systems, Inc. Technical Support.

• Chapter 6: WILDSTAR A5 for OpenVPX Hardware Reference describes hardware specifications, along with voltage, and clocking.

• Chapter 7: Host Module Reference contains information regarding the Host Module.

• Chapter 8: Serial Board Configuration Utility provides a means for configuring common settings of the baseboard operating system.

• Appendix A: WILDSTAR A5 and WILDSTAR 7 for OpenVPX 6U Backplane Pinout contains the WILDSTAR A5 for OpenVPX Backplane Pinout.

• Appendix B: OpenVPX Flash Utility provides information about the WILDSTAR A5 for OpenVPX Flash Utility.

• Appendix C: Statement of Volatility contains information regarding memory volatility for the WILDSTAR A5 for OpenVPX.

• Appendix D: OpenVPX Board Restore Procedure describes how to restore boards to a factory default configuration, or upgrade a board to a new baseboard software release.

• Appendix E: OpenVPX Disk Sanitization Procedure describes how to erase and sanitize the SSD and flash module.

• Appendix F: Security Enhanced Linux provides guidance on enabling and disabling SELinux on WILDSTAR A5 for OpenVPX boards.

15080-0000 Rev 3.0


1.2 ConventionsDifferent text styles are used throughout the manual to call attention to specific items:

1.3 Key Words and DefinitionsTerms used throughout the manual are defined below.

40GbE40 Gigabit Ethernet. Uses standard Ethernet XLAUI protocol (4 lanes @ 10.3 Gbps).

56GbE56 gigabit Ethernet. 40GbE protocol running at 14Gbps

Application Programming InterfaceA set of functions coded in the C language allowing communication between an application and the board.

BackplaneA board within a chassis providing an interconnection point for logic and control elements among multiple /WILDSTAR A5 for OpenVPX boards.

DDRDouble Data Rate. The DDR connection's signalling rate is 5Gbit/s in each direction per connection.

Differential Signal PairTwo lines, one negative and one positive.

Differential SignalingTwo-wire signaling, in which the difference in voltage between two wires is used to signal data.

DLLDynamic Linkage Library

DriverSoftware used to handle communication with one to four WILDSTAR A5 for OpenVPX boards.

Convention Description

Text represented as screen display

This typeface is used to represent displays appearing on the screen, such as at the “A:\” prompt.

Keys When specific keys are referenced, they are designated by their labels, such as “the Enter key” or “the Escape key,” or they may be shown as [Enter] or [Esc].When two or more keys are to be pressed simultaneously, the keys are linked with a plus sign (+). For example: [Ctrl] + [Alt] + [Del].

Clickable Links Text that references another area in the document. The user can click on the blue text and the document will jump directly to the section referenced.

15080-0000 Rev 3.0


DRAMDynamic Random Access Memory

External I/OExternal Input/Output

FDRFourteen Data Rate. FDR is 14.0625 Gbit/s per lane.

InfinibandA switched fabric communications link used in high-performance computing and enterprise data centers.

LaneA set of differential signal pairs, one pair for transmission and one pair for reception. A PCI Express by-N Link is composed of N Lanes.

MMCModular Management Controller

N/CNo Connection

OpenVPXOpenVPX is industry name for the VITA 65 specification. See VITA 65 for description.

PCI Express (PCIe)General performance I/O interconnect which maintains the fundamental attributes of PCI, but replaces the parallel bus implementation with a serial interface that offers new features and new levels of performance. It is available as Gen1 (2.5 Gbps), Gen2 (5 Gbps) or Gen3 (8 Gbps).

QDRQuad Data Rate. The QDR connection's signalling rate is 10Gbit/s in each direction per connection.

QSFPQuad Small Form-factor Pluggable. A compact, hot-pluggable transceiver used for data communications applications.

REF CLKReference clock for high speed serial I/O

RTMRear Transition Module.

RxAbbreviation of “Receive”.

Single-ended SignalingUses one wire per signal, in which a single voltage is generated that the receiver compares with a fixed reference voltage.

SSDSolid State Drive. A storage device made with flash memory and no moving parts.

15080-0000 Rev 3.0


SDRSingle Data Rate. The SDR connection's signalling rate is 2.5Gbit/s in each direction per connection.

Tx Abbreviation of “Transfer”.

UARTUser Asynchronous Receiver Transmitter

VITA 46The VITA 46 family of standards comprises this base standard defining physical features of compliant components in addition to a set of protocol layer standards which define specific serial or parallel interconnects used in a system implementation. VITA 46 defines a high speed connector that allows for high density, high bandwidth serial communication over a backplane.

VITA 65Open VPX. Based on the VPX family of standards, the OpenVPX standard uses module mechanical, connectors, thermal, communications protocols, utility, and power definitions provided by specific VPX standards and then describes a series of standard profiles that define slots, backplanes, modules, and Standard Development Chassis.

VPXVPX is industry name for the VITA 46 specification. See VITA 46 for description.

VPX Control Plane1Gbit Ethernet connection from each payload slot’s P4 connector to switch slot.

VPX Data PlaneHigh-speed serial connection on P1 backplane connector.

VPX Expansion PlaneHigh-speed serial connection on P2 backplane connector.

15080-0000 Rev 3.0

7WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 2: Introduction

Chapter 2: Introduction

8 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 2: Introduction

15080-0000 Rev 3.0


WILDSTAR A5 2PE and 3PE for OpenVPX boards will support either a small FPGA package with 36 Serial IO (I.e. 36SIO) or a larger package with 48 Serial IO (i.e. 48SIO). All cards will be hot swappable.

P1 is generally used for packetized protocols such as Infiniband, Ethernet or Serial RapidIO and will always go to the IOPE. Data can also be transferred over PCIe with PCIe backplane connections over P2. This card has flexible PCIe upstream port selection that allows the upstream port to be the on-board PPC, any P2 PCIe connection or select PCIe connections on P5. Based on the upstream port DIP switches, the PPC will automatically determine if it needs to be an endpoint or root complex on boot.

P3 is used for LVDS connections. There are 16 TX and 16 RX uni-directional LVDS connections and 8 single ended IO.

15080-0000 Rev 3.0


2.1 About the WILDSTAR A5 for OpenVPX

2.1.1 WILDSTAR A5 2PE for OpenVPX Architecture

Figure 2-1: WILDSTAR A5 2PE for OpenVPX Block Diagram

P3

Annapolis Micro Systems, Inc.Copyright 2012-13

IOPE0

AlteraStratix® V

F151736 SIO

GXA3*, GXA4*,GXA5*,

GSD4*, GSD5*

F193248 SIO

GXA7**, GXA9**, GXAB**,

GSD6**, GSD8**

64*/32**

DDR3 DRAM0**, 1GB**

P2P1

12*/16**

96

P0 P4

Utility Plane

DDR3 DRAM0**, 1GB**

DDR3 DRAM0, 1GB**, 2GB*

IOPE1

AlteraStratix® V

F151736 SIO

GXA3*, GXA4*,GXA5*,

GSD4*, GSD5*

F193248 SIO


GSD6**, GSD8**

Data Plane

ExpansionPlane

UserDefinedPlane

Control &User Def

Plane

0*/32**

APM86290PowerPCPCIe Switch

NOR Flash 16 MB

DRAM2GB

SSD4 GB

8

7*/11**

4

4

4

4

4444

88

48

12*/16**

96

8*/17**

RJ45

Micro USB

SMA

4

4

1

1

1 1 2

3UART

10/100/1000 BASE-T Ethernet

MMC

QSFP+QSFP+

QSFP+

Mezz 02nd Slot

Mezz 0

Mfg Options

OR

QSFP+QSFP+

QSFP+

Mezz 12nd Slot

Mezz 1

Mfg Options

OR

Pluggable Module

Manufacturing Option

JTAG

IRIG-B or

Front Panel Clk

UART

SignalTap USBSATA

IPMI

64*/32**


* = Only 36 SIO Board** = Only 48 SIO Board

0*/32**

64*/32**

DDR3 DRAM0**, 1GB**

DDR3 DRAM0**, 1GB**


0*/32**

64*/32**


0*/32**

8*/17**

0*/4**

0*/4**

P5

ExpPlane

6*/8**

6*/8**

6*/8**

6*/8**

G2 only

96

96

PCI ExpressUp to Gen3 (7 Gbytes/s per 8x connection)

Ethernet up to 1Gb

Differential Pairs

Single Ended

HiSpeed Serial IOXCVR speed 1 up to 14.1 Gbps (1.71 GBytes/s per lane)XCVR speed 2 up to 12.5 Gbps (1.52 GBytes/s per lane)

8

15080-0000 Rev 3.0


2.1.2 WILDSTAR A5 3PE for OpenVPX Architecture

Figure 2-2: WILDSTAR A5 3PE for OpenVPX Block Diagram

Annapolis Micro Systems, Inc.Copyright 2012-13

IOPE0

AlteraStratix® V

F151736 SIO

GXA3*, GXA4*,GXA5*, GSD4*,

GSD5*

F193248 SIO


GSD6**, GSD8**

64*/32**

DDR3 DRAM0**, 1GB**

P2P1

12*/16**

96

P0 P4 P5

Utility Plane

DDR3 DRAM0**, 1GB**


IOPE1

AlteraStratix® V

F151736 SIO

GXA3*, GXA4*,GXA5*,

GSD4*, GSD5*

F193248 SIO


GSD6**, GSD8**

CPE0

AlteraStratix® V

F151736 SIO

GXA3*, GXA4*,GXA5*,

GSD4*, GSD5*

F193248 SIO


GSD6**, GSD8**

Data Plane

ExpansionPlane

UserDefinedPlane

Control &User Def

Plane

ExpPlane

0*/32**

APM86290PowerPCPCIe Switch

NOR Flash 16 MB

DRAM2GB

SSD4 GB

36

36

8 8

4*/8**

4

4

4

4

4444 8 8

8

88

48

12*/16**

96

4*/8**

4*/9**

0*/4** 4

RJ45

Micro USB

SMA

4

6

4

4

6

1

1

1 1 2

3UART

10/100/1000 BASE-T Ethernet

MMC

QSFP+QSFP+

QSFP+

Mezz 02nd Slot

Mezz 0

Mfg Options

OR

QSFP+QSFP+

QSFP+

Mezz 12nd Slot

Mezz 1

Mfg Options

OR

Pluggable Module

Manufacturing Option

JTAG

IRIG-B or

Front Panel Clk

UART

SignalTap

QDRII+ SRAM0, 4, 8, 16 MB






36

36

36

36

36

36

36

36

36

36

USBSATA

IPMI

64*/32**


* = Only 36 SIO Board** = Only 48 SIO Board

0*/32**

64*/32**

DDR3 DRAM0**, 1GB**

DDR3 DRAM0**, 1GB**


0*/32**

64*/32**


0*/32**

4*/8**

4*/9**

3*/7**

3*/7**

4*/9**

4*/9**

6

G2 only

4

6

P3

96

96

PCI ExpressUp to Gen3 (7 Gbytes/s per 8x connection)

Ethernet up to 1Gb

Differential Pairs

Single Ended

HiSpeed Serial IOXCVR speed 1 up to 14.1 Gbps (1.71 GBytes/s per lane)XCVR speed 2 up to 12.5 Gbps (1.52 GBytes/s per lane)

8 8

8

15080-0000 Rev 3.0


2.1.3 WILDSTAR A5 for OpenVPX FeaturesThe WILDSTAR A5 for OpenVPX is equipped with the following system support features:

• One, Two or Three Altera GX or GS Stratix V FPGA Processing Elements:

• GXA3, GXA4, GXA5, GXA7, GXA9, GXAB

• GSD4, GSD5, GSD6, GSD8

• 8x PCIe Gen3 Connection from each FPGA to on-board PCIe switch for over 7 GB/s per Direction of Full Duplex PCIe Bandwidth

• Up to a Board Total of 8 GB DDR3 DRAM in 2 or 4 Memory Banks for each IO FPGA for up to 25 GB/s of board DRAM bandwidth.

• Up to a Board Total of 96 MB of QDRII+ SRAM in 6 Memory Banks for the Computational FPGA for up to 54 GB/s of board SRAM bandwidth.

• Backplane IO

• 16x High Speed Serial IO lanes from FPGA to VPX Data Plane (P1) for up to 28 GB/s per Direction of Full Duplex Protocol Agnostic Bandwidth

• 16x PCIe Gen1/2/3 Connections from on-board PCIe switch to VPX Expansion Plane (P2)

• Up to 32 LVDS and 8 Single Ended lines to P3

• Up to 8x High Speed Serial FPGA connections on P4

• Up to 16x High Speed Serial FPGA or Gen 1/2/3 PCIe connections to P5 (optional)

• PCIe Upstream Port can be any Backplane PCIe Port or on-board PowerPC

• Option for up to 6 Front Panel QSFP+ Transceivers running up to 14.1Gbps for up to 42 GB/s per Direc-tion of Full Duplex Protocol Agnostic Bandwidth

• Front Panel QSFP+ and Backplane Protocol Agnostic connections can support multiple channels of SDR/DDR/QDR/FDR Infiniband, 10/40Gb Ethernet, Serial Rapid IO and user designed protocols

• Self Hosted by APM86290 Dual Core Processor

• Each core runs up to 1.2 GHz

• 2 GB of DDR3 DRAM @ 800 MHz DDR

• On-Board 4GB SATA SSD and 16MB NOR Boot Flash

• 4x PCIe Gen2 connection to on-board PCIe Switch

• Host Software: Linux - API and Device Drivers

• Full CoreFire Next Board Support Package for Fast and Easy Application Development

• Open VHDL Model including Source Code for Hardware Interfaces and SignalTAP Access

• Open VHDL IP Package for Communication Interfaces

• System Management using Intelligent Platform Management Interface (IPMI)

• Hot swappable

• Diagnostic monitoring and configuration over VPX Ethernet connection, VPX PCIe bus or Front Panel USB UART.

15080-0000 Rev 3.0


• IRIG-B Support via Front Panel SMA or VPX backplane/RTM

• Front panel status LEDs for FPGAs as well as other system health

• Current, Voltage and Temperature Monitoring Sensors

• Accepts Standard Annapolis WILDSTAR 4 / 5 / 6 Family I/O Modules

• 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing

• Configured to support OpenVPX payload profile:

• MOD6-PAY-4F1Q2U2T-12.2.1-n

• Integrated Heat Sink

• Available in Industrial Temperature Grades

• Air or Conduction Cooled

• (2PE versions only)

• RTM available with:

• Additional PowerPC connections (Ethernet RJ45, USB, SATA connector or on-board SSD option and RS-232 Console)

• IRIG-B Support

• QSFP+ connection for P4 and P5 High Speed Serial IO

• Up to 16 RX and 16 TX FPGA LVDS lines

• Up to 8 2.5V FPGA Single Ended lines

• 48 3.3V or 5V General Purpose IO lines controlled by PowerPC

15080-0000 Rev 3.0


15080-0000 Rev 3.0

15WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 3: Getting Started

Chapter 3: Getting Started

16 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 3: Getting Started

15080-0000 Rev 3.0


3.1 Unpacking and Inspecting the WILDSTAR A5 for OpenVPXThe WILDSTAR A5 for OpenVPX is shipped in a sealed, static-sensitive package. In order to protect its sensitive components from moisture and static electricity damage, the board should remain in this package until installation time.

Your WILDSTAR A5 for OpenVPX shipment includes the following items:

• WILDSTAR A5 for OpenVPX

• WILDSTAR A5 for OpenVPX VHDL DVD, containing the following documentation:

• WILDSTAR A5 for OpenVPX Hardware Reference Manual

• WILDSTAR A5 WD Driver API Reference Manual

• xWFT User Guide

• xWFT API Software Reference Manual

• WILDSTAR A5 for OpenVPX Release Notes

• Analog-to-Digital Converter Mezzanine Card Manuals

• Digital-to-Analog Converter Mezzanine Card Manuals

• Fiber Mezzanine Card Manuals

• Copper Mezzanine Card Manuals

• Paper Copies:

• WILDSTAR A5 for OpenVPX Hardware Reference Manual

• WILDSTAR A5 WD Driver API Reference Manual

• xWFT User Guide

• WILDSTAR A5 for OpenVPX Release Notes

When handling the WILDSTAR A5 for OpenVPX, avoid touching any of the components on the board’s surface, as they are sensitive and can be easily damaged.

Inspect the board thoroughly for damage that may have occurred during shipping. If there is any apparent damage to the board or any items missing from the shipment, contact Annapolis Micro Systems, Inc. using the information provided in Chapter 5: Technical Support of this manual.

CautionBefore removing the board from its package, be sure to be grounded of all static electricity.

15080-0000 Rev 3.0


3.2 Board Illustrations and LED DefinitionsThe following illustrations show major component locations on all WILDSTAR A5 for OpenVPXs. LEDs and switches are defined below.

3.2.1 WILDSTAR A5 for OpenVPX ViewsRepresentations of the WILDSTAR A5 for OpenVPX are shown below.

15080-0000 Rev 3.0


Figure 3-1: WILDSTAR A5 2PE for OpenVPX, Component Side

Figure 3-1 shows the WILDSTAR A5 2PE for Open VPX with one mezzanine card site populated. Additional options include having both mezzanine sites populated, or neither site populated.

VPX Front Panel

Front Panel

Alignment Post

Front Panel Ejector

Alignment Post Recep-

VPX Backplane Connectors

RJ45

Heatsink

Mezz Site 0 with QSFP Option

Mezz Site 1 with

Standard Mezz

15080-0000 Rev 3.0


Figure 3-2: WILDSTAR A5 2PE for OpenVPX, Rev. A, Solder Side

VPX Front Panel

Front Panel Clock

Alignment Post Receptacle



15080-0000 Rev 3.0


Figure 3-3: WILDSTAR A5 2PE for OpenVPX, Rev. B, Solder Side

VPX Front Panel

Front PanelClock




15080-0000 Rev 3.0


Figure 3-4: WILDSTAR A5 3PE for OpenVPX, Component Side

Figure 3-4 shows the WILDSTAR A5 3PE for Open VPX with neither mezzanine card site populated. Additional options include having both mezzanine sites populated, or one site populated.

VPX Front Panel

Front Panel Ejector

Alignment Post

Front Panel Ejector

AlignmePost Recep

VPX Backplane Connector

s

RJ45

Heatsink

Mezz Site 0

Mezz Site 1 with

Standard Mezz

15080-0000 Rev 3.0


Figure 3-5: WILDSTAR A5 3PE for OpenVPX, Solder Side

VPX Front Panel

Front Panel Clock




15080-0000 Rev 3.0


Figure 3-6: WILDSTAR A5 2PE for OpenVPX LEDsPower Good5V PG

12V PG LED

Eth0 LED

PG 3.3V

MMC Ready LED

IOPE0 Done

Eth1 LED IOPE1 Done LED

PPC Fault

15080-0000 Rev 3.0


Figure 3-7: WILDSTAR A5 3PE for OpenVPX LEDs

5V PGLED

PG 3.3V AUX LED

12V PG LED

MMC Ready LED (Found on Component Side of Board)

Eth0 LEDEth1 LED

IOPE1 Done LED

PPC Fault LEDCPE

Done

IOPE0 Done LED

15080-0000 Rev 3.0


Figure 3-8: WILDSTAR A5 2PE for OpenVPX Front Panel LED Locations

Board Status LED

IRIG In Clock I/O / TRIG I/O

Hot Swap LED

Hot Swap Switch Located in Handle

EthernetUSB UART

IOPE1 User LEDs

IOPE0 User LEDs

15080-0000 Rev 3.0


Figure 3-9: WILDSTAR A5 3PE for OpenVPX Front Panel LED Locations

IRIG In Clock I/O / TRIG I/O

Hot Swap LED

Hot Swap Switch Located in Handle

Ethernet

IOPE1 User LEDs

Board Status LED

USB UART

CPE User LED

IOPE0 User LEDs

15080-0000 Rev 3.0


3.2.1.1 Front Panel Status LEDs

3.2.1.1.1 HOT SWAP STATUSThere is one blue Hot Swap LEDs labeled “HS” on front panel. The BLUE LED and its control shall be operational whenever Management Power (3.3VAUX) is available. It shows the hot swap state (which is the same as defined for AMC) as follows:

• ON: Module can safely be extracted. Turned on once Management Power is available to board.

• BLINK: System booting up or shutting down

• OFF: Board is operational and unsafe for extraction.

3.2.1.1.2 STS: Board StatusThere will be one bi-color Red/Green LED for board status with the following states:

• SOLID GREEN: Board is operating normally.

3.2.1.1.2.1 Control Plane StatusVPX Control Plane Status/Activity: There are 20 GREEN LEDs showing link/activity of each Control Plane Ethernet link. They are defined as:

• GREEN: Link is up but no activity

• BLINK GREEN: Link is up with activity.

• OFF: No Link/Link is down

3.2.1.1.2.2 Data Plane StatusVPX Data Plane Status: There 24 GREEN LEDs showing status of each 4x Data Plane port. These show link status as follows:

• SOLID GREEN: Link is up but no activity

• BLINK GREEN: Link is up with activity

• OFF: No Link/Link is down

3.2.1.1.2.3 Switch StatusThere will be one, tri-color Red/Green/Blue (RGB) LED for general board status:

• SOLID GREEN: normal operation, but above switch temp warning threshold

• SOLID BLUE: normal operation

• BLINK RED: switch power off, Health output indicate failure, Power not good, or over-temperature event has happened

15080-0000 Rev 3.0


3.2.1.1.3 FPGA User LEDsThere are four tri-color (RGB) FPGA User LEDs per IOPE and one per CPE (if present). Three of the four IOPE LEDs are centered under the QSFP cages (QSFPs may not be populated depending on ordering option).

3.2.1.2 Solder Side Debug Status LEDs

• 12V Power Good. This Green LED will light if 12V from the VPX backplane is enabled and good.

• 5V Power Good. This Green LED will light if 5V from the VPX backplane is enabled and good.

• 3.3V AUX Power Good. This Green LED will light if 3.3V AUX from the VPX backplane is enabled and good.

• MMC Ready. This Green LED will light when MMC status is good (i.e. MMC and PPC are booted and board is in operational state, i.e. Board Health is good). Functionality may change as needed.

• Ethernet 0 Link/Status. This LED shows link status of Ethernet channel 0 which goes to the front panel.

• Ethernet 1 Link/Status. This LED shows link status of Ethernet channel 1 which goes to the VPX backplane

• IOPEx Done. Indicates FPGA is configured.

• PPC Fault. This Red LED will blink or be lit if there is a PPC hardware error.

15080-0000 Rev 3.0


3.2.2 WILDSTAR A5 for OpenVPX SwitchesWILDSTAR A5 for OpenVPX switch locations are defined in Figure 3-10 and Figure 3-11.

Figure 3-10: WILDSTAR A5 2PE for OpenVPX, Rev. A, Switch Locations

SW4

SW3

SW2

SW1

15080-0000 Rev 3.0


Figure 3-11: WILDSTAR A5 2PE for OpenVPX, Rev. B, Switch Locations

SW4

SW3

SW2

SW1

15080-0000 Rev 3.0


Figure 3-12: WILDSTAR A5 3PE for OpenVPX Switch Locations

SW2

SW4

SW3

SW1

15080-0000 Rev 3.0


3.2.2.1 DIP Switch Configuration OptionsDIP switches settings are described below.

3.2.2.1.1 PCI Express Switch Configuration (REFDES: SW3)One switch with eight positions.

• Upstream Port Select. This switch setting configures the on-board PCIe switch’s upstream port. Options are:

• Reserved Switches:

• Global Speed Select. These jumpers will define the maximum PCIe speed supported for ALL PCIe interfaces. They are defined as:

3.2.2.1.2 Reserved Switches (REFDES: SW2)One switch with two positions.

Upstream Port 4 3 2 1

PowerPC (4x) (default) OFF ON OFF ON

VPX P2 (8x): EP[07:00] ON ON OFF OFF

VPX P2 (8x): EP[15:08] ON ON OFF ON

Reserved 6 5

Reserved (default) ON OFF

PCIe Global Speed 8 7

Gen3 (8Gbps-default) OFF ON

Gen2 (5Gbps) OFF OFF

Gen1 (2.5Gbps) ON OFF

Reserved 2 1

Reserved (default) OFF OFF

15080-0000 Rev 3.0


3.2.2.1.3 PowerPC UART Selects (REFDES: SW4)One switch with four positions.

Note: Front Panel UART is USB, backplane UART is RS-232.

Note: There are four UART pins reserved on the VPX backplane for PowerPC UART 1 and 2. Since RS-485 is differential it uses all four pins. When RS-232 is selected then both UART 1 and 2 are available.

PPC UART0 Console Location Select 4

PowerPC: Front Panel, MMC: Backplane (default) ON

PowerPC: Backplane, MMC: Front Panel OFF

PPC UART1/2 RS-232/RS-485 Select 3

PowerPC UART1, 2: RS-232 (default) ON

PowerPC UART1: RS485 (UART 2 Unused) OFF

RS-485 RX Termination Select 2

100-ohm Parallel Termination ON

No Termination (default) OFF

Backplane UART Disable 1

Disable All Backplane UARTs ON

Enable All Backplane UARTs (default) OFF

15080-0000 Rev 3.0


3.2.2.1.4 MMC Configuration Selects (REFDES: SW1)One switch with four positions.

The ws_flash_tool.sh utility can be used to verify that on-board SPI flash is locked. The Global Flash Write Enable DIP switch above controls the ability for software to lock/unlock SPI flash and controls lock/unlock directly for other flash devices.

In System Program (ISP) Select (reserved) 1

Reserved ON

Reserved (default) OFF

Global Flash Write Enable 2

On-Board Flash Write Enabled (Not Write Protected, default) ON

On-Board Flash Write Disabled (Write Protected) OFF

Chassis Manager Select 3

Board acts as Chassis Manager (ChMC) ON

Board is not a Chassis Manager (IPMB) (default) OFF

MMC Hard Reset Select (Rev B) 4

VPX SYSReset causes hard (pin) MMC Reset ON

VPX SYSReset causes soft (SW) MMC Reset (default) OFF

15080-0000 Rev 3.0


15080-0000 Rev 3.0

37WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 4: Installation

Chapter 4: Installation

38 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 4: Installation

15080-0000 Rev 3.0


This chapter provides hardware installation instructions for WILDSTAR A5 for OpenVPXs, as well as switch setting descriptions and PE, board, and system reset options.

Note:A PDF of the WILDSTAR A5 for OpenVPX Hardware Reference Manual can be found on the Documentation CD-ROM included with your board.

4.1 WILDSTAR A5 for OpenVPX InstallationFollow the steps below to install the WILDSTAR A5 for OpenVPX into the host system.

1. Ground yourself of static electricity with a ground strap.

2. Shut down the host system and power off.

3. Grasp the WILDSTAR A5 for OpenVPX by the front panel ejectors with the VPX connectors facing away from the user.

4. Gently slide the WILDSTAR A5 for OpenVPX into the slot.

5. When the VPX connectors first contact the backplane connectors, push firmly on the front panel ejectors until they snap into place. Engage the front panel ejector tabs with the chassis rails to fully seat the WILDSTAR A5 for OpenVPX in the VPX backplane.

Note: Avoid resting the WILDSTAR A5 for OpenVPX on it’s VPX backplane connectors, as this may cause damage to the board.

To remove the board, connect a ground strap to the user and power off the host system. Gently press the red ejector release buttons, press down on the front panel ejectors, and slowly pull the board from the chassis.

CautionCare should be taken not to catch the QSFP connectors on the PCIe chassis when board is inserted, as it can damage the QSFP cage.

CautionThe WILDSTAR A5 for OpenVPX must be inserted into the chassis gently to avoid scraping frag-ile components on the edges of the board.

15080-0000 Rev 3.0


4.2 WILDSTAR A5 for OpenVPX Switch SettingsSwitches on the component side of each WILDSTAR A5 for OpenVPX control basic configurations.

WILDSTAR A5 for OpenVPXs are delivered with all switches in their default settings. Confirm that switches are set according to the information in Table 4-1.

Table 4-1: WILDSTAR A5 for OpenVPX Default Switch Settings

For detailed switch descriptions, see WILDSTAR A5 for OpenVPX Switches.

4.3 Configure Backplane Slot JumpersSome backplanes have jumpers for slot configuration. These jumpers could include selection of system controller, flash protect and whether the slot is connected to backplane bussed Maskable Reset. Note that this card will perform a safe shutdown if maskable reset is asserted on the backplane, which will look identical to the hot swap handle being unlocked. Refer to the hot swap section on board states based on hot swap LED.

4.4 Power Up SystemAfter all cable connections have been made and the board has been properly plugged in, turn on power to the host system. The WILDSTAR A5 for OpenVPX can also be inserted into a powered backplane.

Switch Position

Switch 8 7 6 5 4 3 2 1

SW1 X X X X OFF OFF ON OFF

SW2 X X X X X X OFF OFF

SW3 OFF ON ON OFF OFF ON OFF ON

SW4 X X X X ON ON OFF OFF

15080-0000 Rev 3.0


4.5 WILDSTAR A5 for OpenVPX Hot SwappingThe WILDSTAR A5 for OpenVPX supports hot swap with the lower VPX handle. There is a built in micro switch that detects whether the handle is locked or not.

4.5.1 WILDSTAR A5 for OpenVPX Hot Swap ProcedureThe sequence for adding a WILDSTAR A5 for OpenVPX to a powered VPX backplane is done by the following:

1. A board is inserted into a powered VPX chassis

2. Lock both VPX handles.

3. The board will automatically power up once inserted and handles are locked. The blue carrier hot swap LED will blink as PowerPC is booting and go off once booted.

The sequence for removing the WILDSTAR A5 for OpenVPX from a powered VPX backplane is done by the following:

1. Unlock both VPX handles by pushing on the red button on the VPX handle, do not attempt to remove board yet.

2. Blue carrier hot swap LED will blink as PowerPC shuts down safely.

3. Blue carrier hot swap LED will remain lit when WILDSTAR A5 for OpenVPX is safe to remove from the chassis.

4. WILDSTAR A5 for OpenVPX can be removed from powered backplane.

15080-0000 Rev 3.0


15080-0000 Rev 3.0

43WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 5: Technical Support

Chapter 5: Technical Support

44 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 5: Technical Support

15080-0000 Rev 3.0

45WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 5: Technical Support

If you have any questions about installing, programming, using, or maintaining your WILDSTAR A5 for OpenVPX, please call the WILDSTAR Technical Support team at (410) 841-2514, fax at (410) 841-2518, or send e-mail to [email protected]. Our web site address is http://www.annapmicro.com.

The suggestions listed below will help us respond to your questions more quickly.

5.1 Board Identification NumbersEach Annapolis Micro Systems board is prominently labeled with three unique codes: the Product Configuration Code (PCC), the Serial Number (SN), and the Revision Level Code (RLC). You can also find these codes by installing the board and running wd_inst.exe from the host software CD.

• The Product Configuration Code (PCC) identifies PE type, memories, clocking, and other options selected for the particular board.

• The Serial Number (SN) is a unique number identifying each board.

• The Revision Level Code (RLC) includes information about revisions and engineering modifications made to the board.

See Figure 5-1 for the locations of these labels.

15080-0000 Rev 3.0

http://www.annapmicro.com

mailto:[email protected]

46 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 5: Technical Support

Figure 5-1: Labels for WILDSTAR A5 for OpenVPX Serial Number, PCC, and RLC

When contacting Annapolis Micro Systems with board-related questions, please include these codes in your query, as well as the information listed below:

• Board operating system

• Host software version

• Host platform

• Host OS

• Driver versions

RLC

PCC

Serial Number

15080-0000 Rev 3.0

47WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 6: WILDSTAR 6 /VPX Hardware Reference

Chapter 6: WILDSTAR A5 for OpenVPX Hardware Reference

48 WILDSTAR A5 for OpenVPX Hardware Reference ManualChapter 6: WILDSTAR 6 /VPX Hardware Reference

15080-0000 Rev 3.0


This chapter contains WILDSTAR A5 for OpenVPX Hardware Reference information for the WILDSTAR A5 for OpenVPX, including thermal management, clocking, and backplane specifications.

6.1 WILDSTAR A5 for OpenVPX Specifications Table 6-1 specifies the physical dimensions and operating range for the WILDSTAR A5 for OpenVPX:

Table 6-1: WILDSTAR A5 for OpenVPX Specifications

Table 6-2: WILDSTAR A5 for OpenVPX Tolerances

Note:The WILDSTAR A5 for OpenVPX is designed for 12V-centric VPX backplanes (i.e. the majority of power is drawn from +12V).

6.2 Thermal and Power Management This section describes WILDSTAR A5 for OpenVPX temperature sensing, voltage and current limits, heatsink information, power functions, as well as external power capabilities.

6.2.1 WILDSTAR A5 for OpenVPX HeatsinksHeat remediation for WILDSTAR A5 for OpenVPXs includes a passive heatsink with thermal monitoring.

Note:All WILDSTAR A5 for OpenVPXs are shipped with a heatsink installed. The heatsink is not removable except by the factory.

Figure 6-1 shows a heatsink mounted on the WILDSTAR A5 for OpenVPX. These larger heatsinks act as a stiffener for the boards, making them sturdier.

Physical Dimensions:

Length: 233.20 mm / 9.181 inWidth: 164.26 mm / 6.467 inThickness: 2.95mm / 0.116 inWeight: 2lb 3.8oz / 1016 g

Operating Range: Temperature (Commercial): 0º to 50ºC

Backplane Supplied Voltage Tolerance

+3.3V +/- 5%

+5.0V +/- 5%

+12.0V +/- 5%

CautionWILDSTAR A5 for OpenVPXs should never be run without the supported heatsink. Otherwise, the board could permanently be damaged.

15080-0000 Rev 3.0


Figure 6-1: WILDSTAR A5 for OpenVPX (Component Side, Shown With Heatsink)

Heatsink

15080-0000 Rev 3.0


6.2.2 Temperature SensingThe PowerPC and Ethernet/Infiniband Switch ASIC on each board contain devices that monitor the junction temperatures of these components. Additional sensing diodes are located at various board locations to monitor ambient temperature. Information concerning temperatures can be revealed by using the Annapolis Micro Systems, Inc. software included in your WILDSTAR A5 for OpenVPX shipment.

Note:WILDSTAR A5 for OpenVPX temperature monitoring sensors are accurate within +/- 1˚C.

Figure 6-2 shows temperature monitoring points on the WILDSTAR A5 for OpenVPX.

CautionThe FPGA junction temperature on commercial WILDSTAR A5 for OpenVPX types should never exceed 125°C. The PCIe switch junction temperature should not exceed 110°C. Temperatures above these ranges may result in performance degradation and component damage.

15080-0000 Rev 3.0


Figure 6-2: WILDSTAR A5 2PE for OpenVPX, Temperature Monitoring Points (Component Side)

PPC

Ambient 1

PCIe Switch

= Internal Temperature Sensing Diodes

IOPE0

IOPE1

Ambient 2 Ambient 0

15080-0000 Rev 3.0


Figure 6-3: WILDSTAR A5 3PE for OpenVPX, Temperature Monitoring Points (Component Side)

PPC

Ambient 1

PCIeSwitch

= Internal Temperature Sensing Diodes

IOPE0

IOPE1

Ambient 2

Ambient 0

CPE

15080-0000 Rev 3.0


6.3 Supported Backplane ProfilesThe WILDSTAR A5 for OpenVPX complies with payload slot profile SLT6-PAY-4F1Q2U2T-10.2.6-n but can be inserted into the following six payload slot profiles.

VPX Payload Slot Profile Data Plane (4x) Expansion Plane (8x)

Control Plane (1x-1000BASEX)

Control Plane (2x-Copper)

SLT6-PAY-4F1Q2U2T-10.2.1-n 4 2 2 2

SLT6-PAY-4F2T-10.2.2-n 4 0 0 2

SLT6-PAY-8F-10.2.3-n 8 0 0 0

SLT6-PAY-2F2U2T-10.2.5-n 2 0 2 2

SLT6-PAY-4F1Q2U2T-10.2.6-n 4 2 2 2

SLT6-PAY-4F2Q2U2T-10.2.6-n 4 4 2 2

Key

Control Plane2 1x

User Defined

User Defined

Data Plane2 4x

User Defined

Key

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE

DiffP1/J1

SEP0/J0

Key

Control Plane2 2x

Data Plane 4 4x

User Defined

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE

DiffP1/J1

SEP0/J0

Key

Key

Key

Control Plane2 2x

Data Plane 8 4x

User Defined

User Defined

SE

DiffP6

SE

DiffP5

SE

DiffP4

SE

DiffP3

SE

DiffP2

SE Diff

P1

SEP0

Key

Key

Key

Reserved

2F2U2T-10.2.5 4F2T-10.2.2 8F-10.2.3

15080-0000 Rev 3.0


4F1Q2U2T-10.2.1 4F1Q2U2T-10.2.6 4F2Q2U2T-10.2.7

Data Plane 4 4x

Expansion Plane2 8x

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE

DiffP1/J1

SEP0/J0

Key

Key

Key

Control Plane2 1x

Control Plane2 2x

Data Plane 4 4x

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

SE

DiffP2/J2

SE

DiffP1/J1

SEP0/J0

Key

Key

Key

2 RST

2 CLK

Expansion Plane2 8x

Control Plane2 1x

Control Plane2 2x

Data Plane 4 4x

Expansion Plane2 8x

User Defined

User Defined

SE

DiffP6/J6

SE

DiffP5/J5

SE

DiffP4/J4

SE

DiffP3/J3

DiffP2/J2

SE

DiffP1/J1

SEP0/J0

Key

Key

Key

Expansion Plane 2 8x

SE

Control Plane2 1x

Control Plane2 2x

2 RST

2 CLK

15080-0000 Rev 3.0


6.4 ClockingThe WIDSTAR A5 for OpenVPX clocking structure is very flexible in that it allows all programmable clocks on a board to be synchronized to a common source. Each FPGA module has its own PLL so can run at different rates than other FPGA modules, if desired. The 8x8 crossbar and PLLs are programmed via provided software API.

Figure 6-4: WILDSTAR A5 for OpenVPX Clocking

• SYNCCLK: Designed to be a free-running clock that the Si5375 PLL can synchronize to, if desired

• 1PPSCLK: This clock can be a free-running clock or a trigger pulse. It goes directly into an FPGA pin

• PCLK: PCLK is the main processing clock for the FPGA

• MEMCLK (MCLK): MCLK is used to run the memory interfaces on the FPGA

• HSS REFCLKx: These clocks are for the high speed serial (HSS) interfaces. Each clock goes to each side of the device. The PCIe interface has it’s own fixed 100 MHz clock

• VPX AUXCLK: This clock is distributed on the VPX backplane and complies to the OpenVPX specification. It is generally designated for a trigger or 1 pulse per second (1PPS) type clock although it can be used for a free running clock. Generally clocks <125 MHz are used on these pins.

IOPE/CPE

Altera S5

Silabs Si5374

(4 PLLs)

1:5 clock buffer

125 MHz Oscillator

MEM CLK (2)P

LL

AP

LL

BP

LL

CP

LL

D

PCLK

HSS REFCLK1 (2)

HSS REFCLK0 (2)

PL

LA

PL

LB

PL

LC

PL

LD

PLL REFCLK INPUTS (4)

SYNCCLK (1)

OTHER FPGA MODs

REF

(Can be used for Loop Timing)

100 MHz Oscillator OTHER FPGA

MODs/PCIe Switch

HSS REFCLK

Clock Mux(8x8 XBAR)

IO CARD Clock In 0

IO CARD Clock In 1

OTHER FPGA MODs

FPGA MODULE

1PPSCLK (1)

BPCLK Input

PowerPC GPIO (SW Trigger)

IOPE0 FPGA Clock

From VPX Backplane

On Front Panel

FPCLK (SMA)

FPSMA

SMA OUT (<275 MHz)FPCLK

FPGA Clock to ClockMux (From IOPE0 Only)

VPX REFCLK

MLVDS XCVRs

VPX AUXCLK

25 MHz Oscillator

TXEN (/model/xx ctrl)Output When System

Controller

RXEN (/model/gpio0 ctrl)

TXEN (/model/xx ctrl)

To/From VPX Backplane

OTHER FPGA MODs

Silabs Si5374

(4 PLLs)

IOPE Only

PL

LA

PL

LB

PL

LC

PL

LD

PL

LA

PL

LB

PL

LC

PL

LD

REF

PLL REFCLK INPUTS (4)

HSS REFCLK2 (2)

HSS REFCLK3 (2)

HSS REFCLK4 (2)

HSS REFCLK5 (2)

Mezz CardDirect HSS REFCLKs

(IOPE Only)

15080-0000 Rev 3.0


• VPX REFCLK: This clock is distributed on the VPX backplane and complies to the OpenVPX specification. The OpenVPX specification states a board which is system controller should drive a 25 MHz clock on this line. System controller is determined by a backplane signal which can usually be selected in a chassis by jumper. By specification, software is also allowed to override this and move system controller. There is also provisions in the spec to allow for other frequencies other than 25 MHz. Generally clocks <125 MHz are used on these pins.

• BPCLK: This is an LVDS backplane clock that comes in VPX backplane pins P4.A9(+) and P4.B9(-).

• IO Card Clock x: These are clocks driven from the IO card. Often an ADC or DAC will provide a divided down version of the sample clock on these pins.

• PowerPC GPIO. This is driven by a GPIO on PowerPC. It can be used as a low precision SW trigger

• IOPE0 FPGA Clock: This is driven by IOPE0 and can be either a clock or a trigger.

• FPCLK: This clock is used to receive a clock/trigger via the front panel SMA. There are software programmable termination options when the SMA receives a clock:

1. The clock path can be AC or DC coupled

2. If DC coupled, there is an option for a 50-ohm resistor to GND, one diode drop above GND (for 2.5V LVPECL), two diode drops above GND (for 3.3V LVPECL), or FLOAT

3. When DC coupled, there is a threshold option of 1.136V (2.5V LVCMOS), 1.380V (2.5V LVPECL), 1.633V (3.3 V LVCMOS) and 2.185V (for 3.3V LVPECL)

• SMA OUT: This clock is used to send a clock/trigger out the front panel SMA. The clock coming out will be a 3.3V LVTTL signal with 24mA drive capability. Maximum clock rate is approximately 275 MHz

• Loop Timing Clocks: The FPGA can drive a source clock for any of the four clocks generated by the Si5375 PLL. This allows for one clock to be used for SONET loop timing where one HSS reclk provides the RX clock and one HSS REFCLK provides the TX clock based on the recovered RX clock fed to PLL from FPGA.

15080-0000 Rev 3.0


The following diagram shows how the HSS reference clocks are attached to the IOPE dedicated reference clock inputs. Each red box represents a group of six High Speed Serial (HSS) transceivers

Figure 6-5: Physical layout of Reference Clock Connections on FPGA

Note: Reference clocks can only be used on the side they come in on. Mezzanine reference clocks can only be used with HSS signals on right side (i.e. mezzanine HSS, not backplane).

Note: There are two global reference clock trees per side.

Note: There are six PLLs available in two Silicon Labs Si5374 devices that generate reference clocks. Each side gets a copy from each PLL.

QSFP+QSFP+

QSFP+

Mezz 0

Mezzanine Card

OR

Mezz/QSFP0 (4x)

SYS (2x)

Mezz/QSFP1 (4x)

SYS (2x)

Mezz/QSFP2 (4x)

SYS (2x)

Mezz3 (4x)

SYS (2x)

MEZZ REFCLK0

MEZZ REFCLK1

SI5374 REFCLK5

SI5374 REFCLK4

SI5374 REFCLK1

SI5374 REFCLK0

SI5374 REFCLK3

SI5374 REFCLK2

VPX P1 CH0 (4x)

VPX P1 CH1 (4x)

PCIE

PCIE PCIe REFCLK

VPX P4 [1:0] (2x)

VPX P4 [3:2] (2x)

SYS (2x) SI5374 REFCLK5

SI5374 REFCLK4

SI5374 REFCLK1

SI5374 REFCLK0

SI5374 REFCLK3

SI5374 REFCLK2P1

P1

P4

VPX Backplane

PCIe Switch

FPGA LEFT SIDE FPGA RIGHT SIDE

GBR3

GBR2

GBR1

GBR0

GBL3

GBL2

GBL1

GBL0

15080-0000 Rev 3.0


6.4.1 Front Panel Clock TerminationThere is a front panel SMA which allows the user to input an AC Coupled Clock, a DC Coupled Trigger (or Clock), IRIG, or output a signal. If the SMA is being used as a clock or trigger signal, it cannot also be used for IRIG. In this case, the user may input IRIG data through a backplane pin supported by the WILDSTAR OpenVPX Rear Transition Module (or another custom-designed card).

Figure 6-6: WILDSTAR A5 for OpenVPX SMA Circuit

The FPCLK block requires seven control signals for proper operation, all of which must be driven open collector (i.e. driven to GND for a ‘0’ and allowed to float for a ‘1’). The SW should default to driving all control signals to ground unless the user sets them to a ‘1’.

• SMA_SEL[1:0]_OC

• TERMSEL[2:0]_OC

• THRESHSEL[1:0]_OC.

SMA_SEL[1:0] determine the mode of the circuit.

SMA_SEL1 SMA_SEL0 FP SMA Mode IRIG SRC

1 1 DC Coupled Trigger Input Backplane

1 0 AC Coupled CLK Input Backplane

0 1 Output Backplane

0 0 IRIG Front Panel

FPSMA

TERMSEL[2:0]1xx: GND010: ~0.7v011: ~1.4v00x: Float

49.9 Ohm

VREF (1.6V)

49.9 Ohm

THRESHSEL[1:0]11: ~1.14v10: ~1.63v01: ~1.38v00: ~2.19V

0

1

FPCLKDC_SEL

00

01

10

11

IRIG-BADC IRIG Data

( To FPGA)

SMA Out(From ClockMux)

SMA_SEL[1:0]

FPCLK In(To ClockMux)

IRIG-B (From VPX Backplane)

00

011x

15080-0000 Rev 3.0


When the Front Panel SMA Mode is set to DC Coupled Trigger Input, the user can select the termination on the input as well as the threshold for which the signal is compared to determine whether the signal is interpreted as a ‘0’ or a ‘1’.

The TERMSEL[1:0] signals determination the termination according to the table below.

THRESHSEL[1:0] determine the low to high threshold according to the table below.

6.4.1.1 LimitsWhen the input is configured as a DC Coupled Trigger Input, the input signal must be kept between 0V and 3.3V.

When the input is configured as an AC Coupled Clock input, the input signal must be less than 3.2Vpp.

When the input is configured as an IRIG input, the input signal must be kept between 0V and 5V.

TERMSEL2 TERMSEL1 TERMSEL0 Input Termination Comments

1 x x 50Ω to GND

0 1 150Ω to 1 diode drop above

GNDRecommended for 2.5V

LVPECL Inputs

0 1 050Ω to 2 diode drops above

GNDRecommended for 3.3V

LVPECL Inputs

0 0 1 Invalid

0 0 0 High ImpedanceRecommended for LVCMOS

Inputs

THRESHSEL 1 THRESHSEL 0 Input Threshold Comments

1 1 1.14 Recommended for 2.5V LVCMOS Inputs

1 0 1.63V Recommended for 3.3V LVPECL Inputs

0 1 1.38V Recommended for 2.5V LVCMOS Inputs

0 0 2.19V Recommended for 3.3V LVPECL Inputs

15080-0000 Rev 3.0

61WILD Storage for OpenVPX Reference ManualChapter 7: Host Module Reference

Chapter 7: Host Module Reference

62 WILD Storage for OpenVPX Reference ManualChapter 7: Host Module Reference

14980-0000 Rev 3.4


7.1 Host Module IntroductionThe host module consists of the PowerPC (PPC) and the Modular Management Controller (MMC). This module is common across multiple Annapolis Micro Systems, Inc. VPX boards. Figure 7-1 contains a block diagram showing the PowerPC and MMC connections. There are two ethernet ports on the PowerPC and each connects to a PHY that supports either a copper of fiber interface. It auto-selects based on which links are up and will prefer copper. Not all boards have all front panel or backplane Ethernet connections as listed in the block diagram.

Figure 7-1: Host Module Architecture

P3

HiSpeed Serial IOSingle EndedDifferential Pairs

P2P1P0 P4 P5 P6

Utility Plane

Data Plane

ExpPlane

UserDefinedPlane

Control & User DefPlane

ExpPlane

Rsvd

APM86290

Dual Core 1.2 GHz PowerPC

PCI Express

4

MMC

DDR3 DRAM2GB

64

RJ45

Micro USB

UART

Ethernet PHY 0

Ethernet PHY 1

RGMII RGMII

10/1

00/

100

0B

AS

E-T

(c

opp

er)

*

Magnetics

100

0BA

SE

-X (

seria

l)**

10/100/1000BASE-T (copper)

1000

BA

SE

-X(s

eria

l)*

Magnetics

CPutp01 CPutp02CPtp01

Boot NOR

(16MB)

SATA Solid State Drive

(4GB)

USB to UART

Convert

UART0

SA

TA

*

US

B*

MUX

RS-232Convert

RS-232/RS-422Convert

UART1/UART2

RS

-232

(2

)O

R

RS

-422

USB

I2C

EEPROM

To PPC UART3

UART3To MMC

PCIe

RS

-232

Management Plane (I2C)

Software Trigger

I2C Control

(Not Present On VPX Storage)

Notes:* Not connected on VPX Switch** Connected to Switch Silicon on VPX Switch, not backplane

14980-0000 Rev 3.4


7.2 Host Module Resets

7.2.1 PowerPC Reset ConditionsThe OpenVPX’s PowerPC will be reset:

• Following power up until all of the following conditions are true: Host 12V, 5V and 3.3VAUX are within spec and Global board power is good.

• If the PowerPC does not notify MMC it has booted (i.e. has hung during boot) as it will be reset by a MMC watchdog timer.

• If an MMC “cold reset” or “graceful reboot” event occurs via VITA 46.11 FRU Control message.

• If VITA 46.11 FRU State Policy Bits are set to hold PowerPC in reset.

• If payload power is cycled via VPX SYSRESET, VPX Maskable Reset, Hot Swap event, or VITA 46.11 Set FRU Activation message occurs.

Note:It is possible to set VITA 46.11 FRU State Policy Bits to disable VITA 46.11 Set FRU Activation message option to deactivate with the “activate locked” bit. This will not allow any events that would cause payload power to be disabled such as Maskable Reset and Hot Swap events. It is also important to note that it is possible to set the “deactivate locked” bit so that payload power cannot be enabled until this bit is cleared. These bits are persistent over power reset cycles and are only changeable with VITA 46.11 IPMI mes-sages.

7.2.2 VPX Maskable ResetIf a maskable reset is asserted on the VPX backplane, the MMC will perform a safe shutdown of the PPC as if a hot swap event has occurred. This allows chassis with a maskable reset button to safely shutdown all cards in the chassis that support this feature with a button push. Many chassis have a jumper disconnecting Maskable reset from each VPX slot which allows this feature to be disabled.

7.2.3 VPX SYSRESETA VPX SYSRESET will reset all devices on board back to a known state. This will perform a hard reset to the MMC which will remove main payload power and cause the board to behave as if chassis power was cycled. Note since SYSRESET is attached to MMC hard reset pin it is not maskable by any VITA 46.11 commands.

7.2.4 MMC Reset ConditionsThe MMC will be reset under the following conditions:

• While the SYSRESET# signal on the VPX P0 backplane connector is asserted.

• If a VITA 46.11 FRU Control message is received. There are two options for this message that reset the MMC:

• “Warm Reset”: This is a MMC software reset and will reset the MMC software only without changing configuration. The PowerPC will not be reset and payload power will not be removed.

• “Cold Reset”: This will perform a reset similar to a SYSRESET event. Payload power is removed and board is returned its initial power up state.

14980-0000 Rev 3.4


7.3 Host Module MMC Features The OpenVPX MMC will provide the following features:

• Boot Loader

• Backplane Hardware Address Translation

• Hot-Swap button and LED

• IPMI interface on Debug Port

• IPMI interface on serial channel to Payload

• IPMB interfaces on System IPMB backplane channel

• MMC ready LED

• Device SDRs for sensors and management locator records

• FRU information for main board

• VITA 46.11 Mandatory Sensors:

• FRU State

• IPMB Link State

• FRU Health

• FRU Voltage

• FRU Temperature

• Payload Test Status

• Payload Test Results

• Auxiliary FRU Sensors

• 3.3V Current Sensor

• 5V Current Sensor

• 12V Current Sensor

• PPC Temperature Sensor

• Chassis Manager Site assignment

When board is assigned as Chassis Manager, it will function as a Tier 1 Chassis Manager described later. Otherwise, it will function as a Tier 1 Intelligent Platform Management Controller as defined by VITA 46.11. Also known as IPMC, this management controller interfaces with a Chassis’ IPMB and represents the FRU and any devices subsidiary to it.

Note:There must be only one board in the chassis configured to run as Chassis Manager. It provides a central-ized IPMI interface to access all boards in the chassis.

A VITA 46.11 Chassis Manager tracks the board and FRU population within a single Chassis comprised of VITA 46.11 components. The Chassis Manager performs these functions using the common System IPMB interface,

14980-0000 Rev 3.4


which provides IPMI protocol access to all intelligent FRUs in the Chassis. When assigned role of Chassis Manager, the MMC will provide the following Tier 1 functions:

• IPMC Discovery

• IPMC/FRU Polling

• Maintain SDR Repository containing all device SDRs and Management Controller Locator Records for each FRU in the system

• Maintain Chassis Address Table

• IPMI interface on LAN running on PPC

14980-0000 Rev 3.4

67WILD Storage for OpenVPX Reference ManualChapter 8: Serial Board Configuration Utility

Chapter 8: Serial Board Configuration Utility

68 WILD Storage for OpenVPX Reference ManualChapter 8: Serial Board Configuration Utility

14980-0000 Rev 3.4


The serial board configuration utility provides a means for configuring common settings of the baseboard operatingsystem. The following provides a brief description of the options and their corresponding dialogs within theconfiguration utility.

The serial board configuration utility can be accessed through the serial console, or remotely through an ssh session. The default serial port settings for the console interface are: 57600 bps, 8 data bits, 1 stop bit, no parity, and Xon/Xoff flow control. The ssh client login user id is root, no password is necessary.

To access the serial board configuration utility, run the following command from the command prompt:

serconfig

Note:This chapter applies to baseboards with a version of 1.15.0 or greater. If the /etc/rstversion file exists, and the version is 1.15.0 or greater then this manual is applicable. If this is not the case, please refer to the manual on the CD that was shipped with the board.

Figure 8-1: Configuration Menu

Figure 8-1 shows the main serial configuration menu that will be presented on the console when the utility is started. At the top of the menu, the IP address of the system is shown. The following configuration options are available:

• Set Network Configuration (Hot Key 'I'): Set basic network configuration options for the available ethernet ports.

• Restore Network Default Configuration (Hot Key 'N'): Restore network to default configuration.

• Wild Factory Flash Recover (Hot Key 'F'): Sanitize and restore flash device to factory settings.

• Set Time (Hot Key 'T'): Set the time of the hardware reference clock.

• Set Date (Hot Key 'D'): Set the date of the hardware reference clock.

14980-0000 Rev 3.4


• Turn Web Administration OFF/ON (Hot Key 'W'): Enable or disable the integrated HTTP server which is used for various administrative tasks.

• Reboot (Hot Key 'R'): Reboot the system's PowerPC.

• Quit (Hot Key 'Q'): Quit the serial configuration menu.

Figure 8-2: Network Interface Menu

Note:The WILD OpenVPX 14Gbit Switch Card configuration is shown, but other board options may vary.

Figure 8-2 presents the available Ethernet interfaces that can be configured as well as a brief description of their physical location on the baseboard.

Figure 8-3: Network Configuration Menu

Figure 8-3 presents the possible configuration options for the selected interface. Note that changing the configuration of an ethernet interface will require a reboot for the changes to take effect.

14980-0000 Rev 3.4


Figure 8-4: Set Network Configuration Menu

If a static network configuration is selected from the “Network Configuration Menu” (see Figure 8-3) the dialog in Figure 8-4 is displayed, which allows for static network configuration of the selected interface.

Figure 8-5: Set New Time Menu

The dialog box shown in Figure 8-5 allows for setting of the hardware reference clock, in 24-hour format. After selecting “OK” the hardware reference clock will be updated with the specified time.

14980-0000 Rev 3.4


Figure 8-6: Set New Date Menu

The dialog box shown in Figure 8-6 allows for setting of the date portion of the hardware reference clock. After specifying a date and selecting “OK” the hardware reference clock will be updated.

14980-0000 Rev 3.4


Figure 8-7: Restore Network Default Configuration Confirmation

The dialog box shown in Figure 8-7 is the confirmation window for restoring the network to the default configuration. This operation will set the network configuration back to the original factory state, overwriting any changes made by the user. Note that the restore operation will require a reboot for the changes to take effect.

Figure 8-8: Wild Factory Flash Recover Confirmation

The dialog box shown in Figure 8-8 is the confirmation window for the Wild Factory Flash Recover operation. This operation will completely erase all data stored in the flash device, and then reprogram the device to the factory default configuration. Any environment variables added to uboot will also be erased as part of this procedure. The flash recovery take approximately 20 minutes to complete, the board will reboot itself during the procedure, and reconfigure U-Boot, please refrain from interrupting. It is extremely important that the process completes without interruption, or the board may end up in a non-functional state.

14980-0000 Rev 3.4


14980-0000 Rev 3.4

75WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix A: OpenVPX Backplane Pinout

Appendix A: WILDSTAR A5 and WILDSTAR 7 for OpenVPX

6U Backplane Pinout

76 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix A: OpenVPX Backplane Pinout

15080-0000 Rev 3.0


A.1 WILDSTAR A5 and WILDSTAR 7 for OpenVPX 6U Backplane Pinout

Figure A-1: OpenVPX Payload Profile

The WILDSTAR A5 and WILDSTAR 7 /VPX boards will have the above OpenVPX payload profile: SLT6-PAY-4F2Q2U2T-10.2.7 which is new to the OpenVPX 2.1 specification. These cards will plug into any OpenVPX payload slot.

15080-0000 Rev 3.0


A.2 Pin P0Table A-1: Pin P0

Note:Active low signals are denoted with an asterisk (*).

Connector P0 follows the VITA 65 defined pins where:• +12V: +12V in (all bussed together)

• +5V: +5V in (all bussed together)

• Busx I2C CLK: I2C clocks for chassis management. See VITA 46.0, section 4.8.8.

• Busx I2C DAT: I2C data for chassis management. See VITA 46.0, section 4.8.8.

• GAn*: Geographical addressing bits for I2C. See VITA 46.0, section 4.8.2.

• GAP*: Geographical addressing parity. See VITA 46.0, section 4.8.2.

• TDI, TDO, TCK, TMS, TRST*: JTAG Port. Can be used for debug port to Altera FPGAs.

• REF_CLK+/-: 25 MHz OpenVPX reference clock or other frequency. Can be driven and/or received. See VITA 46.0, section 4.8.4 and VITA 65 OpenVPX specification 3.5.1 for proper backplane termination/usage.

• AUX_CLK+/-: optional 1 pulse-per-second (1 PPS) timing reference or other clock. Can be driven and/or received. See VITA 46.0, section 4.8.6 and VITA 65 OpenVPX specification 3.5.2 for proper backplane termination/usage.

There are no user defined pins on P0.

Row G Row F Row E Row D Row C Row B Row A

1 +12V +12V +12V No Connect +12V +12V +12V



4 Bus1 I2C CLK Bus1 I2C DAT GND -12V_Aux GND SYSRESET* NVMRO

5 GAP* GA4* GND 3.3V_Aux GND Bus0 I2C CLK Bus0 I2C DAT

6 GA3* GA2* GND +12V_Aux GND GA1* GA0*

7 TCK GND TDO TDI GND TMS TRST*

8 GND REF_CLK- REF_CLK+ GND AUX_CLK- AUX_CLK+ GND

15080-0000 Rev 3.0


A.3 Pins P1 & J1

Table A-2: P1 & J1


Connector P1 follows the VITA 65 defined pins where:• DP01-x: 4x port connected to IOPE0

• DP02-x: second 4x port connected to IOPE0

• DP03-x: 4x port connected to IOPE1

• DP04-x: second 4x port connected to IOPE1

• Boxes in green above are VITA46 (OpenVPX) defined control signals.

The user-defined portion of the connector is defined by Annapolis Micro Systems, Inc as:• UDx: These pins are not yet used and should be left unconnected

Note: Signal direction is named with respect to the VPX payload card, so RX is from backplane to VPX payload card while TX is from payload card to backplane.

Plug-InModule P1


Even Odd Even Odd

Bplane J1 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

Dat

a P

lan

eP

ort

1

GDiscrete1 GND GND-J1 DP01-T0- DP01-T0+ GND GND-J1 DP01-R0- DP01-R0+

2 GND DP01-T1- DP01-T1+ GND-J1 GND DP01-R1- DP01-R1+ GND-J1 GND

3 P1-VBAT GND GND-J1 DP01-T2- DP01-T2+ GND GND-J1 DP01-R2- DP01-R2+


5

Dat

a P

lane

Por

t 2

SYS- GND GND-J1 DP02-T0- DP02-T0+ GND GND-J1 DP02-R0- DP02-R0+


7 Reserved GND GND-J1 DP02-T2- DP02-T2+ GND GND-J1 DP02-R2- DP02-R2+


9

Dat

a P

lane

Por

t 3

UD0 GND GND-J1 DP03-T0- DP03-T0+ GND GND-J1 DP03-R0- DP03-R0+


11 UD1 GND GND-J1 DP03-T2- DP03-T2+ GND GND-J1 DP03-R2- DP03-R2+


13

Dat

a P

lane

Por

t 4

UD2 GND GND-J1 DP04-T0- DP04-T0+ GND GND-J1 DP04-R0- DP04-R0+


15Maskable

Reset*GND GND-J1 DP04-T2- DP04-T2+ GND GND-J1 DP04-R2- DP04-R2+


15080-0000 Rev 3.0


A.4 Pins P2 & J2

Table A-3: P2 & J2


Note: Row G defined pins added in VITA65 Rev 2.1 Draft candidate

Connector P2 follows the VITA 65 defined pins where:• EP[07:00] lanes go to PCI-E switch as 8x bus

• EP[15:08] lanes go to PCI-E switch as a second 8x bus

• AXresetx are new resets added to OpenVPX 2.0 spec draft. Functionality TBD

• EPclockx are new differential clocks added to OpenVPX 2.0 spec draft. Functionality TBD

• ETH_LED1*: LED for 1000BASE-X Ethernet to PowerPC. On=1GbE, Off=10/100MbE

• ETH_LED0*: LED for 1000BASE-X Ethernet to PowerPC. On=Link, Blink=Activity


Plug-InModule P2


Even Odd Even Odd

Backplane J2 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

X16

usi

ng [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

AXreset1* GND GND-J2 EP00-T- EP00-T+ GND GND-J2 EP00-R- EP00-R+

2 GND EP01-T- EP01-T+ GND-J2 GND EP01-R- EP01-R+ GND-J2 GND

3 AXreset2* GND GND-J2 EP02-T- EP02-T+ GND GND-J2 EP02-R- EP02-R+


5

x4 u

sing

EPclock1- GND GND-J2 EP04-T- EP04-T+ GND GND-J2 EP04-R- EP04-R+


7 EPclock1+ GND GND-J2 EP06-T- EP06-T+ GND GND-J2 EP06-R- EP06-R+


9

x8 u

sing

[15:

8]

x4 u

sing

EPclock2- GND GND-J2 EP08-T- EP08-T+ GND GND-J2 EP08-R- EP08-R+


11 EPclock2+ GND GND-J2 EP10-T- EP10-T+ GND GND-J2 EP10-R- EP10-R+


13

x4

ETH_LED1 GND GND-J2 EP12-T- EP12-T+ GND GND-J2 EP12-R- EP12-R+


15 ETH_LED0 GND GND-J2 EP14-T- EP14-T+ GND GND-J2 EP14-R- EP14-R+


15080-0000 Rev 3.0


A.5 Pins P3 & J3Table A-4: Pins P3 & J3


Connector P3 is completely user defined. They are defined by Annapolis Micro Systems, Inc as: • USR[05:00]-x: LVDS connections to IOPE0

• USR[07:06]-x: LVDS connections to CPE0 (Not Connected for WILDSTAR A5 2PE FPGA boards)

• USR[13:08]-x: LVDS connections to IOPE1

• USR[15:14]-x: LVDS connections to CPE0 (Not Connected for WILDSTAR A5 2PE FPGA boards)

• USR_SE[3:0]: 2.5V single ended connections to IOPE0

• USR_SE[7:4]: 2.5V single ended connections to IOPE1


Plug-InMod P3


Even Odd Even Odd

Bplane J3

Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

Use

r D

efin

ed

USR_SE0 GND GND-J3 USR00-T- USR00-T+ GND GND-J3 USR00-R- USR00-R+

2 GND USR01-T- USR01-T+ GND-J3 GND USR01-R- USR01-R+ GND-J3 GND

3 USR_SE1 GND GND-J3 USR02-T- USR02-T+ GND GND-J3 USR02-R- USR02-R+














15080-0000 Rev 3.0


+

+

+

+

1

1 +

1

1

1

1 +

1

A.6 Pins P4 & J4Table A-5: P4 & J4


Connector P4 follows the VITA 65 defined pins where:• CPtp01-Dx is 1000Base-T port to PowerPC

• CPutp01-T and CPutp02 are 1000Base-X ports to PowerPC

• “Unused” pins are unused by Annapolis Micro Systems, Inc.

The user defined portion of the connector is defined by Annapolis Micro Systems, Inc as:• SATA_x: Connected to PowerPC

• USBx: Connected to PowerPC

• UART0_RX and UART0_TX are Processor UART connections (RS232).

• UARTx/RS485x port can be either two RS232 UART ports without flow control or one RS485/RS422 port.

• RTMx-x connections vary by board as follows:

• 1. WSA5 3PE 1932 FPGA Board: RTM1-x and RTM0-x both connected to CPE0

• 2. WSA5 3PE 1517 FPGA Board: RTM0-x connected to CPE0

• 3. WSA5 2PE 1932 FPGA Boards: RTM0-x connected to IOPE0 and RTM1-x connected to IOPE1

• 4. WSA5 2PE 1517 FPGA Boards: Not Connected

• 5. Storage Card: RTM0-x connected to Storage FPGA

• IRIG_IN: Analog input for IRIG-B time code

• 2.5V: For low power RTM logic

Plug-InMod P4


Even Odd Even Odd

Bplane J4 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

Use

r D

efin

ed

UART2TX/RS485TX+

GND GND-J4 RTM0-T0- RTM0-T0+ GND GND-J4 RTM0-R0- RTM0-R0

2 GND RTM0-T1- RTM0-T1+ GND-J4 GND RTM0-R1- RTM0-R1+ GND-J4 GND

3UART1TX/RS485X-

GND GNDJ4 RTM0-T2- RTM0-T2+ GND GND-J4 RTM0-R2- RTM0-R2


5 UART0_RX GND GND-J4 RTM1-T0- RTM1-T0+ GND GND-J4 RTM1-R0- RTM1-R0


7 UART0_TX GND GND-J4 RTM1-T2- RTM1-T2+ GND GND-J4 RTM1-R2- RTM1-R2


9 2.5V GND GND-J4 USB0- USB0+ GND GND-J4 BPCLK- BPCLK+

0 GND SATA_TX- SATA_TX+ GND-J4 GND SATA_RX- SATA_RX+ GND-J4 GND

1

2 U

TP IRIG_IN GND GND-J4 CPutp02-T- CPutp02-T+ GND GND-J4 CPutp02-R- CPutp02-R

2 GND CPutp01-T- CPutp01-T+ GND-J4 GND CPutp01-R- CPutp01-R+ GND-J4 GND

3

Con

trol

Pla

ne2

TP

s

UART2RX/RS485RX+

GND GND-J4 Unused Unused GND GND-J4 Unused Unused

4 GND Unused Unused GND-J4 GND Unused Unused GND-J4 GND

5UART1RX/RS486RX-

GND GND-J4 CPtp01-DB- CPtp01-DB+ GND GND-J4 CPtp01-DA- CPtp01-DA

6 GND CPtp01-DD- CPtp01-DD+ GND-J4 GND CPtp01-DC- CPtp01-DC+ GND-J4 GND

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• BPCLK: LVDS or 2.5V SE input to clock mux circuit. If using as SE input, use “+” side of pair. If front panel SMA configured for clock input then this pin is Not Connected.

Note:Signal direction is named with respect to the VPX payload card, so RX is from backplane to VPX payload card while TX is from payload card to backplane.

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A.7 Pins P5 and J5

Table A-6: P5 & J5

Connector P5 follows the VITA 65 defined pins where:• WILDSTAR A5 3PE for Open VPX Boards:

• EP[23:16] is an 8x connection to CPE0.


• WILDSTAR A5 2PE for Open VPX Boards:

• EP[23:16] is an 8x connection to PCI Express Switch. It can be only be PCI Express Gen 1/2/3.

• EP[31:24] is an 8x connection to PCI Express Switch. It can be only be PCI Express Gen 1/2/3.

• WILDSTAR 7 for Open VPX Boards:



The user-defined portion of the connector is defined by Annapolis Micro Systems, Inc as: • STAPx: Signal Tap JTAG Select bits. Functionality is reserved.

• ~HALTRST: Used with JTAG P0 bits for processor debugging

• I2Cx: Used for RTM control and identification

• USBPEN: Output to backplane which enabled power to USB cable when high

• USBOC: Input from backplane which indicated USB over current condition


Plug-InModule P5


Even Odd Even Odd

Backplane J5 Row i Row h Row g Row f Row e Row d Row c Row b Row a

1

X16

usi

ng [1

5:0]

x8 u

sing

[7:0

]

x4 u

sing

STAP0 GND GND-J2 EP16-T- EP16-T+ GND GND-J2 EP16-R- EP16-R+


3 STAP1 GND GND-J2 EP18-T- EP18-T+ GND GND-J2 EP18-R- EP18-R+


5

x4 u

sing

~HALTRST GND GND-J2 EP20-T- EP20-T+ GND GND-J2 EP20-R- EP20-R+


7 I2CDAT GND GND-J2 EP22-T- EP22-T+ GND GND-J2 EP22-R- EP22-R+


9

x8 u

sing

[15:

8]

x4 u

sing

I2CCLK GND GND-J2 EP24-T- EP24-T+ GND GND-J2 EP24-R- EP24-R+


11 ~I2CINT GND GND-J2 EP26-T- EP26-T+ GND GND-J2 EP26-R- EP26-R+


13

x4

USBPEN GND GND-J2 EP28-T- EP28-T+ GND GND-J2 EP28-R- EP28-R+


15 USBOC GND GND-J2 EP30-T- EP30-T+ GND GND-J2 EP30-R- EP30-R+


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A.8 Pins P6 & J6This connector is currently reserved for supporting VITA 66 (Optical Interconnect on VPX) or VITA 67 (Analog/RF Interconnect).

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87WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix B: OpenVPX Flash Utility

Appendix B: OpenVPX Flash Utility

88 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix B: OpenVPX Flash Utility

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89WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix B: OpenVPX Flash Utility

WILDSTAR A5 and WILDSTAR 7 OpenVPX boards provide a DIP switch to write-protect non-volatile memory on the board. Some devices on the board require a software utility to enable or disable write-protection using the DIP switch.

The following sequence must be used to lock the non-volatile memory on the board:

1. Run the ws_flash_tool.sh utility, using the “lock” argument, to prepare the flash parts for locking:

# ws_flash_tool.sh lockLocking SPI NOR Flash parts on the board

2. Put the DIP switch in the write-protect position.

The following sequence must be used to unlock the non-volatile memory on the board:

1. Run the ws_flash_tool.sh utilty, using the “unlock” argument, to prepare the flash parts for locking:

# ws_flash_tool.sh unlockUnlocking SPI NOR Flash parts on the board

2. Put the DIP switch in the non-write-protect position.

The utility can also be used to query the current state of the SPI flash and the DIP switch. The following is an example of how to use the utility to report this information:

# ws_flash_tool.sh statusOn-Board Flash Write Enabled (Not Write Protected, default)

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91WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix C: Statement of Volatility

Appendix C: Statement of Volatility

92 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix C: Statement of Volatility

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93WILDSTAR A5 for OpenVPX Hardware Reference Manual

Appendix C: Statement of VolatilityMarch 2, 2015

To Whom it May Concern,

Here are details of the memory volatility of our WILDSTAR A5 and WILDSTAR 7 for OpenVPX mainboards:

There is volatile SRAM and DRAM on WILDSTAR A5 and WILDSTAR 7 for OpenVPX mainboards that will be cleared whenever power is cycled to the board.

These mainboards also have non-volatile memory, which, in come cases can be write-protected, and in all cases can be erased for sanitization purposes. This non-volatile memory is documented below.

In a WILDSTAR A5 or WILDSTAR7 for OpenVPX chassis, the non-volatile memory can be write-protected in one of two ways: (1) chassis-level protection and (2) board-level protection. These are described below. When the flash is write-protected, it can still be read, so it is effectively read-only.

1. In the chassis there is an OpenVPX-defined flash protect backplane signal. This signal is called Non-Volatile Memory Read Only, or NVMRO. NVMRO will write-protect all protect-able non-volatile flash in the chassis if enabled. Sometimes this is enabled with a jumper in the chassis backplane and sometimes it is hardwired. NVMRO is electrically pulled up on the backplane which defaults to a write-protect state when left open. Generally a jumper would be populated to drive NVRMO low to allow protect-able flash to be written.

2. Board-level flash protection is enabled by setting the “Flash Write Enable” DIP switch to “OFF” on the mainboard. This is controlled with Switch 3, position 2 on WILDSTAR 7 baseboards and Switch 1, position 2 on WILDSTAR A5 baseboards. This will write-protect flash locally and not affect state of backplane NVMRO.

Note:If flash is write-protected, then the WILDSTAR A5 and WILDSTAR 7 for OpenVPX can be used with an NFS mount and does not need to have any data stored locally in flash. In this case, the boot option and network configuration information should be configured before flash is write-protected.

WILDSTAR A5 and WILDSTAR 7 for OpenVPX mainboards also contain some non-volatile memories which can be write-protected only after being locked via software.

• PowerPC Boot Flash: 16MB SPI NOR Flash. Micron Part Number N25Q128A11EF840E. A software utility to set the lock bits must be run prior to write-protecting the flash using one of the two methods above. See “Appendix A: WILDSTAR A5 and WILDSTAR 7 for OpenVPX Flash Utility” for instructions to lock, unlock and verify lock of this SPI flash. To overwrite all factory partitions and return board to factory shipping state, the update utility should be run with the option to force updates (see sanitization procedure).

• PowerPC Solid State Disk (SSD): 4GB SATA SSD. Greenliant Part Number GLS85LS1004P-S-I-F2JE. Connected to PowerPC SATA interface. To return to default factory state, follow sanitization procedure.

• PCIe Switch Configuration EEPROM. 16KB SPI EEPROM. Microchip PN 25AA128-I/ST. To return to default factory state, follow sanitization procedure.

WILDSTAR A5 and WILDSTAR 7 for OpenVPX mainboards contain the following non-volatile memories which are not write-protected but can be cleared for sanitization purposes:

• 256 KB EEPROM: ST M24M02-DRMN6TP. Connected to Module Management Controller (MMC). This is not protected by flash protect but can be cleared with the OEM IPMI “eeprom erase” command. It can only be written with OEM “write eeprom” command or standard IPMI write FRU command.

If you have any additional questions about our products, please don’t hesitate to call.

Sincerely,

Paul KowalewskiGeneral Manager

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94 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix C: Statement of Volatility

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95WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix D: OpenVPX Board Restore Procedure

Appendix D: OpenVPX Board Restore Procedure

96 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix D: OpenVPX Board Restore Procedure

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97WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix D: OpenVPX Board Restore Procedure

The WILDSTAR A5 and WILDSTAR 7 board restore procedure can be used to restore boards to a factory default configuration, or upgrade a board to a new baseboard software release. This procedure will discard all data on the SSD, it is recommended that files valuable to the user be backed up before running this procedure. Please note that the board must not be interrupted, or powered off during the procedure. If the procedure is interrupted then the board may end up in a non-functional state.

Note:This chapter applies to baseboards with U-Boot version 1.16-2015.05.29 or greater. The version of U-Boot can be observed from the serial console on initialization. If the version is not 1.16-2015.05.29 or greater, then the wild factory flash recovery tool must be run on the board before the restore procedure is executed. If the baseboard version is 1.15.0 or greater, refer to Chapter 8: Serial Board Configuration Utility for instructions on how to run the wild factory flash recovery tool. If the version is less than 1.15.0, please call the WILDSTAR Technical Support team at (410) 841-2514, fax at (410) 841-2518, or send e-mail to [email protected].

1. Obtain the restore image:• The restore image can be found on the CD shipped with the board, example filename:

wsa5vpx.baseboard-1.15.0-baseboard.wsa5vpx.tar.gz• The restore image can also be obtained from the WILDSTAR Technical Support Team at (410) 841-2514, fax

at (410) 841-2518, or send e-mail to [email protected]

2. Connect the serial console cable to the board. Refer to section 3.2.2.1.3 to verify that the switches are configured properly for console access. The default serial port settings for the console interface are: 57600 bps, 8 data bits, 1 stop bit, no parity, and Xon/Xoff flow control.

3. Power the board on, and press the space bar key to stop the autoboot countdown in U-Boot.

4. Note that the version of U-Boot has to be 1.16-2015.05.29 or greater.

5. At the U-Boot command prompt, type the following command and press enter: run ramdisk_boot

6. Login to the board with username: root, and password: password

7. Copy the restore image onto the board, this step will require network access. In the example command below, the file was copied from a server on the local network with IP address 192.168.1.100.

scp [email protected]:/home/myusername/restore/wsa5vpx.baseboard-1.15.0-baseboard.wsa5vpx.tar.gz.

8. Execute the command below to start the restore procedure. This command will take approximately 20 minutes to complete, and must not be interrupted. If the procedure is interrupted the board may end up in a non-functional state.

restore_system wsa5vpx.baseboard-1.15.0-baseboard.wsa5vpx.tar.gz

9. When the process is complete, the console will request that the user run the reboot command. Run the following command to complete the restore procedure and reboot the board: reboot

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98 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix D: OpenVPX Board Restore Procedure

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99WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix E: OpenVPX Disk Sanitization Procedure

Appendix E: OpenVPX Disk Sanitization Procedure

100 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix E: OpenVPX Disk Sanitization Procedure

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WILDSTAR A5 and WILDSTAR 7 boards provide the ability to erase and sanitize the SSD and flash module.

The secure erase operation sends a secure erase ATA instruction to the SSD's firmware, and the firmware erases all blocks on the disk. This procedure takes approximately 5 minutes to complete.

The sanitization procedure consists of 5 steps, outlined below. This is a more comprehensive procedure, which makes use of secure erase also. This procedure takes approximately 15 minutes to complete.

1. Secure erase the whole disk.

2. Fill the whole disk with random data.

3. Fill the whole disk with random data one more time.

4. Secure erase the whole disk again.

5. Fill the whole disk with fixed character pattern of 0x55.

Note:This chapter applies to baseboards with U-Boot version 1.16-2015.05.29 or greater. The version of U-Boot can be observed from the serial console on initialization. If the version is not 1.16-2015.05.29 or greater, then the wild factory flash recovery tool must be run on the board before the restore procedure is executed. If the baseboard version is 1.15.0 or greater, refer to Chapter 8: Serial Board Configuration Utility for instructions on how to run the wild factory flash recovery tool. If the version is less than 1.15.0, please call the WILDSTAR Technical Support team at (410) 841-2514, fax at (410) 841-2518, or send e-mail to [email protected].

E.1 Sanitize the Flash Disk

Note:Please refer to section MMC Configuration Selects (REFDES: SW1) to verify that the switches on the board are configured correctly, and the flash device is not write protected before proceeding.

To sanitize the flash, follow the instructions in Serial Board Configuration Utility, to run the Wild Factory Flash Recover procedure. This procedure will erase all blocks of data on the flash device, and restore the original factory settings to the disk.

E.2 Secure Erase the SSD

Note:Please refer to section MMC Configuration Selects (REFDES: SW1) to verify that the switches on the board are configured correctly, and the SSD is not write protected before proceeding.

The user can secure-erase the contents of the SSD to permanently destroy all data on the disk. This procedure is destructive, and it should be used with caution. All valuable data should be backed up prior to running this procedure, as it is unrecoverable.

1. Connect the serial console cable to the board. Refer to section PowerPC UART Selects (REFDES: SW4) to verify that the switches are configured properly for console access. The default serial port settings for the console inter-face are: 57600 bps, 8 data bits, 1 stop bit, no parity, and Xon/Xoff flow control.

2. Power the board on, and press the space bar key to stop the autoboot countdown in U-Boot.

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WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix E: OpenVPX Disk Sanitization Procedure

3. Note that the version of U-Boot has to be 1.16-2015.05.29 or greater.

4. At the U-Boot command prompt, type the following command and press enter:

run ramdisk_boot


6. Execute the following command from the command prompt. This command will send the secure-erase command to the firmware on the SSD, and takes about 5 minutes to complete.

secure_erase_ssd

7. Once the secure erase is complete, the SSD will not be functional or have any data on it.

8. If the user would like to restore that SSD to the factory state, the procedure in OpenVPX Board Restore Procedure can be followed to restore the board to a functional state.

E.3 Sanitize the SSD

Note:Please refer to section MMC Configuration Selects (REFDES: SW1)to verify that the switches on the board are configured correctly, and the SSD is not write protected before proceeding.

The user can run this procedure to permanently destroy all data on the SSD, and overwrite it multiple time for added security. This procedure is destructive, and it should be used with caution. All valuable data should be backed up prior to running this procedure, as it is unrecoverable.

1. Connect the serial console cable to the board. Refer to section PowerPC UART Selects (REFDES: SW4) to ver-ify that the switches are configured properly for console access. The default serial port settings for the console interface are: 57600 bps, 8 data bits, 1 stop bit, no parity, and Xon/Xoff flow control.

2. Power the board on, and press the space bar key to stop the autoboot countdown in U-Boot. Note that the version of U-Boot has to be 1.16-2015.05.29 or greater.

3. At the U-Boot command prompt, type the following command and press enter:

run ramdisk_boot


5. Execute the following command from the command prompt. This command will send the secure-erase command to the firmware on the SSD, and takes about 5 minutes to complete.

sanitize_ssd

6. Once the sanitization is complete, the SSD will not be functional or have any data on it.

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7. If the user would like to restore that SSD to the factory state, the procedure in OpenVPX Board Restore Procedure can be followed to restore the board to a functional state.

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104 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix E: OpenVPX Disk Sanitization Procedure

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105WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix F: Security Enhanced Linux

Appendix F: Security Enhanced Linux

106 WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix F: Security Enhanced Linux

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The environment that ships with WILDSTAR A5 for OpenVPX and WILDSTAR 7 for OpenVPX products is capable of running Security Enhanced Linux (SELinux) policies. SELinux provides a security layer, which is enforced at the kernel and file system levels, that is capable of enforcing access control security policies. The goal of this appendix is to provide guidance on enabling and disabling SELinux on WILDSTAR A5 for OpenVPX and WILDSTAR 7 for OpenVPX products. For more specific information about SELinux please see http://selinuxproject.org/.

F.1 Checking PrerequisitesThe SELinux feature is available as of kernel version 1.04 and file system version 1.16.0. Below is example output which shows how to discover both versions:

root@wsa5vpx_48sio_3pe_1000200:~# cat /etc/rstversion 1.16.048b4f711f6ef3bf63a41dd52405a196df3eee19c

root@wsa5vpx_48sio_3pe_1000200:~# uname -r | cut -d '-' -f 31.04

If the versions of your system are prior to the required versions above, the system must be updated before SELinux can be enabled. Refer to OpenVPX Board Restore Procedure for details on updating to a newer software set with SELinux support.

When enabling or disabling SELinux support it is required that the target system have read and write access to the on board storage devices. Ensure that the target board is in a system that is not currently write protected and refer to MMC Configuration Selects (REFDES: SW1) to ensure the on board switches are configured correctly to disable write protection.

It is recommended that the ssh keys of a system capable of connecting to the target board via SSH be copied to the target, at least temporarily, for the sake of troubleshooting login issues. This can be done with a command similar to the following (the syntax and availability of this command will vary based on operating system):

ssh-copy-id root@<IP address of board where you will be enabling SELinux>

Once copied, the user should be able to SSH into the target board from the client system (the system on which you ran the ssh-copy-id command) without entering a password.

Additionally, it is also recommended, again for the sake of troubleshooting, that a serial console connection be available.

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WILDSTAR A5 for OpenVPX Hardware Reference ManualAppendix F: Security Enhanced Linux

F.2 Enabling SELinuxThe state of SELinux can be controlled by a configuration file on the file system of the target board located at /etc/selinux/config. By default, this configuration file lists SELinux as “disabled” as seen below:

SELINUX=disabled

Unless you are confident in your SELinux policy configuration, it is recommended that the above line be changed from “disabled” to “permissive”. This will effectively enable SELinux, but using a permissive nature, so users will still maintain full access to the system, however, the SELinux layer will warn of access violations it would block if it were running in “enforcing” mode. After changing the configuration of SELinux to “permissive” the system must be rebooted. During the reboot the SELinux layer will recognize this is the first time the system has been booted with SELinux enabled and will proceed to relabel the file system with the appropriate security context attributes. This process will take some time, usually on the order of minutes, after which the system will automatically reboot.

Once the system comes up after the relabeling step, you may attempt to log in as the root user. You will be prompted to change your password at this point, relabeling the file system will expire the root password. After logging in it is advised that you check the SELinux audit logs, which can be found at /var/log/audit/audit.log, for any access violations that would prevent the system from booting if in enforcing mode. After making the desired policy modifications to comply with your security requirements, the system can be placed into “enforcing” mode if required. This can be done by editing the “SELINUX=” property in the SELinux configuration file at /etc/selinux/config to read “SELINUX=enforcing”

Note:A SELinux policy module named “annapmicro” has been added to allow a vanilla file system to boot correctly with SELinux in “enforcing” mode. The binary policy files as well as the source for the policy can be found in /opt/annapmicro/selinux/policy on the target board's file system.

F.2.1 Disabling SELinuxTo disable SELinux the “SELINUX=” property in the configuration file at /etc/selinux/config must be edited as below:

SELINUX=disabled

After editing the configuration file the system must be rebooted for the changes to take effect.

F.2.2 Re-Enabling SELinuxIf SELinux had previously been enabled, was disabled and you wish to enable it again, the file system must be relabeled with the appropriate security attributes. The first step is to re-enable SELinux by editing the “SELINUX=” property in the /etc/selinux/config file to be either “permissive” or “enforcing”. Next, to ensure the file system is relabeled on boot, you can run the following command from the target system:

root@wsa5vpx_48sio_3pe_1000200:~# /sbin/fixfiles onbootSystem will relabel on next boot

The final step is to reboot the system for the changes to take effect.

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mailto:root@wsa5vpx_48sio_3pe_1000200


F.3 Troubleshooting SELinuxProblem: Locked out of system after putting SELinux into “enforcing” mode.Solution: To proceed a serial connection is required.

1. Reboot the board.

2. During the UBOOT countdown, press the space bar to interrupt normal startup.

3. Follow the console steps below to boot the system with SELinux in “permissive” modePress ' ' to stop autoboot, any key to boot: 4=> printenv scsiargsscsiargs=setenv bootargs root=/dev/$scsi_root_dev ro=> setenv scsiargs 'setenv bootargs root=/dev/$scsi_root_dev ro enforcing=0'=> boot

4. Examine security violation logs in /var/log/audit/audit.log as well as serial console output to determine which access violation prevented boot while in “enforcing” mode.

5. Once making policy adjustments or otherwise correcting the problem, rebooting the system will put SELinux back into “enforcing” mode.

Problem: System does not function even with SELinux in permissive mode.Solution: To proceed a serial connection is required.

1. Reboot the board.

2. During the UBOOT countdown, press the space bar to interrupt normal startup.

3. Follow the console steps below to boot the system with SELinux disabledPress ' ' to stop autoboot, any key to boot: 4=> printenv scsiargsscsiargs=setenv bootargs root=/dev/$scsi_root_dev ro=> setenv scsiargs 'setenv bootargs root=/dev/$scsi_root_dev ro selinux=0'=> boot

4. Correct issues that prevented the system from booting properly (possibly by examining the security access exceptions printed in the failing boot's console output and making policy adjustments).

5. Once making desired changes to correct the problem, the system must be relabeled since the system is currently booted with SELinux disabled. Refer to section Re-Enabling SELinux for details.

Problem: No longer able to log in as non-root users after putting SELinux into “enforcing” mode.Solution: To proceed it is assumed the “root” user has access to the system; if not, please refer to the previous problem scenarios of being locked out of the system after enabling SELinux.

1. Log into the system using the “root” user while SELinux is enabled and in either “permissive” or “enforcing” modes.

2. Reset the affected user's password using the “passwd” command.

3. Attempt to log in as the affected user.

Problem: Kernel panics and system halts after enabling SELinux.Solution: Ensure that the system is not write-protected. SELinux requires write-protect to be disabled in order to relabel the file system with the appropriate security context attributes.

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Documents

WILDSTAR A5 for VPX - Intel · Unless specifically indicated otherwise, references throughout this manual to “WILDSTAR A5 for Open-VPX” pertain to both the WILDSTAR A5 2PE for