What Does it Take to Build a Complete Test Flow for 3-D IC?edpsieee.ieeesiliconvalley.org/edp2012/Papers/3D 4... · 2019-04-14 · What Does it Take to Build a Complete Test Flow

What Does it Take to Build a Complete Test Flow for 3-D IC?

Brion Keller, Bassilios Petrakis, Cadence Thanks to : Sandeep Goel, TSMCEDPS, Monterey, CA April 5-6, 2012

2 © 2012 Cadence Design Systems, Inc. All rights reserved.

• TSMC– Ashok Mehta

• imec– Erik Jan Marinissen

• Cadence– Sergej Deutsch (now at Duke Univ.)– Vivek Chickermane, – Subhasish Mukherjee

Acknowledgements


• 3D stacking of ICs is a hot DFT topic– Using TSVs as die interconnects has many advantages

• 3D DFT is needed to do modular testing of– Die internal logic – Die interconnects

• Presentation focuses on– Modular testing techniques of 3D stacking ICs with TSV– A tool flow for automatic insertion of 3D wrappers– Method can be extended to other interconnect types (e.g.,

interposers)

Purpose


• Introduction• 3D-DFT requirements

• 3D-DfT architecture• 3D wrapper generation flow• Results• Conclusions

Presentation outline


• 3D chip stacking with wire-bonds– Heterogeneous technologies– Dense integration, small footprint

1. introduction – Through Silicon Vias (TSVs)

board

board

System-in-Package (SiP)

TSV-Based 3D-SIC

• Through-Silicon Vias Metal vias that provide interconnectsfrom front-side to back-sidethrough silicon substrate

• TSV benefits

– Even denser integration

– High density, low capacitance

– Increased bandwidth

– Increased performance

– Lower power dissipation

– Lower manufacturing cost?


• Pre-Bond Test– Focus on die-internal circuitry– Original thick or thinned-down wafer– Probe access at DUT– Probe on micro-bumps or dedicated pads

2. 3D-DFT requirements Test access distinctly different

die

• Mid-Bond / Post-Bond / Final Tests– Focus on interconnects and die-internal circuitry

– Test access (probe or socket) at bottom die

– Require DfT to propagate teststimuli/responses up/down through stack

– Requirements– Modular test: core, die, interconnect

– TestTurn: test up till this die

– TestElevator: test higher-up die

bottom die

middle die

top die


• Example functional design

• ≥2 stacked dies, possibly core-based

• Inter-connect: TSVs

• Extra-connect: pins

3. 3D-DFT architecture

Die 1

Die 2

Die 3

Core 3

Core 2.1

Core 1.1 Core 1.2 Core 1.3

Core 2.2

TS

V

TS

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pin pin pin pin


• Example functional design– ≥2 stacked dies, possibly core-based

– Inter-connect: TSVs

– Extra-connect: pins

• Example existing design for test

– Core: internal scan, TDC, LBIST, MBIST; IEEE 1500 wrappers, TAMS

– Stack product: IEEE std 1149.1


Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC

IEEE 1149.1 Boundary Scan

IEEE 1500 IEEE 1500IEEE 1500

IEEE 1500

IEEE 1500

IEEE 1500

TS

V

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pin pinpin pin pin pin



Board

Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

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Vpad

pad

pad

pad

Example functional design

• ≥2 stacked dies, possibly core-based• Inter-connect: TSVs

• Extra-connect: pins

Example Existing Design-for-Test• Core: internal scan, TDC, LBIST, MBIST;

IEEE 1500 wrappers, TAMs• Stack product: IEEE Std 1149.1

3D-DFT ArchitectureTest wrapper per die

• Based on IEEE 1149.1 or 1500

• Two entry/exit points per die:1. Pre-bond : extra probe pads2. Post-bond : extra TSVs

[Marinissen et al. – VTS’10 / 3DIC’10]


• Pre-bond– Die test

• Post-bond– Die 1/2/3 test– Interconnect 1-2 + 2-3

• Post-packaging– Serial debug

3. 3D-DFT architecture Modes of operation

Die 3

Core 3

BIS

T

IEEE 1500

pad pad






Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

TS

V

TS

V

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TS

Vpin pinpin pin pin pin

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TS

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TS

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TS

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TS

V

TS

V

TS

V

TS

Vpad

pad

pad

pad

inte

sttu

rn






Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

TS

V

TS

V

TS

V

TS

V

TS

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TS

V

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TS

Vpad

pad

pad

pad

bypa

ssel

evat

ein

test

turn






Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

TS

V

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V

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TS

Vpad

pad

pad

pad

bypa

ssel

evat

eby

pass

elev

ate

inte

sttu

rn






Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

TS

V

TS

V

TS

V

TS

V

TS

V

TS

V

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TS

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TS

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Vpad

pad

pad

pad

exte

stel

evat

eex

test

elev

ate

exte

sttu

rn


Board





Die 1

Die 2

Die 3

Core 3

Core 2.1


Core 2.2

BIS

TTD

C

TDC

TDC

TDC



IEEE 1500

IEEE 1500

IEEE 1500

TS

V

TS

V

TS

V

TS

V

TS

V

TS

V

TS

V

TS

V

TS

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TS


TS

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TS

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TS

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TS

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TS

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TS

Vpad

pad

pad

pad


3. 3D-DFT architecture Schematic view: wrapped die

Die x

bypassbypass

WSI

WSC

WSO

n

1

6

1

n

WPI*

WPO*

m

WSOs

WSCs

WSIs

WPOs

WPIs

n

1

6

1

n

bypassbypass

WIRWIR

m

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register

scan chainscan chain

switch box

switch box

switch box

switch box


to/from top die

Parallel T

AM

to/from bottom

die

Parallel T

AM

Serial T

AM

Serial T

AM


• Serial Test Access Mechanism (TAM)– Instructions– Low-bandwidth test data– Typical usage:

board-/system-level debug


Die x

bypassbypass

WSI

WSC

WSO

n

1

6

1

n

WPI*

WPO*

m

WSOs

WSCs

WSIs

WPOs

WPIs

n

1

6

1

n

bypassbypass

WIRWIR

m

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register


switch box

switch box

switch box

switch box


to/from top die

Parallel T

AM

to/from bottom

die

Parallel T

AM

Serial T

AM

Serial T

AM


• Serial Test Access Mechanism (TAM)– Instructions– Low-bandwidth test data– Typical usage:

board-/system-level debug

• Parallel TAM– High-bandwidth test data– Typical usage:

– Volume production testing in semiconductor factory


Die x

bypassbypass

WSI

WSC

WSO

n

1

6

1

n

WPI*

WPO*

m

WSOs

WSCs

WSIs

WPOs

WPIs

n

1

6

1

n

bypassbypass

WIRWIR

m

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register


switch box

switch box

switch box

switch box


to/from top die

Parallel T

AM

to/from bottom

die

Parallel T

AM

Serial T

AM

Serial T

AM


Die 1

bypassbypass

WSI

WSC

WSO

n

1

6

1

n

WPI*

WPO*

bypassbypass

WIRWIR

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register


switch box

switch box

switch box

switch box


Die N

bypassbypass

WSI

WSC

WSO

n

1

6

1

n

WPI*

WPO*

m

bypassbypass

WIRWIR

m

Wrap

per B

oun

dary R

egisterW

rapp

er Bou

nd

ary Register


switch box

switch box

switch box

switch box


Bo

un

dary S

can Reg

isterB

ou

nd

ary Scan R

egister

switch box

switch box

TDI

TCK

TMS

TRSTN*

TDO

Adapter

1149.1

WSIs

WPIs

n

1

6

1

n

3. 3D-DFT architecture Schematic view: stack

Functional I/O

s / WP

I/WP

O


• Implemented instructions decided at design-time– Different instructions enable different test access paths

• Flexible test scheduling decided at test-time– Inclusion/exclusion of tests for different phases of test flow– Reordering of tests (reject-oriented analysis, abort-on-first-fail)

3. 3D-DFT architecture Flexible instruction set-up

Serial Prebond TurnIntest

Postbond

Elevator

Turn

BypassParallel

Intest

Extest

Bypass


3. 3D-DFT architecture Test mode set-up example

ParallelPostbondBypassElevator

Die 2

WSI

WSC

WIR2

WSO

scan chain

WBR

scan chain

bypass

bypass

WPI*

WPO*

switch box

Die 3(top)

WIR3

scan chain

WBR

scan chain

switch box

bypass

bypass switch box

Die 1(bottom)

TDI

WIR1

scan chain

WBR

scan chain

switch box

bypass

bypass switch box

1149.1TCK

TMS

TRSTN*

TDO

WPI*

WPO*

switch box

n

1

6

1

n

WSI

WSC

WSO

WPI*

WPO*

n

1

6

1

n

Note: Figure abstracts from functional circuitry and only shows DfT features

WIR2 WIR3WIR1

1149.1

scan chain

WBR

scan chain

bypass

ParallelPostbondIntestTurn

ParallelPostbondBypassTurn


• DfT Insertion with Encounter RTL Compiler

4. 3D wrapper generation flow

DesignDesign

LibraryLibrary

Wrapped DesignWrapped Design

WIR InsertionWIR Insertion

Wrapper Cell InsertionWrapper Cell Insertion

MultimodeScan Chain Configuration

MultimodeScan Chain Configuration

JTAGInsertion

JTAGInsertion

User-definedParameters


Bypass Register InsertionBypass Register Insertion

3D Wrapper Insertion 3D Wrapper Insertion

JTAG InsertionJTAG Insertion

TAP Controller InsertionTAP Controller Insertion

Boundary Cell InsertionBoundary Cell Insertion

JTAG-to-1500JTAG-to-1500


DesignDesign

LibraryLibrary

Wrapped DesignWrapped Design

WIR InsertionWIR Insertion

Wrapper Cell InsertionWrapper Cell Insertion

Multi-ModeScan Chain Configuration

Multi-ModeScan Chain Configuration

JTAGInsertion

JTAGInsertion



Bypass Register InsertionBypass Register Insertion

3D Wrapper Insertion (RC)3D Wrapper Insertion (RC)

JTAG InsertionJTAG Insertion

TAP Controller InsertionTAP Controller Insertion

Boundary Cell InsertionBoundary Cell Insertion

JTAG-to-1500JTAG-to-1500

• JTAG macro insertion (TAP controller, IR, decode logic)

• Boundary cell insertion at bottom I/Os

• JTAG-to-1500(preventing pins)– Operation sequence

1a. JTAG: “WIR Program”1b. 1500: WIR loading2a. JTAG: “scan”2b. 1500: scan

– RequiresJTAG-to-1500 adapter

4. 3D wrapper generation flow JTAG insertion

WPOs

WPIs

WSOs

WSIsWSO

w

w

w

w

w

w

w

w

w

w

w

w

WIR

tow

ard

/fr

om

to

p d

ie

WSI

WPI

WSC

WPO

BPO[0]

BPO[1]

OEN

BPI[0]

BPI[1]

BPI[2]

tow

ard

/fr

om

exte

rnal I/O

s

scan

chains

TDI

TDO

TMS

TCK

TRST JTAG Macro

J

J

J

J

J

J

JTAG-to-

1500


4. 3D wrapper generation flow3D wrapper schematic view


• TSMC test chip• 65nm CMOS

• Functional design– 727 functional I/Os– 229,249 std. cells– 28,224 flip-flops– Area 2,070,536µm2

• 3D wrapper area:– 1.0% of the chip std. cell area– negligible for realistic designs

5. Results 3D-DFT wrapper and skin model

+7.8%

+1.0%

+0.6%

3D Wrapper3D Wrapper



IEEE 1149.1 Boundary ScanIEEE 1149.1 Boundary Scan

Die

DfT Area:


• 3D chip stacking using Through-Silicon Vias has much potential

• 3D test challenges include pre-bond and post-bond testing• 3D-DfT architecture

– Test-only pads for pre-bond testing– Serial and Parallel test access mechanisms– TestTurns: to bypass upper dies in stack– TestElevator mode: for test paths to/from upper dies

• 3D wrapper insertion flow– Inserts 1500-style wrappers and 1149.1 for bottom die– Generates input to run ATPG

• Industrial case study: negligible area costs of 3D wrapper

6. ConclusionSummary: DFT for pre- and post-bond


Documents

What Does it Take to Build a Complete Test Flow for 3-D IC?edpsieee.ieeesiliconvalley.org/edp2012/Papers/3D 4... · 2019-04-14 · What Does it Take to Build a Complete Test Flow