Week2n3b Up to 53 Slides

8/2/2019 Week2n3b Up to 53 Slides

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Computer-System Structures

I/O Structure

orage ruc ure

Storage Hierarchy ar ware rotect on

General System Architecture


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Computer-System Operation

mo ern computer system cons sts o a , memory,system bus and a number of device controllers

I/O devices and the CPU can execute concurrentl .

Each device controller is in charge of a particular devicetype.

buffer storage and special purpose registers

A bootstrap program is required to initialize the

CPU moves data from/to main memory to/from localbuffers

I/O is from the device to local buffer of controller. Device controller informs CPU that it has finished its


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Computer-System Architecture


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Common Functions of Interrupts The occurrence of an event is usually signaled by an interrupt

from either the hardware or the software System call or monitor call is executed to trigger an interrupt

Interrupt transfers control to the interrupt service routinegenerally, through the interrupt vector, which contains theaddresses of all the service routines.

Interrupt architecture must save the address of the interrupted

instruction.

Incoming interrupts are disabledwhile another interrupt isbeing processed to prevent a lost interrupt.

A trapis a software-generated interrupt caused either by an

error or a user request. An operating system is interruptdriven and priority interrupts

have been introduced in modern systems,


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Interrupt Handling ,

transfers execution to a fix location to execute the interrupt serviceroutine through a table of pointers which is stored in LMA

On completion of execution of service routine, the CPU resumes the

LMA locations hold the addresses of the interrupt service routines(interrupt vector) for the various devices

Se arate se ments of code determine what action should be taken foreach type of interrupt

The operating system preserves the state of the CPU by storing

registers and the program counter.

polling

vectoredinterrupt system

Interrupts are an important part of a modern computer system and

they must be handled quickly System call is the method used by a process to request action by the

operating system


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Polling

The CPU stops in regular interval to process the user-

ro ram to check now with EVERY connected

device, if an action of the CPU is required.

This is a very ineffective method, since this checking

a es up su s an a process ng me.


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Interrupts

Much more efficient is the method to assign to each device a"ringer".This allows the CPU to continuousl rocess the User-Pro ram. If

a device needs now to be handles, it uses the "ringer" to send analarm system to the CPU. The CPU interrupts now its currentactivit and handles the re uest of the interru tin device.


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Interrupt time line for a

s ng e process o ng ou pu


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An interru t is a si nal to the CPU from

some other module in the system.,

completes, the I/O module will interrupt.The CPU will then interrupt its normal flow

of control to rocess the interru t.

Interrupts improve CPU efficiency.

T e o ow ng examp e ustrates w y.


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Control Flow Without Interrupts

User program runs (1) until

WRITE instruction transfers

control to the I/O ro ram.

I/O program prepares I/Omodule for writing (4).

CPU waits for I/O command to

complete, which may take a

lon time.

I/O program finishes in (5) and

report status of operation.

User program resumesexecuting (until next WRITE).


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In the previous example, the CPU has to wait for.

It would be more efficient if the processor could

executes in parallel.

nterrupts ma e t s poss e.


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Control Flow with Interrupts

User program executes

an I/O program,which issuesthe I/O command. (4)

user application

User code executes during I/O

User program interrupted (x)when I/O operation is done.

handler

(2b) Execution of user code


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Interrupt Processing

Interrupt processing comes at unpredictable points in

ro ram execution.

The interrupted program must not be affected, so itsstate must be temporarily saved and later restored


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Interrupt Processing

vary slightly according to CPUarchitecture.

,

handle the interrupt (exact details

depend on nature of interrupt), restore

state.

Interrupts allow devices and CPU to

run in parallel.

-


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I/O interrupts

I/O interrupts assist in the operation of externaldevices. A hard drive controller can si nal the

completion of a write/read operation, so that it can

be given more operations to carry out. A COMport can signal I/O activity by an attached Modem

or Mouse.


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Program interrupts

Program (also known as "internal") interrupts are

.

when a user programs are in error (divide by zero,

tr in to access the memor s ace occu ied b theOperating System Kernel, etc).


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Hardware interrupts

Hardware (or "external") interrupts are either-

can be disabled, non-maskable may not. They are

generated if critical hardware errors areencountered. Faulty RAM; Hard Drive crashes can

signal hardware interrupts.


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Timer interrupts

Timer interrupts are classed as "external" and help

to determine how long a given process has been

running. The system timer has the highestn erna pr or y, a .


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Critical Events

ve s e pe p

(e.g. a mouse click, key pressed) are signaled. ,

appropriate interrupt is flagged and detected

by the CPU, which can pass control to theappropriate handler. The CPU can then

resume it's previous task.


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The Hierarchy

important than others. For example: a COM port should always take

precedence over a sound card, due to the heavy use

of a mouse in a GUI. This helps to ensure that there

" ",

have the same priority.


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Instruction Execution Cycle of an Interrupt

System

ny sys em a uses

interrupts must include a

'

Execution Cycle to

detect when an interrupthas been signaled.


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What Happens When an Interrupt is Generated?


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Categories of Interrupts

Interrupts fall into two major categories:

mas a e

non-maskable.

sensitive.


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Edge level interrupts

e eve e up s e e ze e

falling or rising edge of the input signal.

interrupts and are latched internally inside

the processor. If this latching was not done,the processor could easily miss the falling

edge (due to its short duration) and thus not

respon to t e nterrupt request.


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Level sensitive interrupts

eve se s ve e up s ve e e

problem of latching, in that the requesting

logic state (normally logic zero) till the

processor acknowledges the interrupt. Thistype of interrupt can be shared by other

devices in a wired or configuration, thus is

common y use to support a sy c a n ngand other techniques.


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Maskable Interrupts

interrupts by use of a special interrupt.

condition code register, or a special

interrupt register. If this bit is set, and aninterrupt request occurs on the InterruptRequest input, it is ignored.


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Non-Maskable Interrupts

out or ignored by the processor. These are associatedwith high priority tasks which cannot be ignored

(like memory parity or bus faults). In general, most

processors support the Non-Maskable Interrupt

NMI . This interru t has absolute riorit andwhen it occurs, the processor will finish the current

memory cycle, then branch to a special routine

.


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A step-by-step study

o Timer / I/O Device / Program / Hardware raises an interrupt. This flaghas a value, indicating it's priority.

,

raised interrupts.o If there are multiple interrupts raised, the one with the highest priority is

chosen thus avoidin a deadlock.

o The information currently in the registers, and the Processor StatusWord (PSW) is stored on the stack. Execution is passed to the

appropriate handler.o If another interrupt is encountered at the end of the Processor

Instruction Cycle, which has a higher priority than the one currentlybeing handled, the information currently in the registers, and the PSW is

.

the interrupt handler completes it's execution.

o The PSW and other data is restored to the CPU registers, and executionof the revious rocess can continue.


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The Use of Interrupts

The use of interrupts generally falls into the

follo in cate ories

Input/Output data transfers for peripheral devicesInput signals to be used for timing purposes

Emergency situations (power-down)

Real-Time-execution/MultitaskingEvent driven programs


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Basic Steps

The Basic steps involved in interrupt

Getting signal.Savin current status.

Determining who signaled and what to do about

it.Returning to original activity.


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Interrupt Controlled I/O Transfers


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The Programmable Interrupt Controller

C f I t t


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Cause of an Interrupt

In general, two methods are used to determine what condition is causing

an interrupt:

Examination of the device status word

Examination of the interru t-level status word

Interrupt Latency

The interrupt latency is the interval of time measured from the instant an

interrupt is asserted until the corresponding ISR begins to execute.

Interrupt Response Time

The time interval between the CPU recognizing the interrupt to the timewhen the first instruction of the interrupt service routine is executed.


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I/O Structure e compu er sys em as a num er o ev ce con ro ers connec e

through a common bus

A device controller contains local buffer storage and a set of specialpurpose registers

The device driver is responsible for moving the data between the

peripheral devices and it controls its local buffer storage I/O interrupts are used by the device controllers for transfer of data

me o s: Synchronous

Asynchronous

In s nchronous method after I/O starts control returns to userprogram only upon I/O completion. Waiting for I/O may be accomplished by either wait instruction or wait

loop

Wait instruction idles the CPU until the next interru t

Wait loop continuous until an interrupt occurs At most one I/O request is outstanding at a time, no simultaneous I/O

processing.


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I/O Structure

In asynchronous method, after I/O starts, control returns touser program without waiting for I/O completion. It requires:-

System call request to the operating system to allow user to.

Device-status table contains entry for each I/O device indicatingits type, address, and state.

device status and to modify table entry to include interrupt.

OS will also maintain a wait queue for each I/O device.

device and updates its table entry

An interrupt signals completion of an I/O request, control thenreturns from I/O interrupt to another request or user program

Interrupt schemes vary from system to system This method increases system efficiency


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Two I/O Methods

sync ronous


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Device-Status Table


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Direct Memory Access Structure

Involvement of CPU in data transfer is a time-consuming process. If the CPU needs two

interrupts arrive every four microseconds then lesstime is left for process execution.

s use or g -spee / ev ces a e totransmit information at close to memory speeds.

storage directly to main memory without CPUintervention.

Only one interrupt is generated per block, rather thanthe one interrupt per byte.


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Direct Memory Access Structure

DMA controller has its own registers for source anddestination addresses

use the appropriate source and destinationaddresses, transfer length and it is then instructed tostarts / operat on

While the DMA controller is performing the data

,

As the DMA controller steals memory cycles from theCPU so it slows down CPU execution during DMA

operation DMA interrupts the CPU when the transfer has been


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Issue Read

command toCPU --> I/O

Issue Read

command toCPU --> I/O

--I/O Module

Read Status

of I/O I/O --> CPU

I/O Module

Read Status

of I/O

ssue eaBlock Command

to I/O Module

Do something

else

Do something

else

Interpret

Check

Module

Not

ready

Error Check

Module

Error

-->

Read Status

of DMA

Interpret

Read word

from I/O I/O --> CPU

ready

Read word

from I/O I/O --> CPU

ModuleDMA --> CPU

Module

Write Word

Into Memory CPU --> Memory

Module

Write Word

Into Memory CPU --> Memory

Next Instruction

(c) direct memory access

Done?

No

Done?

No

Next Instruction

(a) Programmed I/O

Next Instruction

(b) Interrupt-driven I/O

FIGURE : Three techniques for input of a block of data


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Storage Structure

Registers

Cache

Main Memory

Magnetic Disk

Hard Disk


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Registers

Registers are available in the CPU and are

.

Faster operations are carried out on contents of.

Processor does not stall while performing

operations on registers.

Size of the registers is very small.

Registers are volatile.

Cache


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Cache

providing data required to complete the instruction.

Cache is a faster memory between the CPU and mainmemor and is a remedial measure to reduce idlin time ofCPU.

Cache is a memory buffer which stores information requiredb the CPU usin re ister-allocation and re ister-replacement algorithms.

Instruction cache holds the next instruction expected to be

executed whereas data cache kee s re uired data for theinstruction t. They are known as hardware caches.

Cache have limited size so cache management is a problemfor desi ners.

Careful selection of the cache size and of a replacementalgorithm can provide 80 99% of all accesses within thecache maximizin s stem erformance.

Caches are volatile.

Main Memory


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Main Memory Main memory can be viewed as a fast cache for secondary storage.

Programs must be loaded in the RAM for execution and main memoryis a large storage media that the CPU can access directly.

Main memory is implemented in a semiconductor technology (DRAM).

Load and store instructions specify memory addresses for

interaction. A typical instruction is executed using fetch-decode-execute cycle.

All programs and data can not be stored in a RAM because of itssmall size and volatility.

Special I/O instructions allow data transfers between the devicecontroller registers and main memory.

In memory-mapped I/O, ranges of memory addresses are set asideand are mapped to the device registers for providing more convenientaccess o ev ces.

In programmed I/O, CPU uses polling to watch the bit in the controlregister to see whether the device is ready for transfer of data

.

In an interrupt-driven I/O, CPU receives an interrupt when the device

is ready for the data transfer.

Magnetic Disks


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Magnetic Disks Ma netic disks rovide a lar e s ace for storin ro rams and

data on permanent basis.

Disks are relatively simple and consist of:

Platters covered with the magnetic material

Read-write head

Disk arm Each surface of platter has tracks, sectors and cylinders

Disk speed depends upon Transfer rate and positioning time (seektime & rotational latency)

Head crash damages the magnetic surface and the entire disk is.

The storage size of a HD is in GBs.

FDD rotates slowly than HDD which reduces wear on the disk. .

Buses attached to a disk drive are EIDE, ATA and SCSI. Data transfer through a bus is carried out between the host

.

Magnetic disks are non-volatile.

Moving-Head Disk Mechanism


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Moving-Head Disk Mechanism

Magnetic Tapes


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Magnetic Tapes

Magnetic tapes are used to backup the data andprograms in order to protect any loss due to HD failure.

Magnetic tapes can hold large quantities of data /

programs., ,

Memory etc.

Magnetic tapes are non-volatile. Storage / handling of magnetic tapes requires special

care.

ecor ng rea ng o n orma on s very s ow ue owinding / rewinding of tapes.

Random access is not available on ta es.

Storage Hierarchy


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Storage Hierarchy

according to:

Speed

Cost

Capacity

Registers, cache and memory are constructed using

semiconductor memor and are volatile.

Electronic disks can be volatile or nonvolatile.

All secondar stora e devices ma netic disk o tical

disk, floppy disk, magnetic tapes, magnetic drumsetc) are nonvolatile.

Storage-Device Hierarchy


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Storage Device Hierarchy

Coherency and Consistency


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Coherency and Consistency

system. For example, value of variable (X) of file G may reside

on magnetic disk, main memory, cache or CPU registers.

,

value of variable (X) must obtain the most recently updatedvalue.

A copy of variable (X) may exist simultaneously in several

caches having different value in a multiprocessor environment.

For cache coherency, system hardware must make sure that anupdate to value of X in one cache is immediately reflected in all

other caches where X resides for concurrent execution of file G.

For cache consistenc in a distributed environment the various

replicas of the file G may be accessed and updated concurrentlyso system must ensure that when a replica is updated in one

- -

through client or server initiated approach.


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X

Hardware Protection


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Hardware Protection

-

I/O Protection emory ro ec on

CPU Protection

DUAL MODE OPERATION


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ar ng o sys em resources mprove u za onbut increased problems. Many jobs could be affected bya bug in one program.

A good OS must ensure that a faulty program cannot

cause other programs to execute incorrectly.

OS dumps the memory of the program for debugging andterminates it.

- -the OS, all other programs and their data from anymalfunctioning program. - - .

Monitor/supervisor/system mode of operation (mode-bit is 0).

Whenever an interrupt or trap occurs, the hardwaresw tc es rom user-mo e to mon tor-mo e. s n t emonitor-mode.

Dual-Mode Operation


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Dual-Mode Operation

e ua -mo e o operat on prov es us w tthe means for protecting the OS from errantusers and errant users from one another.

The hardware allows privileged instructions(e.g. system call) to be executed only in

.

When an interrupt or fault occurs hardware

switches to monitor mode.

Interrupt/fault

monitor user

set user mode

I/O Protection


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I/O Protection

All I/O instructions are defined as privilegedinstructions so users cannot issue I/O instructionsrom user mo e.

Must ensure that a user program could never gain. .,

program that, as part of its execution, stores a newaddress in the interrupt vector).

To do I/O, a user programme executes a system call torequest that the OS perform I/O on its behalf andreturns the control to the users after com letion of I/O

operation.

Use of a System Call to Perform I/O


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Use of a System Call to Perform I/O

Memory Protection


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Must rovide memor rotection for the interru t

vector, the interrupt service routines and userprograms from one another.

used to determine the range of legal addresses a

program may access:

address.

Limit register contains the size of the range

. A trap is generated if any users program attempts to

access unauthorized memory area.

When executing in monitor mode, the operatingsystem has unrestricted access to both monitor andusers memory.

The load instructions for the base and limit registers

are privileged instructions.

Use of a Base and Limit Register


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Use of a Base and Limit Register

Hardware Address Protection


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Hardware Address Protection

CPU Protection


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be stuck in an infinite loop

fail to call s stem services

fail to return control to the OS

Timer interrupts computer after specified period toensure operating system maintains control.Timer is decremented every clock tick.

,control is automatically transferred to the OS.

Timer is also commonly used to implement time

sharing mechanism. Time can be used to compute the current time.

Load-timer is a privileged instruction.

Network StructureL l A N t k LAN


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Local Area Networks LANLANs were introduced in 1970 for economical use of a

number of small computers and sharing of computerresources.

LANs cover a small geographical area and areenerall used in an office environment.

Communication links of LANs have a higher speedand lower error rate.

High-quality cables (TP, Fiber Optic etc) are used forestablishment of LANs.

, .

Communications speed range from Mbps to Gbps.A t ical LAN ma consist of PCs/La to s/PDAs,

shared peripheral devices and one or more gateways.

Local Area Network Structure


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Network Structure Wide Area Networks (WAN)


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Wide Area Networks (WAN)

WANs emerged in the late 1960s to provide efficient communication among sites. WANs are physically distributed over a large geographical area.

Hardware and software resources are shared conveniently and economically by a wide.

ARPANet grew from four sites to millions of sites using internet.

The communication links (telephone lines, leased lines, microwave links, satellitechannels etc) are relatively slow and less reliable.

Communication processors control the communication links for transferring informationamong the various sites.

The internet WAN provide the ability for hosts at geographically separated sites to

communicate with one another. The host computers differ from each other in type, speed, word length, operating system

etc.

Connections between networks use a telephone-system service to provide

T1 service provides a transfer rate of 1.544 Mbps T2 service provides a transfer rate of 6.312 Mbps

T3 service rovides a transfer rate of 44.736 Mb s

T4 service provides a transfer rate of 274.176 Mbps

The router control the path each message takes through the net. Dynamic routingenhances communication efficiency whereas static routing reduces security risks.


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y g y

Modems convert digital data to analog signals and vice versa for communication.WANs are slower than LANs (1200 bps to 1 Mbps) and uses PPP for connecting

computers to the internet.

Wide Area Network Structure

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Week2n3b Up to 53 Slides