ME 7292 Control System Labs

Spring 2014Week 2

Discretization, Quantization and Sampling

Kirti Deo Mishramishra.98

January 30, 2014

Contents

1 Objective 2

2 Equipments 2

3 Experiment Procedure 23.1 Assignment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2 Assignment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.3 Assignment 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Results and Analysis 34.1 Assignment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.2 Assignment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.3 Assignment 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Conclusion 8

6 Appendix 8

List of Figures

1 Simulink Screen Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Control Desk Screenshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Overall delay for two sampling period - 0.0001s and 0.00002s . . . . . . . . . . . . . 54 Overall Time delay - Close View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Quantisation effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables

1 Decimal To Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Binary to Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

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1 Objective

1. To understand data formats and its conversion between fixed-point data and floating-pointdata.

2. To evaluate the overall time-delay when implementing a digital controller on dSpace.

3. To investigate quantization error.

2 Equipments

Equipments used for the experiment mainly were

1. Digital Computer

2. dSpace DS1104 Floating -Point Controller Borad

3. Two BNC cables

4. T-Joint Connector

3 Experiment Procedure

Overall, experimentation consisted of making of simulink model, converting the model into anequivalent C code which could be loaded on the controller board and real time control of thesimulink model through control desk (GUI for DSpace board) software. This section talks aboutthe experimental procedure adopted for assignments and the next section talks about results andanalysis.

3.1 Assignment 1

A matlab code (shown in appendix) was written to make the conversion from the binary to decimaland vice-versa in an automated manner. Two external m files were used namely fp dec2bin16.mand fp bin2dec16.m to make the conversion possible.

3.2 Assignment 2

1. A BNC cable was used to connect port ADCH1 to DACH1.

2. A simulink model with a fixed time step of 0.0001(this step was again repeated with a timestep of 0.00002) was built and converted to an equivalent C-code.

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Figure 1: Simulink Screen Shot

3. A custom interface in Control Desk environment was created.

Figure 2: Control Desk Screenshot

3.3 Assignment 3

1. The resolution of ADCH1 ADCH5 were calculated and found to be 3.0518X105 and 4.8828X104

respectively(without the gain of 10).

2. DACH1 was connected to both ADCH1 ADCH5 using two BNC cables and a T-joint connec-tor.

3. Changes were made to the previous simulink model to abtain the following (fixed step).

4. Corresponding changes were made in Control Desk interface.

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4 Results and Analysis

In this section, results for various assignments and corresponding analysis is presented.

4.1 Assignment 1

1. Following decimal numbers were converted to binary format,

S.No Decimal Numbers Binary Number

1 0 0000000000000000

2 100 0101011000111111

3 1.56 0011111000111101

4 -3.5 1100001011111111

5 -135000 1111110000011110

6 130000 0111111111101111

Table 1: Decimal To Binary Conversion

2. Following binary numbers were converted to decimal format,

S.No Binary Numbers Decimal Number

1 0111010111101101 24272

2 0100010101101100 5.4219

3 1111010101111111 -22512

4 1000010111101001 -9.0182e-05

Table 2: Binary to Decimal Conversion

3. The maximum value of the 16 bit number can be found out by

(1)sign(1 +10i=1

[di]21)X2e15

For the maximum number we take the sign bit as positive(0), exponent part to be 11110(as11111 is reserved for infinity) and fraction part to be 1111111111. The bias was found by

e =4

j=0

[e4j ]X2j

Substituting the values we get, 65504.

The minimum number which we can find is -65504 (other possible case is 0 or 214 if we wantminimum positive number).

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4.2 Assignment 2

1. Two different set of data for two different sampling frequencies are shown below. Clearlyfrom the these curve we can see the delay between the original and the delayed signal. Alsoit is evident that delay reduces due to by increasing the sampling frequency of the signal.Close-ups for these figures is shown next which also suggests the dependency of delay onsampling period.

Figure 3: Overall delay for two sampling period - 0.0001s and 0.00002s

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(a) Sampling - 0.0001 s (b) Sampling - 0.00002 s

Figure 4: Overall Time delay - Close View

2. From the closer view of the above curves we can say that the delay introduced for the twocases are 0.0001 sec and 0.00002 sec respectively.

3. Causes of delay for the two cases are as follows:

Sample And Hold delay - This delay is introduced since data in a digital system is dis-crete(and also quantized). This discrete set of data is a result of sampling process(whichis done at a sampling frequency). This sampled data is held untill the next data pointis encouter. Now when these sampled data points are reconstructed to give back theanalog signal a delay is introduced due to zero-order hold. This delay is generally givenby -

delay =Tsampling

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Calculation/Conversion Delay - This delay is introduced due to the time taken bythe processor to make any calculation if any. In this case even the experiment is prettysimple but it involves data point conversion from decimal to binary and vice versa. Thisdelay can be anywhere between very small to sampling time period. As far as conversiondelay is concerned it is 2s for channel 1-4 ADC, 0.8s for channel 5-8 ADC, 10s forDAC channels.

4. The overall delays are different for the two cases becauses sampling frequency for the twocases are different as suggested by the expression above. Also they are different from thetheoretical value due to the calculation delay which is dependent on processors speed.

4.3 Assignment 3

1. Below is shown the comparison curve for the two channel ouputs(ADCH 1 ADCH 5) withthe orignial sine wave for the first case when the amplitude is 0.001. Clearly we can seefrom the curve below that the black curve which is the output of the 16 bit port (which has ahigher resultion of 3.0518X104) is able to follow the original plot(green curve) more closely ascompared to the 12-bit port(which has a resolution of 4.8828X103). The resolution basically

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tells us the minimum value a ADC can pick up for quatisation. Since the amplitude for thesine wave in this case is 0.001, the ADCH 5 is not able to pick anything(as this amplitude isless than its resolution) and technically should be zero. The spikes seen in the red curve arepossible noises which is also corroborated by their random distribution.

Figure 5: Quantisation effect

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2. In the next case when amplitude of the sine wave is 0.01, the ADCH 5 is able to follow theoriginal curve as it is able to quantize the input signal(as now the input signal is greater thanthe 4.8828X103 value). Again we can see that ADCH 1 is better replication of the sinewave since its resolution is less and thus is able to quantize to the values closer to the originalsignal.

5 Conclusion

Fundamentals of a digtal controller and practical problems in the implementation were understood.In particular the inherent properties of a digital controller namely number conversion, overall delayand quantisation was understood. Moreover the dependency of these properties on the samplingfrequency of the controller and the magnitude of the signals involved were tackled with.

6 Appendix

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ME 7292 Control System Labs% Week 2% Kirti Deo Mishra(# 98)%% The following script coverts binary decimal and processes% the data from the control desk environment into meaning figures.%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

clcclear allclose all

% Assignment 1% Decimal to Binary Conversion% Array of decimal values to be converted to binary.value1 = [0, 100, 1.56, 3.5, 135000, 130000] ;

% Initiating the reults arrayresults1 =[];

% Displaying resultsdisp(['Decimal Number ', ' Binary Number'])for i=1:length(value1)

results1 = [results1; fp dec2bin16(value1(i))];disp([num2str(value1(i)), ' ', results1(i,:)])

end

% Binary to Decimal Conversion% Array of binary numbers to be converted

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value2 = ['0111010111101101'; '0100010101101100'; ...'1111010101111111'; '1000010111101001'] ;

% Initiating array of resultsresults2 =[];% Displaying Resultsdisp(['Binary Number ', ' Decimal Number'])for i=1:size(value2)

results2 = [results2; fp bin2dec16(value2(i,:))];disp([value2(i, :),' ', num2str(results2(i, 1))])

end

% Assignment 2clcclear all% loading data files exported by Control Deskload part1.matload part2.mat

figure('color', [1 1 1])plot(part1.X.Data, part1.Y(1,2).Data,'r',...

part1.X.Data, part1.Y(1,3).Data,'g')grid onxlabel('Time(s)')ylabel('Signal')legend('Original Signal', 'Delayed signal')title('Overall time dalay 0.0001 sec sampling')

figure('color', [1 1 1])plot(part2.X.Data, part2.Y(1,2).Data,'r',...

part2.X.Data, part2.Y(1,3).Data,'g')grid onxlabel('Time(s)')ylabel('Signal')legend('Original Signal', 'Delayed signal')title('Overall time dalay 0.00002 sec sampling')

% Assignment 3

clclear all

% Loading Data files exported from the control deskload assignment 3a.matload assignment 3b.mat

figure('color', [1 1 1])plot(assignment 3a.X.Data, assignment 3a.Y(1,1).Data,'k',...

assignment 3a.X.Data, assignment 3a.Y(1,2).Data,'r',...assignment 3a.X.Data, assignment 3a.Y(1,3).Data,'g')

xlabel('Time(s)')ylabel('Signal')legend('ADCH1(16 bits) signal', 'ADCH5(12 bits) signal', 'Original Signal')

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grid ontitle('Quantisation effect 0.001 amplitude')figure('color', [1 1 1])plot(assignment 3b.X.Data, assignment 3b.Y(1,1).Data,'k',...

assignment 3b.X.Data, assignment 3b.Y(1,2).Data,'r',...assignment 3b.X.Data, assignment 3b.Y(1,3).Data,'g')

xlabel('Time(s)')ylabel('Signal')legend('ADCH1(16 bits) signal', 'ADCH5(12 bits) signal', 'Original Signal')grid ontitle('Quantisation effect 0.01 amplitude')

*************************

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