Yanchang LIN - on behalf of the Daya Bay CollaborationTsinghua University, China

The Electronics System in the Daya Bay ExperimentThe Electronics System in the Daya Bay Experiment

The 1st international conference on Technology and Instrumentation in Particle Physics, Tsukuba, 2009

4

FEE PCB: 8 layer VME module

The Daya Bay electronics subsystem 3

Since both AD and water Cherenkov detector are PMT based, an identical readout electronics subsystem is developed.

Up to 16 Front End Electronics (FEE) modules, one Local Trigger Board (LTB), one flash ADC, and one Fanout module can be equipped in a VME crate. The subsystem can handle up to 256 PMTs.

All modules work with a synchronize clock. Each event has a time stamp.

Multiplicity trigger and energy-sum trigger are implemented in the LTB.

A master trigger module is also being developed to have cross check between AD and MD.

RPC electronics consists of Front End Card (FEC), Read Out Module (ROM) and RPC Trigger Module (RTM). RPC works independently on a self trigger mode. The muon signature is 3 out of 4.

Introduction to the Daya Bay experiment 1

The Daya Bay collaboration has more than 200 collaborators from Asia, North America, and Europe.

The experiment is located in south-east china, 55 km away from central Hong Kong.

The experimental goal is to observe the neutrino mixing angle θ13 with a

precision of sin2(2 θ13)=0.01 in a three-year run. A dry-run of the first anti-neutrino detector without liquid scintillator is expected to start in fall 2009.

The Daya Bay nuclear power complex. The Daya Bay NPP is in the foreground. The Lingao NPP is in the background. The experimental halls are inside the hills to the left.

overburden350 m

98 m

112 m

baseline1.8 km to Daya Bay cores1.6 km to Linao cores

3 prototype FEE modules under testing

FEE overview

2Neutrino and Muon Detectors layout

RPC roof

Neutrino detectors

Water Cherenkov

Anti-neutrino Detector (AD): 20 ton 0.1% Gd-doped Liquid Scintillator (Gd-LS) target with 192 PMTs per module. 4 modules for far site and 2 for near sites.

Muon Detector (MD):2-layer Water Cherenkov. 4-layer Resistive Plate Chamber (RPC) roof.

ΓΓ-catcher-catcher:20 ton LS:20 ton LS

Three zone detector module

Hamamatsu R5912

5

Signal in from PMT

-5V

50

High speedAmp

Dual ADC12bit/40MSPS

FPGA

To VME bus

CH1

single-endedto

diff.

Fast analog sum to trigger

C R- ( R C )s ha ping

threshold

start

CH2

disc.

TDC

Peak finder

cloc

k

char

ge

time 32bit 200us buffer

trigger

VMEinterface

Single channel macro in FPGAX16

RC=25ns

Calibration sig .

NHIT to trigger

K

CH3CH4

CH13CH14CH15CH16

SUM

DAC

High speedDAC

Status bits to triggerDLL

4

Signal width (1%) = 325ns after shaping

X 1

X 20

ADC

ADC

deserializer&

Rangeselection

Pipelinebuffer

fine range

coarse range

stop

320 M

Hit

NHITGen.

Control bits from trigger

trigger

40M Clock

single-endedto

diff.

Fast analog sum to FADC

FPGAConfiguration

logicVME

interfaceFlash ROM

CPLD

event buffer

32bit×256

20bit 350ns buffer

FEE block diagram

AD9222: octal serial LVDS ADC

6

The Daya Bay Clock systemCentral Clock Generator Symatricom GPS

( 200 ns precise PPS )

Symatricom Rubidium Clock( 10 ps Jitter )

Pendulum clock transceiver (50 ps)

A 10 MHz clock and the absolute time base on a Central Clock Generator (CCG) are generated in the control room outside of the tunnel

The 10 MHz clock is broadcast to each underground experimental hall by a Pendulum transceiver.

The absolute time with a precise Pulse Per Second (PPS) signal will be modulated and sent with compensation, so that the cable length difference can be ignored.

The 10 MHz clock is multiplied into 40 Mhz in the Clock Fan-out Board before applying to each LTB.

In the FEE, ADCs run under 40 MHz clock. For TDCs, a 320 MHz clock is generated inside the FPGA on the FEE.

Clock Fan-out Board

Optical cable bundle

Daya Bay FEE is a VME 9U module, which can handle up to 16 channels of PMT outputs. 16 channels of dual range 12 bit ADC and 16 channels of 20 bit TDC are integrated.

The waveform of each input pulse will be sampled with a 40 MHz clock after a shaping circuit. The TDC utilizes a 320 MHz clock. A trigger issued by the LTB is the common stop signal for all the TDC channels.

The event information along with ADC and TDC data will be stored in the buffer inside the onboard FPGA.

The VME controller reads data from each FEE via VME bus using a Chained Block Transfer (CBLT) mode after a data-ready interrupt signal asserts.

Some specifications of the FEE are listed on the table above.

Quantity SpecificationDynamic Rang 0~400 p.e. for fine range0~4000 p.e. for coarse rangeADC bit resolution 10% @ 1 p.e.

No. of ADC bits 12 for fine range12 for coarse rangADC Sampling rate 40 MSPS

Time range 0~500 ns

Time Precision (rms) 500 ps

VME standard VME64xp 9U-340 mm

Channel per board

RPC Layer 1RPC Layer 2RPC Layer 3RPC Layer 4

FECROM

&RTM

Cable VME

RPC electronics

Buffer-full,RdrqstFEE

( Front-End Electronics )

Board 1

FEE( Front-End Electronics )

Board 16

LTB( Local TriggerBoard)

Flash ADC

GPS receiver& clock

1:16Fanout

Optical

ClockTrigger

ClockTrigger

TotalEnergy sum

VME

VME

VME

VM

E

Fast hit info

Energy sum

Buffer-full,Rdrqst

Fast hit info

Energy sum

ClockTrigger

PMT1

PMT16

PMT241

PMT256To master trigger

Electronics for both AD and water Cherenkov detector

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