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Title: 10-Gbps Ethernet MAC and PHY MegaCore Migration Guideline
ContentsTitle: 10-Gbps Ethernet MAC and PHY MegaCore Migration Guideline.......................................................11. Introduction.............................................................................................................................................22. Installation...............................................................................................................................................23. Architecture.............................................................................................................................................24. Generation, Parameterization, and Features...........................................................................................3
4.1 IP Core Generation.............................................................................................................................34.2 IP Core Parameterization...................................................................................................................5
4.2.1 Variation Options...............................................................................................................54.2.2 FIFO Options.....................................................................................................................64.2.3 MAC Options.....................................................................................................................64.2.4 Transceiver Reconfiguration Options................................................................................74.2.5 ECC Options......................................................................................................................7
4.3 IP Core Features.................................................................................................................................75. Interfaces.................................................................................................................................................9
5.1 Avalon-ST TX....................................................................................................................................95.2 Avalon-ST RX.................................................................................................................................105.3 Avalon-MM.....................................................................................................................................115.4 Clock and Reset...............................................................................................................................115.5 Transceiver Reconfiguration............................................................................................................135.6 Control Interface..............................................................................................................................13
5.6.1 Flow Control Interface.....................................................................................................135.6.2 ECC Option Interface......................................................................................................145.6.3 MDIO Interface................................................................................................................14
5.7 Status Interface.................................................................................................................................145.7.1 Avalon-ST Receive Status Interface................................................................................145.7.2 Avalon-ST Transmit Status Interface..............................................................................15
6. Configuration Register..........................................................................................................................166.1 Register Addressing.........................................................................................................................166.2 Register Map....................................................................................................................................166.3 Register Configuration.....................................................................................................................176.4 Statistic Counter...............................................................................................................................18
7. Timing Constraints................................................................................................................................188. References.............................................................................................................................................21
1. IntroductionThe main objective of this document is to provide a comparison summary and migration guideline from the 10-Gbps Ethernet Reference Design to Altera latest 10-Gbps Ethernet solution. The 10-Gbps Ethernet Reference Design is no longer supported and Altera had release several Ethernet MegaCore to support in the latest Altera FPGA such as Stratix V and Arria V devices. Altera Ethernet MegaCore includes:
10-Gbps Ethernet MAC MegaCore XAUI PHY IP MegaCore 10G Base-R PHY IP MegaCore
Altera also released the 10GbE MAC with PHY Design Example to reduce user integration effort. The 10GbE MAC with XAUI PHY Design Example is the closest Ethernet solution if compare to the 10-Gbps Ethernet Reference Design in terms of features, functionality and usability. This documentation will focus on the migration guideline from the 10-Gbps Ethernet Reference Design to the 10GbE MAC with XAUI PHY Design Example.
The rest of this documentation will discuss base on the following category: Installation Architecture Generation, Parameterization, and Features Interfaces Configuration Register Timing Constraints
2. Installation Table 2.1 summarized the IP cores installation requirement for MegaWizard and SOPC Builder/QSYS support.
Table 2.1: Installation requirement for MegaWizard Plug-In Manager Flow10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
MegaWizard Required √ √ ×SOPC Builder Required × × ×QSYS × √ × √Notes:
Required – Installation steps are required√ – Support in ACDS Released, No Installation required× – Not Available
For 10-Gbps Ethernet Reference Design installation steps, refer to the following section in the 10-Gbps Ethernet Reference Design User Guide :
2.1.3.1 Install IP Core Library for MegaWizard Plug-In Manager Flow 2.1.3.2 Install IP Core Libraries for the SOPC Builder Flow
3. ArchitectureTable 3.1 summarized the high level architecture comparison for the following IP Cores:
10-Gbps Ethernet Reference Design 10-Gbps Ethernet MAC MegaCore XAUI/10G-Base-R PHY IP MegaCore 10GbE MAC with PHY Design Example
Table 3.1 IP Cores Architecture Comparison Summary
10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
FIFO √ × × √MAC TX √ √ × √MAC RX √ √ × √MDIO √ × × √XAUI PHY √ × √ √10G Base-R PHY × × √ √SDR XGMII √ √ √ √DDR XGMII √ * * *Transceiver Reconfiguration Interface
√ × √ √
Statistic Counter √ √ × √ATX/CMU PLL √ × √ √ECC Options √ × × ×Notes:
√ – Available× – Not Available* – Manual Conversion is required
Referring to Table 3.1, it is clearly show that the closest solution to the 10-Gbps Ethernet Reference Design is the 10GbE MAC with PHY Design Example where the design example include the FIFO, MDIO, MAC and PHY as a complete Ethernet solution and reduce design integration effort.
For complete architecture block diagram refer to:1. 10-Gbps Ethernet Reference Design refer to Application Note 588, 10-Gbps Ethernet
Hardware Demonstration Reference Design2. 10GbE MAC with PHY Design Example refer to Design Examples and Testbench chapter in 10-
Gbps Ethernet MAC MegaCore Function User Guide
4. Generation, Parameterization, and FeaturesThis chapter will focus on the 10GbE MAC with PHY Design Example generation and also comparison in terms of IP core parameterization, and feature with the 10-Gbps Ethernet Reference Design, 10-Gbps Ethernet MAC MegaCore, and PHY IP MegaCore.
4.1 IP Core GenerationFollow the steps below to generate 10GbE MAC with XAUI PHY Design Example in Qsys:
Step 1: Launch Qsys1. Go to Tools and Select Qsys
Step 2: Set the required device family1. Go to Project Settings tab and select the required Device family
Figure 4.1.1 Qsys Project Settings Tab
Step 3: Generate the 10GbE MAC with XAUI PHY Design Example
1. Go to Interface Protocols -> Ethernet -> Example Designs and double click on Atlera Ethernet 10G Design Example
2. The Altera Ethernet 10G Design Example GUI pop up like figure below:
Figure 4.1.2 Altera Ethernet 10G Design Example GUI
3. Select the desire configuration. For example 10GbE MAC with XAUI PHY Design Example for Stratix V:
Configuration Tab:o MDIOo XAUI PHYo Avalon-ST Dual Clock FIFO
MAC Tab:o Supplementary Addresso CRC on Transmit Patho Statistic Collectiono Statistic Counters: Memory Based
MDIO Tab:o Clock Divisor : 32
DC FIFO Tab:o TX FIFO Depth: 2048o RX FIFO Depth: 2048
XAUI Tab:o XAUI Interface Type: Soft XAUIo PLL Type: CMUAll the Analog Options in XAUI and 10G Base-R tab is NOT applicable to Stratix V and only for Stratix IV. For Stratix V, use the Assignment Editor to set the transceiver analog settings.
4. Click Finish to add the 10GbE MAC with PHY Design Example into Qsys system
Step 4: Generate the Qsys system with 10GbE MAC with PHY Design Example1. Export all the 10GbE MAC with PHY Design Example interfaces if you are not planning to
integrate the design example in Qsys. To Export, just click on the Export column on the required interface.
Figure 4.1.3 10GbE MAC with PHY Design Example with all interface exported in Qsys
2. To generate the design example simulation model, go to Generation Tab: Create Simulation Model: Verilog
3. Ensure the Output Directory Path is set to the required path4. Click Generate
4.2 IP Core Parameterization4.2.1 Variation Options Table 4.2.1.1 shows the IP variation comparison summary.
Table 4.2.1.1 Variation Option Comparison SummaryOption 10-Gbps Ethernet
Reference Design10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
MAC + XGMII(1) √ * * *MAC + XAUI √ × × √MAC + 10G Base-R
× × × √
MAC + Soft XAUI
√ × × √
MAC Only(2) √ √ × √Soft XAUI Only √ × √ √10G Base-R PHY × × √ √Notes:
√ – Available× – Not Available(1) – 32-bit DDR XGMII Interface(2) – 64-bit SDR XGMII Interface* – Manual Conversion is required
The 10-Gbps Ethernet MAC MegaCore, PHY IP MegaCore, and 10GbE MAC with PHY Design Example only support 64bits SDR XGMII interface. Conversion between SDR XGMII to DDR XGMII can be done easily using the ALTDDIO_IN and ALTDDIO_OUT MegaCore. Conversion Guideline can refer to Chapter 7.1 SDR XGMII to DDR XGMII Conversion in 10-Gbps Ethernet MAC MegaCore Function User Guide.
4.2.2 FIFO Options The 10-Gbps Ethernet MegaCore does not include the FIFO on the Avalon ST transmit and receive interface so there will be no FIFO Option available on the MegaCore.
However, Avalon ST FIFO is included as part of the 10GbE MAC with PHY Design Example under Qsys. There are two types of FIFO architecture with three combinations available on the 10GbE MAC with PHY Design Example:
Avalon-ST Single-Clock FIFO Avalon-ST Dual-Clock FIFO Avalon-ST Single-Clock FIFO and Avalon-ST Dual-Clock FIFO
For details information regarding the Avalon ST FIFO, refer to Chapter 15. Avalon-ST Single-Clock and Dual-Clock FIFO in Embedded Peripherals IP User Guide.
Table 4.2.2.1 shows the FIFO Option comparison summary.
Table 4.2.2.1 FIFO Option Comparison SummaryOption 10-Gbps Ethernet Reference
Design10GbE MAC with PHY Design ExampleSingle-Clock FIFO Dual-Clock FIFO
Receiver FIFO Size FIFO Depth: 8, 16, 32, 64, 128, 256, 512, 1024, 4096, 8192
FIFO Depth:64, 128, 256, 512, 1024, 2048, 4096, 8192
FIFO Depth:16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192
Transmitter FIFO Size
Mode:
Store & Forward √ √ ×Fill Level √ √ √Notes:
√ – Available× – Not Available
When Avalon-ST Single-Clock FIFO and Avalon-ST Dual-Clock FIFO option is selected, both FIFOs will be connected in series where it can take advantages on the combination of the FIFO features such as dual clock FIFO interface with Store & Forward mode.
Altera recommend that you use the Avalon-ST Single-Clock FIFO and Avalon-ST Dual-Clock FIFO option if dual clock system with store & forward mode is required.
4.2.3 MAC Options Table 4.2.3.1 shows the MAC Option comparison summary.
Table 4.2.3.1 MAC Option Comparison SummaryOption 10-Gbps Ethernet
Reference Design10-Gbps Ethernet MAC MegaCore
10GbE MAC with PHY Design Example
MAC Options:Preamble Pass-Through Mode
× √ √
Priority-based Flow Control (PFC)
× √ √
Resource Optimization Options:Data Path Option TX & RX TX Only, RX Only, TX & RX TX & RXSupplementary * (1) √ √
AddressCRC on Transmit Path
* (1) √ √
Enable MDIO √ × √Statistic Collection √ Memory-based and Register-
basedMemory-based and Register-
based
Notes:√ – Available× – Not Available*(1) – Feature Available but without resource optimization Option
The MDIO is no longer part of the 10-Gbps Ethernet MAC MegaCore. The MDIO is a standalone IP core and is part of the embedded peripherals IP core. For more information regarding the MDIO, refer to Chapter 14. MDIO Core in Embedded Peripherals IP User Guide.
The MDIO core is included as part of the 10GbE MAC with PHY Design Example which provides a complete Ethernet implementation example solution.
4.2.4 Transceiver Reconfiguration Options The transceiver reconfiguration option is mainly perform configuration on analog settings and also compensate for variations due to process, voltage, and temperature (PVT).
Table 4.2.4.1 shows the Transceiver Reconfiguration Option comparison summary.
Table 4.2.4.1 Transceiver Reconfiguration Option Comparison SummaryOption 10-Gbps Ethernet
Reference Design10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
Transceiver Reconfiguration
√ × √ √
Notes:√ – Available× – Not Available
The transceiver reconfiguration option is depend on the device that you choose, reconfiguration of the transceiver may be an optional or required feature. The configuration method on the same device is the same and is not IP dependent.
To find out more regarding the PHY IP and Reconfiguration controller refer to Altera Transceiver PHY IP Core User Guide.
4.2.5 ECC OptionsECC Option is not supported in the 10-Gbps Ethernet MAC MegaCore, XAUI/10G-Base-R PHY IP MegaCore, and 10GbE MAC with PHY Design Example.
4.3 IP Core FeaturesTable 4.3.1 show the IP Core features comparison summary.
Table 4.3.1 IP Cores Features Comparison SummaryFeatures 10-Gbps Ethernet
Reference Design10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
FIFO:Store & Forward √ - - √Fill Level √ - - √Frame Drop On Error √ - - √MAC:Preamble Passthrough × √ - √Preamble Insertion and Processing
√ √ - √
Source Address Insertion
√ √ - √
Length/Type Field Processing and Checking
√ √ - √
VLAN and Stacked VLAN Frames Processing
√ √ - √
Frame Padding Insertion and Removal
√ √ - √
Frame Check Sequence Insertion and Checking
√ √ - √
RX CRC Forwarding √ √ - √MAC Address Checking
√ √ - √
Supplementary MAC Address Support
√ √ - √
Flow Control √ √ - √Priority-based Flow Control
× √ - √
Link Fault √ √ - √Promiscuous Mode √ √ - √Statistics Counter √ √ - √Control Frame Enable and Ignore
√ √ - √
Local Loopback √ × - √CRC Error Insertion √ × - ×MDIO √ × - √ECC Options √ × - ×PHY IP:Line Loopback √ - √ √Transceiver Status √ - √ √Manual Transceiver Reset Control
× - √ √
Link Fault √ - √ √Transceiver Reconfiguration
√ - √ √
Notes:√ – Available× – Not Available- – Not Applicable
5. Interfaces The comparison and summary includes:
Avalon-ST TX Avalon-ST RX Avalon-ST Status Avalon-MM Clock and Reset Transceiver Reconfiguration Control and Status
5.1 Avalon-ST TXThe Avalon-ST Transmit interface is the standard bus that support widely in Altera IP Cores. Table 5.1.1 and Table 5.1.2 show the Avalon ST Transmit interface comparison summary.
Table 5.1.1 MAC Only Avalon ST Transmit Interface Comparison Summary10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
Direction Description
uset_tx_read avalon_st_tx_ready output When asserted, this signal indicates that the IP core is ready to accept data.
user_tx_data_valid avalon_st_tx_valid input Assert this signal to qualify the transmit data on the Avalon-ST bus.
user_tx_sop avalon_st_tx_startofpacket input Assert this signal to indicate the beginning of the transmit packet.
user_tx_dat [63:0] avalon_st_tx_data [63:0] input Carries the transmit data from the client.user_tx_eop avalon_st_tx_endofpacket input Assert this signal to indicate the end of the
transmit packetuser_tx_mty [2:0] avalon_st_tx_empty [2:0] input Use this signal to specify the number of bytes
that are empty (not used) during cycles that contain the end of a packet.
user_tx_error avalon_st_tx_error input Assert this signal to indicate the current receive packet contains errors.
user_tx_dav × input Indicates that the source has data available for the MAC’s consumption.
Note:× – Not Available
Table 5.1.2 MAC with FIFO Avalon ST Transmit Interface Comparison Summary10-Gbps Ethernet Reference Design
10GbE MAC with PHY Design Example (Single-Clock / Dual-Clock)
Direction Description
avl_st_tx_dav tx_sc_fifo_in_ready / tx_dc_fifo_in_ready
output When asserted, this signal indicates that the IP core is ready to accept data.
avl_st_tx_ena tx_sc_fifo_in_valid / tx_dc_fifo_in_valid
input Assert this signal to qualify the transmit data on the Avalon-ST bus.
avl_st_tx_sop tx_sc_fifo_in_startofpacket / tx_dc_fifo_in_startofpacket
input Assert this signal to indicate the beginning of the transmit packet.
avl_st_tx_dat [63:0] tx_sc_fifo_in_data / tx_dc_fifo_in_data [63:0]
input Carries the transmit data from the client.
avl_st_tx_eop tx_sc_fifo_in_endofpacket / tx_dc_fifo_in_endofpacket
input Assert this signal to indicate the end of the transmit packet
avl_st_tx_mty [2:0] tx_sc_fifo_in_empty / tx_dc_fifo_in_empty [2:0]
input Use this signal to specify the number of bytes that are empty (not used) during cycles that contain the end of a packet.
avl_st_tx_err tx_sc_fifo_in_error / tx_dc_fifo_in_error
input Assert this signal to indicate the current receive packet contains errors.
5.2 Avalon-ST RXThe Avalon-ST Receive interface is the standard bus that support widely in Altera IP Cores. Table 5.2.1 and Table 5.2.2 show the Avalon ST Receive interface comparison summary.
Table 5.2.1 MAC Only Avalon ST Receive Interface Comparison Summary10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
Direction Description
× avalon_st_rx_ready input When asserted, this signal indicates that the client is ready to accept data.
user_rx_data_valid avalon_st_rx_valid output Assert this signal to qualify the receive data on the Avalon-ST bus.
user_rx_sop avalon_st_rx_startofpacket output Assert this signal to indicate the beginning of the receive packet.
user_rx_dat [63:0] avalon_st_rx_data [63:0] output Carries the receive data from the client.user_rx_eop avalon_st_rx_endofpacket output Assert this signal to indicate the end of the
receive packetuser_rx_mty [2:0] avalon_st_rx_empty [2:0] output Use this signal to specify the number of bytes
that are empty (not used) during cycles that contain the end of a packet.
user_rx_error avalon_st_rx_error [2:0] output Assert this signal to indicate the current receive packet contains errors.
user_rx_vlan_tag * input Indicates that the received frame is a VLAN tagged frame.
user_tx_vlan_vlan_tag * input Indicates that the received frame is a stacked VLAN tagged frame.
Note:× – Not Available* – Refer to 5.7.1 Receive Status Interface
Table 5.2.2 MAC with FIFO Avalon ST Receive Interface Comparison Summary10-Gbps Ethernet Reference Design
10GbE MAC with PHY Design Example (Single-Clock / Dual-Clock)
Direction Description
avl_st_rx_ena rx_sc_fifo_out_ready / rx_dc_fifo_out_ready
input When asserted, this signal indicates that the client is ready to accept data.
avl_st_rx_val rx_sc_fifo_out_valid / rx_dc_fifo_out_valid
output Assert this signal to qualify the receive data on the Avalon-ST bus.
avl_st_rx_sop rx_sc_fifo_out_startofpacket / rx_dc_fifo_out_startofpacket
output Assert this signal to indicate the beginning of the receive packet.
avl_st_rx_dat [63:0] rx_sc_fifo_out_data / rx_dc_fifo_out_data [63:0]
output Carries the receive data from the client.
avl_st_rx_eop rx_sc_fifo_out_endofpacket / rx_dc_fifo_out_endofpacket
output Assert this signal to indicate the end of the receive packet
avl_st_rx_mty [2:0] rx_sc_fifo_out_empty / rx_dc_fifo_out_empty [2:0]
output Use this signal to specify the number of bytes that are empty (not used) during cycles that contain the end of a packet.
avl_st_rx_err rx_sc_fifo_out_error / rx_dc_fifo_out_error [4:0]
output Assert this signal to indicate the current receive packet contains errors.
avl_st_rx_dav × output Indicates that the FIFO has data for client’s consumption.
avl_st_rx_vlan_tag * output Indicates the received frame is a VLAN tagged frame.
avl_st_r_vlan_vlan_tag * output Indicates the received frame is a stacked VLAN tagged frame.
Note:× – Not Available* – Refer to 5.7.1 Receive Status Interface
5.3 Avalon-MMThe Avalon-Memory Map Interface (Avalon-MM) is the standard Altera memory map programming interface for configuration registers. Table 5.3.1 show the Avalon-MM interface comparison summary.
Table 5.3.1 Avalon-MM Interface Comparison Summary10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
10GbE MAC with PHY Design Example
Direction Description
avalon_address[8:0](1) csr_address[12:0] (1) eth_10g_design_example_0_mm_pipeline_bridge_address
[18:0] (2)
input Use this bus to specify the register address you want to read from or write to.
avalon_read csr_read eth_10g_design_example_0_mm_pipeline_bridge_read(2)
input Assert this signal to request a read.
avalon_readdata[31:0]
csr_readdata[31:0] eth_10g_design_example_0_mm_pipeline_bridge_readdata
[31:0] (2)
output Carries the data read from the specified register.
avalon_write csr_write eth_10g_design_example_0_mm_pipeline_bridge_write(2)
input Assert this signal to request a write.
avalon_writedata[31:0]
csr_writedata[31:0] eth_10g_design_example_0_mm_pipeline_bridge_writedata
[31:0] (2)
input Carries the data to be written to the specified register.
avalon_waitrequest csr_waitrequest eth_10g_design_example_0_mm_pipeline_bridge_waitreques
t(2)
output When asserted, this signal indicates that the IP core is busy and not ready to accept any read or write requests.
Note:× – Not Available(1) – Refer to Register Map(2) – The design example name can be change in Qsys
5.4 Clock and Reset The 10-Gbps Ethernet MAC MegaCore and 10GbE MAC with PHY Design Example have different clock and reset inputs if compare to the 10-Gbps Ethernet Reference Design. Table 5.4.1 and 5.4.2 shows the clock and reset summary for 10-Gbps Ethernet MAC MegaCore and 10GbE MAC with PHY Design Example.
Table 5.4.1 10-Gbps Ethernet MAC MegaCore Clock and Reset Domain Summary10-Gbps Ethernet MAC MegaCore
Direction Description
Clock Domain:tx_clk_clk input 156.25-MHz transmit clock. Provides the timing
reference for the Avalon-ST transmit and XGMII transmit interfaces.
rx_clk_clk input 156.25-MHz receive clock. Provides the timing reference for the Avalon-ST receive and XGMII receive interfaces.
csr_clk_clk input Configuration clock for the control and status interface.The clock runs at 156.25-MHz or lower.
Reset Domain:tx_reset_reset_n input An active-low asynchronous reset signal for the
tx_clk_clk domain. User can synchronize this reset to tx_clk_clk domain.
rx_reset_reset_n input An active-low asynchronous reset signal for therx_clk_clk domain. User can synchronize this reset to rx_clk_clk domain.
csr_reset_reset_n input An active-low reset signal for the control and status interfaces. User can synchronize this reset to csr_clk_clk domain.
Table 5.4.2 10GbE MAC with PHY Design Example Clock and Reset Domain Summary10GbE MAC with PHY Design Example
Direction Description
Clock Domain:ref_clk input This is a 156.25 MHz (XAUI) or 644.53125Mhz (10G
Base-R) reference clock that is used by the TX PLL and CDR logic
tx_clk_clk input 156.25-MHz transmit clock. Provides the timingreference for the Avalon-ST transmit interface.
xgmii_rx_clk_clk output 156.25-MHz receive clock from PHY IP. mm_clk_clk input Configuration clock for the control and status interface.
The clock runs at 156.25-MHz or lower.dc_tx_clk_clk(1) input Avalon-ST transmit clock for transmit FIFOdc_tx_clk_clk(1) input Avalon-ST receive clock for receive FIFO
mdio_mdc output MDIO clock outputReset Domain:
ref_reset_reset_n An active-low asynchronous reset signal for theReference clock domain. User can synchronize this reset to ref_clk domain.
tx_reset_reset_n input An active-low asynchronous reset signal for thetx_clk_clk domain. User can synchronize this reset to tx_clk_clk domain.
mm_reset_reset_n input An active-low reset signal for the control and status interfaces. User can synchronize this reset to mm_clk_clk domain.
dc_tx_reset_reset_n(1) input An active-low reset signal for the dual-clock FIFO dc_tx_clk_clk domain. User can synchronize this reset to dc_tx_clk_clk domain.
dc_rx_reset_reset_n(1) input An active-low reset signal for the dual-clock FIFO dc_rx_clk_clk domain. User can synchronize this reset to dc_tx_clk_clk domain.
Note:(1) – Only available when Dual-Clock FIFO Option is selected
Figure 5.4.3 below shows an example of the clock and reset connection between the 10-Gbps Ethernet MAC MegaCore and the PHY IP MegaCore.
Figure 5.4.3 10-Gbps Ethernet MAC MegaCore and PHY IP MegaCore Clock and Reset Example Connection
5.5 Transceiver ReconfigurationThe transceiver reconfiguration requirement is device dependent and the interface is similar between all the Ethernet IPs. Table 5.5.1 shows the summary of the Transceiver reconfiguration interface for PHY IP MegaCore and 10GbE MAC with PHY Design Example.
Table 5.5.1 10GbE MAC with PHY Design Example Clock and Reset Domain SummaryPHY IP MegaCore 10GbE MAC with PHY
Design ExampleDirection
Description
reconfig_from_xcvr reconfig_from_xcvr_reconfig_from_xcvr
output Reconfiguration signals from the XAUI transceiver to the Transceiver Reconfiguration IP Core. This output is synchronized to Avalon-MM Clock.
reconfig_to_xcvr reconfig_to_xcvr_reconfig_to_xcvr
input Reconfiguration signals from the Transceiver Reconfiguration IP Core to the XAUI transceiver. This input is synchronized to Avalon-MM Clock.
Refer to Altera Transceiver PHY IP Core User Guide for more details regarding the Transceiver Reconfiguration Controller.
5.6 Control InterfaceThe 10-Gbps Ethernet Reference Design has the following control interfaces:
Flow Control Interface ECC Option Interface MDIO Interface
5.6.1 Flow Control InterfaceTable 5.6.1.1 shows the flow control interface comparison between 10-Gbps Ethernet Reference Design and 10-Gbps Ethernet MAC MegaCore.
Table 5.6.1.1 10-Gbps Ethernet Reference Design and 10-Gbps Ethernet MAC MegaCore Flow Control Interface10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
10GbE MAC with PHY Design Example
Direction Description
xon_request avalon_st_pause_data[0] eth_10g_design_example_0_avalon_st_pause_data[0]
input Assert this signal to generate XON pause frame.
xoff_request avalon_st_pause_data[1] eth_10g_design_example_0_avalon_st_pause_data[1]
input Assert this signal to generate XOFF pause frame.
Alternatively, the flow control frame generation can be request through configuration register. Refer to Configuration section for more details.
The 10-Gbps Ethernet MAC MegaCore also supports the IEEE 802.1Qbb Priority Flow Control (pfc) and a separate control interface is dedicated for Priority Flow Control. The priority flow control feature is NOT supported in the 10-Gbps Ethernet Reference Design.
5.6.2 ECC Option InterfaceThe ECC Option is NOT supported in the 10-Gbps Ethernet MAC MegaCore.
5.6.3 MDIO InterfaceThe MDIO interface is used to configure external PHY device. However, MDIO is NOT included in the 10-Gbps Ethernet MAC MegaCore but as part of the 10GbE MAC with PHY Design Example solution. Table 5.6.3.1 shows the summary of the MDIO interface between 10-Gbps Ethernet Reference Design and 10GbE MAC with PHY Design Example.
Table 5.6.3.1 10-Gbps Ethernet Reference Design and 10GbE MAC with PHY Design Example MDIO Interface10-Gbps Ethernet Reference Design
10GbE MAC with PHY Design Example
Direction Description
phy_mdc mdio_mdc output management data clockphy_mdio_in mdio_mdio_in input management data input
phy_mdio_out mdio_mdio_out output management data outputphy_mdio_oen mdio_mdio_oen output management data output
enable
5.7 Status InterfaceThe 10-Gbps Ethernet Reference Design support only two status output to provide the VLAN and Stack VLAN detection status. The VLAN and Stack VLAN detection is also supported as part of the Avalon-ST Status Interface on the 10-Gbps Ethernet MAC MegaCore. Two Avalon-ST Status Interfaces available are:
Avalon-ST Receive Status Interface Avalon-ST Transmit Status Interface
5.7.1 Avalon-ST Receive Status InterfaceThe VLAN tag and stack VLAN tag detection status can be determine on the Avalon-ST Status Interface. Refer to the following section in the 10-Gbps Ethernet MAC MegaCore User Guide for more information:
Table 6-6. Avalon-ST Status Interface Signals for signals descriptions Figure 6-7. Avalon-ST Receive for example Avalon-ST Status waveform
Table 5.7.1.1 show the Avalon-ST Receive Status interface with descriptions.
Table 5.7.1.1 10-Gbps Ethernet MAC MegaCore Avalon-ST Receive Status Signals10-Gbps Ethernet MAC MegaCore Avalon-ST Status Signal
10GbE MAC with PHY Design Example
Direction Width Description
avalon_st_rxstatus_valid eth_10g_design_example_0_avalon_st_rxstatus_valid
output 1 When asserted, this signal indicates that avalon_st_rxstatus_data[] contains valid information about the receive frame.
The IP core asserts this signal in the same clock cycle itreceives the end of packet (avalon_st_rx_endofpacketis asserted).
avalon_st_rxstatus_data eth_10g_design_example_0_avalon_st_rxstatus_data
output 40 Contains information about the receive frame:■ Bits 0 to 15: Payload length.■ Bits 16 to 31: Packet length.■ Bit 32: When set to 1, indicates a stacked VLAN frame.■ Bit 33: When set to 1, indicates a VLAN frame.■ Bit 34: When set to 1, indicates a control frame.■ Bit 35: When set to 1, indicates a pause frame.■ Bit 36: When set to 1, indicates a broadcast frame.■ Bit 37: When set to 1, indicates a multicast frame.■ Bit 38: When set to 1, indicates a unicast frame.■ Bit 39: When set to 1, indicates a PFC frame.
The IP core presents the valid information on this bus in the same clock cycle it asserts avalon_st_rxstatus_valid. The information on this data bus is invalid when an overflow occurs or when CRC and/or padding removal is enabled.
avalon_st_rxstatus_error eth_10g_design_example_0_avalon_st_rxstatus_error
output 7 When set to 1, each bit of this signal indicates an error type in the receive frame.■ Bit 0: Undersized frame.■ Bit 1: Oversized frame.■ Bit 2: Payload length error.■ Bit 3: CRC error.■ Bit 4: Unused.■ Bit 5: Unused.■ Bit 6: PHY error.
The IP core presents the error status on this bus in the same clock cycle it asserts avalon_st_rxstatus_valid. The error status is invalid when an overflow occurs or when CRC and/or padding removal is enabled.
5.7.2 Avalon-ST Transmit Status InterfaceTable 5.7.2.1 show the Avalon-ST Transmit Status interface with descriptions.
Table 5.7.1.2 10-Gbps Ethernet MAC MegaCore Avalon-ST Transmit Status Signals10-Gbps Ethernet MAC MegaCore Avalon-ST Status Signal
Direction Width Description
avalon_st_txstatus_valid output 1 When asserted, this signal indicates that avalon_st_txstatus_data[] contains valid information about the transmit frame.
avalon_st_txstatus_data output 40 Contains information about the transmit frame:■ Bits 0 to 15: Payload length.■ Bits 16 to 31: Packet length.■ Bit 32: When set to 1, indicates a stacked VLAN frame.■ Bit 33: When set to 1, indicates a VLAN frame.■ Bit 34: When set to 1, indicates a control frame.■ Bit 35: When set to 1, indicates a pause frame.■ Bit 36: When set to 1, indicates a broadcast frame.■ Bit 37: When set to 1, indicates a multicast frame.■ Bit 38: When set to 1, indicates a unicast frame.■ Bit 39: When set to 1, indicates a PFC frame.The IP core asserts the valid information on this bus in the same clock cycle it asserts avalon_st_txstatus_valid. The information on this data bus is invalid when an overflow occurs or when CRC and/or padding insertion is enabled.
avalon_st_txstatus_error output 7 When set to 1, each bit of this signal indicates an error type in the receive frame.■ Bit 0: Undersized frame.■ Bit 1: Oversized frame.■ Bit 2: Payload length error.■ Bit 3: Unused.■ Bit 4: Underflow.■ Bit 5: Client error.■ Bit 6: Unused.The IP core presents the error status on this bus in the same clock cycle it asserts avalon_st_txstatus_valid. The error status is invalid when an overflow occurs or when CRC and/or padding removal is enabled.
6. Configuration RegisterThis chapter will discuss the following:
Register Addressing Register Map Register Configuration
6.1 Register AddressingIt is very important that you understand which register addressing mode on all the Ethernet MegaCores and Reference design. Table 6.1.1 shows the summary of the addressing mode for all the Ethernet MegaCores and reference design.
Table 6.1.1 Register Addressing Mode for Altera Ethernet IP Cores Comparison Summary10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
Addressing Mode DWord(1)
AddressingDWord(1)
AddressingDWord(1)
AddressingByte Addressing
Note:(1) – Double Word (32bits)
The conversion between Dword and Byte addressing are straight forward. Conversion from the byte offsets to dword offsets can be done by just dividing the byte offsets by 4. For example:
rx_padcrc_control in Byte offset = 0x100 rx_padcrc_control in DWord offset = 0x100 / 4 = 0x040
6.2 Register MapTable 6.2.1 shows the Avalon-MM address width summary.
Table 6.2.1 Avalon-MM Address Width Summary10-Gbps Ethernet Reference Design
10-Gbps Ethernet MAC MegaCore
XAUI/10G-Base-R PHY IP MegaCore
10GbE MAC with PHY Design Example
Address Width 9 bits 13 bits 9 bits 19 bits
Refer to Table 5-1. Summary of Register Address Expansion in 10-Gbps Ethernet MAC MegaCore Function User Guide for the 10-Gbps Ethernet MAC MegaCore register address mapping.
Refer to Table 3-2. Base Addresses of Design Example Component in 10-Gbps Ethernet MAC MegaCore Function User Guide for the 10GbE MAC with PHY Design Example base address.
Please take note that the configuration register map is much larger than the 10-Gbps Ethernet Reference Design and this is because the larger register map is used for new feature enhancement in the future. When perform migration to new Ethernet MegaCore, please reserve enough register space for future upgrade.
6.3 Register ConfigurationRegister configuration between 10-Gbps Ethernet Reference Design and 10-Gbps Ethernet MAC MegaCore is not directly compatible so it is advisable to study and understand the configuration register available on the 10-Gbps Ethernet MAC MegaCore before you start changing the configuration.
Refer to 5.2. Register Initialization in the 10-Gbps Ethernet MAC MegaCore Function User Guide to understand some basic register configuration required for the 10GbE MAC with PHY Design Example.
Refer to 5.1. MAC Registers in the 10-Gbps Ethernet MAC MegaCore Function User Guide to understand the MAC configuration register.
Table 6.3.1 shows some example configuration comparison between 10-Gbps Ethernet Reference Design and 10-Gbps Ethernet MAC MegaCore.
Table 6.3.1 10-Gbps Ethernet Reference Design and 10-Gbps Ethernet MAC MegaCore Register Configuration ExamplesDescription 10-Gbps Ethernet Reference
Design10-Gbps Ethernet MAC MegaCore
Configure MAC Address = 00-1C-23-17-4A-CB
mac_0 = 0x23174ACB mac_1 = 0x0000001C
MAC Address For TX Address Insertion: tx_addrins_macaddr0 = 0x23174ACB tx_addrins_macaddr1 = 0x0000001C
MAC Address For RX: rx_frame_addr0 = 0x23174ACB rx_frame_addr1 = 0x0000001C
Configure MAC maximum frame length = 1518
frm_length = 1518 MAC TX Maximum Frame Length: tx_frame_maxlength = 1518
MAC RX Maximum Frame Length: rx_frame_maxlength = 1518
Confugure MAC minimum IPG = 12
tx_ipg_length = 12 Not Available, the 10-Gbps Ethernet MAC MegaCore IPG is control by Deficit Idle Counter (DIC) with an average IPG of 12
Enable Promiscuous Mode
Set PROMIS_EN bit to 1 in command_config register
Set EN_ALLUCAST and EN_ALLMCAST bit to 1 in rx_frame_control regiser
Enable Padding and CRC Insertion on Transmit path
Padding and CRC Insertion is always enable on the TX path
Enable Padding insertion on TX Path: tx_padins_control = 0x1
Enable CRC insertion on TX Path: tx_crcins_control = 0x3
Enable Padding and CRC removal on Receive path
Enable Padding removal on RX path: Set PAD_EN bit to 1 in
command_config register
Enable CRC removal on RX path: Set CRC_FWD bit to 0 in
command_config register
Enable Padding and CRC removal on RX path: rx_padcrc_control = 0x3
Enable Source MAC Address Insertion on Transmit Path
Set TX_ADDR_INS bit to 1 in command_config register
Enable MAC Source Address Insertion on TX path: tx_addrins_control = 0x1
Configure Pause Quanta for flow control = 0xFFFF
pause_quant = 0xFFFF tx_pauseframe_quanta = 0xFFFF
Enable Pause Frame Generation
Not Available, Pause frame generation is always enable
tx_pauseframe_enable = 0x1
Generate XON/XOFF Frame
Set XON_GEN bit to 1 in command_config register
Set XOFF_GEN bit to 1 in command_config register
Generate XON Frame: tx_pauseframe_control = 0x1
Generate XOFF Frame: tx_pauseframe_control = 0x2
Forward Pause Frame Set PAUSE_FWD bit to 1 in command_config register
Set FWD_PAUSE bit to 1 in rx_frame_control register
Ignore received Pause Frame
Set PAUSE_IGNORE bit to 1 in command_config register
Set IGNORE_PAUSE bit to 1 in rx_frame_control regiser
Forward All Control Frame except Pause Frame
Set CNTL_FRM_ENA bit to 1 in command_config register
Set FWD_CONTROL bit to 1 in rx_frame_control regiser
Configure and Enable Supplemental MAC Address. Eg. Supplemental Address 0 = 00-1C-23-17-4A-CB
Configure Supplemental Address 0: smac_0_0 = 0x23174ACB smac_0_1 = 0x0000001C
Enable Supplemental Address 0: Set bit 31 to 1 in smac_0_1
to enable smac_0_1 =
0x8000001C
Configure Supplemental Address 0: rx_frame_spaddr0_0 = 0x23174ACB rx_frame_spaddr0_1 = 0x0000001C
Enable Supplemental Address 0: Set EN_SUPP0 bit to 1 in rx_frame_control
regiser
Clear all Statistic Counter
Set CNT_RESET bit to 1 in command_config register
Clear TX Statistic Counter: tx_stats_clr = 0x1
Clear RX Statistic Counter: rx_stats_clr = 0x1
Enable Transmit Path Set TX_ENA bit to 1 in command_config register
tx_transfer_control= 0x0
Enable Receive Path Set RX_ENA bit to 1 in command_config register
rx_transfer_control= 0x0
6.4 Statistic CounterRefer to byte address offset 0x3000:0x3FFF for RX Statistics Counters and 0x7000:0x7FFF for TX Statistic Counter in Table 5-2. MAC Register in 10-Gbps Ethernet MAC MegaCore Function User Guide.
7. Timing Constraints Figure 7.1 shows a 10-Gbps Ethernet design example with XAUI interface. This chapter will show you step by step how to constraints the design.
Figure 7.1 10-Gbps Ethernet MAC MegaCore and PHY IP MegaCore Example DesignStep 1: Identify all the clock domain for each data path
o Reference Clock – 156.25Mhz from Oscillatoro Transmit Data Path – 156.25Mhz from Altera PLL
o Receive Data Path – 156.25Mhz from XAUI PHYo Avalon MM – 125Mhz from Altera PLLPlease take note that all clock domains in the example design are driven by different clock.
Step 2: Identify the top level input clocko REF_CLK Input – 156.25Mhz from Oscillatoro SYS_CLK Input – 100Mhz from Oscillator
Step 3: Create top level timing constraint file (.sdc)1. Create a new timing constraint file with the file extension is .sdc. For this example, we will
name the timing constraint file, top.sdc2. Use the “create_clock” command to create all the top level input clock. Example:
create_clock -name sysclk -period 10.000 [get_ports {SYS_CLK}]create_clock -name refclk -period 6.400 [get_ports {REF_CLK}]
Step 4: Constraint all the generated clock1. Identify if there’s any PLL or transceiver used in the design.2. If yes, use the “derive_pll_clocks” command to derive all the generated clocks
derive_pll_clocks3. With the “derive_pll_clocks” command, all the clock output from the PLL or transceiver will
be created. For example, it will clock for transmit data path, receive data path and Avalon-MM in the example design.
Step 5: Add all timing constraint files into Quartus II project1. Launch Quartus II2. Go to Assignments -> Settings3. Select TimeQuest Timing Analyzer on the Category menu4. Add all the timing constraint file and IP variation file (.qip) and click OK
5. Select Processing -> Start Compilation to start full compilation
Step 6: Create timing netlist and add SDC files in TimeQuest Timing Analyzer1. Select Tools -> TimeQuest Timing Analyzer to launch TimeQuest Timing Analyzer2. Double clicks on Create Timing Netlist on the Tasks menu
3. Double clicks on Read SDC File to add all the required SDC files
Please take note that you need to ensure that TimeQuest Timing Analyzer able to detect all the IPs SDC files and do not add the SDC files manually. If TimeQuest Timing Analyzer fails to detect all the SDCfiles, repeat Step 5.
4. Double clicks on Update Timing Netlist to update the design timing netlist with SDC files.
Step 7: Check the design timing report1. Double click on “Report Top Failing Paths” to report top failing path summary.
2. Alternatively, use the following command to report top failing path summary.qsta_utility::generate_top_failures_per_clock "Top Failing Paths" 200
3. Click on Report -> Top Failing Paths and check all the failing path report. The design is fully meet the entire timing requirement when “No failing paths found.” is reported.
8. ReferencesRefer to the related documentation below to understand more:
10-Gbps Ethernet Reference Design User Guide 10-Gbps Ethernet MAC MegaCore Function User Guide
Altera Transceiver PHY IP Core User Guide Embedded Peripherals IP User Guide AN588: 10-Gbps Ethernet Hardware Demonstration Reference Design AN638: 10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration
Reference Design 10-Gbps Ethernet IP Core Resource Center
