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DR.AMBEDKAR INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
SUBJECT CODE: CSL37
SUBJECT: LOGIC DESIGN LAB
TOPIC: SIMULATION
NAME:
USN:
SECTION:
BATCH:
1(b). Simulate the simplified logic expression using VHDL and verify it’s working.
F=A’B+AB’+ABC
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
2(b). Simulate the above combinational circuit using VHDL and verify it’s working.
FULL ADDER
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
FULL SUBTRACTOR
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
MAGNITUDE COMPARATOR
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
3(b).Design and develop the VHDL code for 8:1 Multiplexer. Simulate and verify it’s working.
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
4(b).Simulate 3:8 Decoder using VHDL and verify it’s working.
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
5(b). Design and develop the VHDL code for D Flip Flop.
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
6(b). Design and develop the VHDL code for Switched Tail counter. Simulate and verify it’s working.
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN:
8(b). Design and develop the VHDL code for Mod-8 up counter. Simulate and verify it’s working.
VHDL CODE:
INPUT SCREEN:
OUTPUT SCREEN: