PREFACE

Subject Name: ELECTRONICS DEVICES AND CIRCUITS (EDC)

Dear Students,

It gives me the immense pleasure to handover this lab manual of the Electronics Devices and Circuits.

Semiconductor devices like Diodes, Bipolar Junction Transistors and MOSFETs are very important basic Components of any electronic circuit. Many digital integrated circuits and analog circuits are designed

using these components.

The important applications of the FET is as a switch and an amplifier. FETs/MOSFETs are used in various other applications like oscillators, feedback amplifiers, large and small signal amplifiers. MOSFETs are used for analog and digital circuit design. They are widely used in VLSI technology on FPGA or CPLD.

The practicals of this subject are divided into hardware and software practicals. Hardware practical’s to be performed on bread board and simulation practical’s to be performed using MULTISIM software on PC.

At the end of the term students need to appear for 50 marks university practical Exam.

Students should perform all the experiments and 100% attendance for practicals is must to appear for final university Examination.

In practical examination external examiner appointed by university will come to assess the Students. Students are assessed based on practical performance and oral, related to subject knowledge.

As students in second year are going to appear first time for university practical examination, before final university examination mock examination is conducted for preparation.

My Best Wishes to all of you for your academic performance in the semester

Prof. J.A. Lele Assistant Professor

Dept. of E&TC, MITCOE, pune-38

Mission of the InstituteTo be a Globally, Socially conscious institute of research and innovation

with an excellence in professional education and to take up the challenges of change for benefit of the society.

Vision of the InstituteTo empower young generation for substantial contribution to

economical, technological and social development of the society.

Mission of the DepartmentTo create an environment that shall foster the growth of intellectually capable, innovative professionals who can contribute for the welfare of

the mankind.

Vision of the DepartmentTo become leading Department with excellence in academics to develop

technologically and ethically strong individuals.

MIT COLLEGE OF ENGINEERING, KOTHRUD,

PUNE

Programme Educational Objectives (PEOs), Programme Outcomes (POs), Course Outcomes (COs) and their

Mapping

Department: Electronics and Telecommunication Academic Year: 2016-17

Programme Educational Objectives (PEOs)

I To prepare students for advanced education, research and development, and other creative efforts in the field of Electronics and Telecommunication Engineering.

II To develop students to apply fundamental knowledge, Basic Science, Mathematical models to real life projects.

III

To become industry ready and practice the profession of engineering using a systems perspective and analyze, design, develop, optimize and implement complex

Electronics and Telecommunication systems.

IV

To inculcate in students effective teamwork, collaboration, communication with colleagues and multidisciplinary approach.

V To provide students life-long learning atmosphere to exercise leadership and incorporate societal needs and constraints in their professional endeavors.

Programme Outcomes (POs)

After successful completion of graduation Graduates will have

a) An ability to apply knowledge of mathematics, basic sciences and engineering.

b)An ability to identify, formulate and solve complex engineering problems reaching substantial conclusions.

c) An ability to design and conduct experiments, analyze and interpret data.

d) An ability to design a system/process to meet desired needs based on innovative ideas.

e) An ability to function on multidisciplinary tasks.

f) An ability to use modern engineering tools, software and equipments to analyze problems.

g) An understanding of professional and ethical responsibility.

h) An ability to communicate effectively and work in team.

i)An ability to understand the impact of engineering solutions in a global, economic, environmental and social context.

j) Knowledge and an ability to deal with contemporary issues.

k) An ability to engage in lifelong learning in broadest context of technological change.

l) An ability to manage all aspects of project work including finance.

PSO1 An ability to analyze and simulate diverse problems in the field of Electronics and Telecommunication.

PSO2 An ability to Design & Implement application oriented engineering systems using Embedded Platform.

Mapping of Programme Educational Objective & Programme Outcomes:-

PEOS

POs PSOs

a b c d e f g h i j k l PSO1 PSO2

I H M M H H H M H L L H L H H

II H H H H M H L M M H H

III M H H M L M H M H M L H H H

IV L H H H M H L H M M

V L M H H L H M M M

Course Outcomes:

After successfully completing the course students will be able to

Course Outcomes

CO-I Comply and verify parameters after exciting devices by any stated method.

CO-II Simulate/Implement hardwired circuit to test the performance and application for what it is being designed.

CO-III Analyze and model FET and MOSFET for small signal at low and high frequency.

CO-IV Apply concept of feedback to improve stability of circuits.

CO-V Design a variable voltage regulator circuits

Mapping of Course Outcomes & Programme Outcomes:-

Course Outcomes Programme Outcomes

a b c d e f g h i j k

CO-1 H H H L M M M L

CO-2 M H H H M M M M

CO-3 H H H H M M M L L L

CO-4 M H H H M M M L L L

CO-5 M H H H M M L L M

Summary M H H H M M M L L L

MIT College of Engineering, Pune.Electronics and Telecommunication Department

(Electronic Devices and Circuits Lab)

LIST OF THE EXPERIMENTSSubject: EDC Academic Year/Sem: 2016-17 /I

Sr. No. Title of Experiment

COsMapped

No of Hrs Required

Page No

1. Design a single stage FET in CS configuration and verify DC operating point.

I,II 2

2. Build, Test & simulate single stage CS (FET) amplifier. Calculate Ri, Ro and Av.

I,II,III 4

3. Simulate frequency response of single stage CS amplifier (use same circuit) and find the bandwidth

II,III 2

4. Implement Voltage-Series feedback amplifier and calculate Rif, Rof, Avf and Bandwidth.

I,II,IV 4

5. Simulation of current shunt feedback amplifier and find Rif, Rof and Bandwidth.

I,II,IV 2

6. Simulation of FET oscillator and calculate output voltage and frequency.

I,II,IV 2

7. Implement Wein bridge /RC phase shift/ Hartley /Colpitts oscillator using MOSFET.

I,II,IV 4

8. Simulate MOSFET Inverter (Observe Dynamic Characteristics).

II,III 2

9. Build and test MOSFET as a switch. II,III 2

10. Design and implement a variable voltage regulator using three terminals IC.

II,V 2

11. Implement Complementary symmetry push pull amplifier.

II 2

PREPARED BY Prof. J.A.Lele APPROVED BY Prof.(Dr.)V.V.Shete PAGE No.: 01 OF 01

DSGN: Prof.SIGN:

DSGN: H.O.DSIGN:

The course structure includes the following:

Code Subject Short Name

Weekly load(in Hrs) Semester Examination Scheme of Marks

Lectures Tutorials PR/DRG

TheoryTW PR OR MAX.

MARKSPaper Online

204182

Electronic Devices and

CircuitsEDC 04 -- 02 50 50 -- 50 -- 150

General Instructions

All students have to attend laboratory sessions or classes with punctuality and preparation. Requisite records should be brought to the classes and instructions should be followed accordingly. Students should safe-guard their personal belongings and valuables. Students are encouraged to voice their opinions and engage each other in healthy technical discussions

and debates. Students should keep their bags properly inside the lab in the predefined area. Students should switch off the computers, fans, and such other appliances after their sessions.

Prof. S. M. KulakarniAssistant ProfessorElectronics and Telecommunication Engineering Department

EXPERIMENT NO. : 1

AIM : Design a single stage FET in CS configuration and verify DC operating Point.

OBJECTIVES : 1.Build & test FET common source (CS) amplifier.

2. Measure the voltage gain, input resistance (Ri), output Resistance (Ro)

of the amplifier.

COMPONENTS :

APPARATUS :

THEORY :The schematic of an n-channel JFET along with its circuit symbol is shown in Figure. From the

layered structure shown by Figure 1a, it is clear that the n-channel JFET has its major portion

made of n-type semiconductor. The mutually-opposite two faces of this bulk material from the

source and the drain terminals. Further, it is also seen that there are two relatively-small p-

regions embedded into this substrate which are internally joined together to form the gate

terminal. Thus, here, the source and the drain terminals are of n-type while the gate is of p-

type. Due to this, two pn junctions will be formed within the device, whose analysis reveals the

mode in which the JFET works. Further the circuit symbol shown by Figure 1b has an arrow

pointing towards the device at its Gate terminal which indicates the direction in which the

current would flow, provided the pn junction is forward biased.

Component Value

JFET

Resistors

Capacitors

Instrument Specifications

Power Supply

CRO

Function Generator

DMM

Id Smaller Rd

Vdd / RdVgs= Vtn + 2.0

Q pointLargerRd V = V

tn+ 1.5

gs

Vgs= Vtn + 1.0

V VV

ds

The effect of a drain resistor in the comnon-source configuration:

+Vdd

R DKVL: Vdd = I d Rd + Vds

Id Vout

Vds

Vgs

This is the equation of a line that can be superimposed on the FETI-V characteristics as shown at right. This is the “load-line”.• The points of intersection represent the allowed device voltages and

drain current for the resistor-FET combination. These are the “quiescent” operating conditions or “Q points”, i.e. the DC bias conditions.

• There are a number of possible Q-points along the load-line, depending on the gate voltage. It is the job of the circuit designer to choose this Q-point.

• The choice of Q-point will vary with the circuit application. For simple amplifier circuits a Q-point in the middle of the saturation region is often desirable.

CIRCUIT DIAGRAM:

DESIGN : For BFW 10/11,

From Data sheet,

IDSS = 10 mA and VP = -3 V

Let, ID= 0.4 mA

Formula : ID= IDSS [1- (VGS / VP)]2---------------------(1)

0.4= 10 [1- (VGS / -3]2

VGS = -2.4 V

Rs = VGS / ID

Rs = -2.4 / 0.4

Rs = 6 KΩ

Consider,

VDS = VDD / 2

VDS = 6V

Apply KVL, we get

VDD = VDS + ID (RD + Rs)

12 = 6 + 0.4 Χ 10-3 (RD + 6 Χ103) RD = 9 KΩ

Select RS =RD =6.8 KΩ

Ig= 10000 nA ……. (From data sheet)

RG =VGS /IG = 2.4 / 10,000 Χ 10 -9 = 0.2MΩ

Select RG = 1 MΩ

PROCEDURE :

1. Implement the CS amplifier for DC analysis on general purpose breadboard.

2. Make the connections as per the circuit diagram.

3. Apply the dc power supply VDD of +12 V.

4. Measure the drain current ID, VDS and VGS voltages across the JFET.

5. Draw the DC load line and plot the ID vs VDS voltage on graph paper.

Also plot VGS voltage on graph paper.

OBSERVATION TABLE:

RESULT :

IDQ VDSQ VGSQ

Parameter TheoreticalValue

PracticalValue

IDQ

VDSQ

VGSQ

CONCLUSION

:--------------------------------------------------------------------------------------------------------

QUESTIONS :

1. What is DC operating point? How to fix it?

2. Compare JFET configurations.

3. Explain construction and working of N-channel JFET.

4. Explain JFET V-I characteristics and fix the Q point from your readings on it. (do it on graph

Paper.)

EXPERIMENT NO. : 2

AIM : Build and simulate Single Stage CS amplifier. Calculate Ri , Ro and Av.

OBJECTIVES : 1. Build & test FET common source (CS) amplifier

2. Measure the voltage gain, input resistance (Ri), output Resistance

(Ro) of the amplifier

COMPONENTS :

Component Value

JFET

Resistors

Capacitor

APPARATUS :

THEORY :

Figure 2

Figure 2. shows V_I characteristics of the n-channel JFET. The ohmic region is where the

drain to source voltage is small and drain current in nearly proportional to the drain to source voltage.

When a positive drain to source voltage is applied, this voltage increases from zero to a small value, the

Instrument Specifications

Power Supply

CRO

Function Generator

DMM

depletion region width remain very small and under this condition the semiconductor bar

behaves just like a resistor. So, drain current increases almost linearly with drain to source voltage.

In the saturation region, the drain current is almost constant and it is not

dependent on the drain to source voltage actually. When the drain to source voltage continuous to

increase the channel resistance increases and at some point, the depletion regions meet near the drain to

pinch off the channel. Beyond that pinch off voltage, the drain, current attains saturation.

In The breakdown region, the drain current increases rapidly with a small

increase of the drain to source voltage. Actually for large value of drain to source voltage, a breakdown

of the gate junction takes place which results a sharp increase of the drain current.

CIRCUIT DIAGRAM:

DESIGN : For BFW 10/11,

From Data sheet,

IDSS = 10 mA and VP = -3 V

Let ID= 0.4 mA

Formula : ID= IDSS [1- (VGS / VP)] 2--------------------- (1)

0.4= 10 [1- (VGS / -3] 2

VGS = -2.4 V

Rs = VGS / ID

Rs = -2.4 / 0.4

Rs = 6 KΩ

Consider, VDS = VDD / 2

VDS = 6V

Apply KVL, we get

VDD =VDS + ID (RD + Rs)

12 = 6 + 0.4 Χ 10-3 (RD + 6 Χ103) RD = 9 KΩ

Select RS =RD =6.8 KΩ

Ig = 10000 nA …… (From data sheet)

RG =VGS /IG = 2.4 / 10,000 Χ10 -9 = 0.2MΩ

Select RG =1 MΩ

For Capacitor

XCS = (1/ 100) Rs at 500 Hz

XCS = 6.8 KΩ/100 = 68 Ω

So, Cs=1/ ( 2 π Χ 500Hz Χ 68 Ω) = 4.6 µF

Select Cs = 10 µF

Similarly,

XC1 = (1/ 100) RG at 500 Hz

XC1 = (1/ 100) 2 Χ 105 = 2 KΩ

So, Cc1= 1/ (2 π Χ 500 Χ 2 Χ 103 ) = 0.15µF

Select CC1 = CC2 = 0.01 µF

From equation 1) gm= 10

Av = gm* RD = 90

PROCEDURE :1. Implement the CS amplifier on general purpose breadboard.

2. Make the connections as per the circuit diagram.

3. Apply sinusoidal input signal at 200mV, 1 kHz and adjust its

amplitude so as to get maximum undistorted output.

4. Measure the o/p (Vo) on CRO.

5. Apply the same I/P through R’ and measure the O/P voltage (Vo’).

6. Apply the I/P without R’. Connect the R’’ across the O/P. Measure

the O/P voltage (Vo’’).

7. Calculate the Ri and Ro as per the given Formula and calculate the

voltage gain theoretically.

8. Draw the I/P & O/P waveforms on graph sheet.

OBSERVATION TABLE:

R’= R”=

Vi Vo Vo’ Vo’’

FORMULA : Av=Vo/Vi

Ri = [Vo’/ (Vo-Vo’)] Χ R’

Ro = [(Vo-Vo’’)/Vo’’)] Χ R’’

CALCULATION :

1. Av =

2. Ri =

3. Ro =

RESULT :

Parameter Practically measured

Av

Ri

Ro

CONCLUSION

:-------------------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------------------------

------

QUESTIONS :

1. Draw AC equivalent circuit of above amplifier & perform small signal analysis. Find Av, Ri

Ro theoretically.

2. Explain E-MOSFET characteristics and parameters.

3. Explain Non-ideal voltage current characteristics of the MOSFET.

EXPERIMENT NO. : 3

AIM : Simulate frequency response of single stage CS amplifier (use same circuit) and find the bandwidth.

OBJECTIVES : 1. Simulate frequency response of FET common source (CS) amplifier

2. With the analysis, find the bandwidth.

APPARATUS : PC with Multisim 2001

CIRCUIT DIAGRAM:

THEORY:

On the X axis we plot the frequency in Hz whereas the voltage gain Av in decibels (dB) is plotted on the Y-axis.

Ideally the frequency response should be flat over the entire frequency range. The typical frequency response of a CS amplifier is shown in above figure. In the usual application, mid band frequency range are defined as those frequencies at which the

response has fallen to 3dB below the maximum gain (|A| max). These are shown as fL and fH and are

called as the 3dB frequencies are simply the lower and higher cut off frequencies respectively. The

difference between higher cut off and lower cut off frequency is referred to as bandwidth (fH - fL).

PROCEDURE :1. Connect the circuit as shown in the circuit diagram on multisim.

2. Apply sinusoidal input signal at 200mV, 1 kHz and adjust its amplitude so as

to get

maximum undistorted output.

3. Keeping input voltage constant vary the frequency from 1 Hz to 10 MHz in

regular steps and note down the corresponding output voltage.

4. Plot the graph: gain (dB) verses Frequency on a semi log graph sheet.

5. Calculate the bandwidth from the graph.

6. Calculate voltage gain

CALCULATIONS:

FL=

FH=

Bandwidth= FH - FL =

CONCLUSION :-------------------------------------------------------------------------------------------------

-----------------------------------------------------------------------------------------------------------------------------

----------------

QUESTIONS: 1. Explain frequency response of FET CS amplifier?

2. Why there is roll off at low frequencies and at high frequencies?

3. Draw high frequency

EXPERIMENT NO: 4

AIM : Implement voltage-series feedback amplifier. Calculate Rif, Rof, Avf and Bandwidth.

OBJECTIVES : 1. Build & test FET common source (CS) amplifier.

2. Measure the voltage gain, input resistance (Ri), output Resistance (Ro) and

bandwidth of the amplifier.

COMPONENTS:

APPARATUS:

THEORY :

If an amplifier has feedback path exists from output to input then that amplifier is termed as

Feedback amplifier.There are four different types of feedback topologies based on type of output

signal and feedback signal (voltage or current signal). Voltage feedback is taken in parallel with the

load and current feedback is taken in series with the load. They are

Name Value

JFET BFW 11

Resistors

Capacitors

Instrument SpecificationsPower SupplyCROFunction GeneratorDMM

a)Voltage-series: Output signal is voltage signal, feedback signal is voltage

signal. Also called as series-series feedback. It is employed in voltage amplifiers.

b) Current series: Output signal is current signal, feedback signal is voltage signal. Also called

as shunt-series feedback. It is employed in Transconductance amplifiers.

C) Current shunt: Output signal is current signal, feedback signal is current

signal. Also called as shunt-shunt feedback. It is employed in current amplifiers.

d) Voltage shunt: Output signal is voltage signal, feedback signal is current signal. Also called as shunt-

shunt feedback. It is employed in current amplifiers.

The first word indicates the type of output signal and the second word indicates the manner in which

feedback signal is taken whether it is taken in series or shunt with the load.

CIRCUIT DIAGRAM:

DESIGN :

For BFW10/11, From Data Sheet,

VP = -3V and IDSS = 10mA

FORMULA : ID = IDSS[1-(VGS/Vp)]2

Given, Q condition is ID = 2mA.

We Know that,[ID / IDSS]1/2= 1-(VGS/Vp )1 – 0.44 =VGS/3

VGS = - 0.55 * 3 = -1.65 V

IDRS = |VGS|

Choose RS = 1KΩ and VDS = 5V =VDD/2

VDD = VDS + ID (RS + RD)RD = 1.5 KΩ

Igs= 1000nA (From Data Sheet).

Before conduction, minority carriers have to be drained out, for this RG would be usually very

large. Further input impedance of the amplifier would be equal to RG itself.

Thus, Igs RG = Vgs

RG = Vgs/Igs= 1.65MΩChoose RG = 2 MΩ

It should act as a short circuit at lowest frequency of interest.

XCS =(1/100) RS = 10Ω 1t 500Hz (say)CS = 1/2fXCS=CS = 33μF.

Choose CS = 33 or 47μF.

Theoretically, gain AV without feedback is calculated asAV = -gm RD

For the above circuit:gm is computed as below,

We have, ID = IDSS[1-(VGS/Vp )]2

Differentiating with respect to Vgs,|∂ID /∂VGS| = 2IDSS(1+VGS/VP) (1/VP))∂ ID /∂VGS= gm hence gm= 2(10)(1+1.65/3)( 1/3)gm= 10 mA/V|AV| = gmRD = 15.

To Design feedback circuit (R1, R2)Let us Assume gain with feedback gain desired is 2i.e. AVf = 2.

Then AVf=AV/1+AVβ where β = R2/R1+ R2

(Practically we may not get AV = 15,It is better to measure AV practically & design R1 & R2).

E.g: Say AV = 4.8 (Practical Value)AVf=AV/1+AV β 2/4.8 = 1/1+4.8 β R1 = 2.4 R2Choose R2 = 68KΩ, R1 = 165KΩ (150KΩ + 15KΩ).

PROCEDURE:

1. Make the connections as per the circuit diagram on bread board.

2. Adjust the amplitude of input such that you will get the maximum undistorted output

voltage (Sine Wave) in without feedback condition.

3. Observe input and output waveform simultaneously to see phase difference.

4. Measure the o/p voltage and i/p voltage. Calculate the voltage gain using given formula.

5. Apply the same i/p through R’ and Measure the o/p voltage (Vo’) across output

terminal. Calculate input resistance using given formula.

6. Apply the i/p w/o R’. Connect the R’’ across the o/p. Measure the o/p voltage (Vo’’)

and Calculate output resistance using given formula.

7. Repeat the above procedure for with feedback condition.

OBSERVATION TABLE:

R’ = R’’ =

Parameter Vi Vo Vo’ Vo’’Without FeedbackWith Feedback

CALCULATIONS:

Without Feedback with Feedback

1. Av = 1. AVf =

2. Ri = 4. Rif =

3. Ro = 3. Rof =

Verification of improvement in parameter.

1. AVf =

2. Rif =

3. Rof =

Bandwidth:

Without Feedback With Feedback

1. FL= 1. FL=

2. FH = 2.FH =

RESULT :

CONCLUSIO

N:________________________________________________________________________________

________________________________________________________________________________

QUESTIONS: 1. Why is negative feedback employed in high gain amplifier?

2. Justify the topology as voltage series feedback in the given circuit.

3. Explain any application of feedback amplifier.

Parameter

WithoutFeedback With Feedback

Simulated Simulated

Voltage Gain

Input Resistance

Output ResistanceBandwidth

EXPERIMENT NO: 5

AIM : Simulation of current shunt feedback amplifier, Calculate Rif, Rof, and bandwidth.

OBJECTIVE : 1. To identify topology of feedback with proper justification.

2. To measure voltage gain, input resistance, output resistance and bandwidth

for without feedback.

3. To measure voltage gain, input resistance, output resistance and bandwidth

for with feedback.

4. To verify the improvements in various parameters as per the derived

equations.

APPARATUS : PC with Multisim 2001

THEORY :

Some Properties of Negative Feedback

Gain desensitivity The negative reduces the change in the closed-loop gain due to open-loop gain variation

Desensitivity factor: 1+ A Bandwidth extension

High-frequency response of a single-pole amplifier:

Low-frequency response of an amplifier with a dominant low-frequency pole:

Negative feedback: Reduces the gain by a factor of (1+AM ) Extends the bandwidth by a factor of (1+AM )

Interference reduction The signal-to-noise ratio:

The amplifier suffers from interference introduced at the input of the amplifier Signal-to-noise ratio: S/I = Vs/Vn

Enhancement of the signal-to-noise ratio: Precede the original amplifier A1 by a clean amplifier A2 Use negative feedback to keep the overall gain constant

LAB MANUAL/EDC

Reduction in nonlinear distortionThe amplifier transfer characteristic is linearized through the application of negative feedback

β= 0.01Achanges from 1000 to 100

CIRCUIT DIAGRAM:

LAB MANUAL/EDC

PROCEDURE :

1. Make the connection as per the circuit diagram.

2. Adjust the amplitude of input such that you will get the maximum undistorted output

i) voltage (Sine Wave) in without feedback condition.

3. Observe input and output waveform simultaneously to see phase difference.

4. Measure the o/p voltage and i/p voltage. Calculate the voltage gain using given formula.

5. Apply the same i/p through R’ and Measure the o/p voltage (Vo’) across output

ii) terminal. Calculate input resistance using given formula.

6. Apply the i/p w/o R’. Connect the R’’ across the o/p. Measure the o/p voltage (Vo’’) and

Calculate output resistance using given formula.

7. Repeat the above procedure for with feedback condition.

8. Calculate the bandwidth by simulation using ac analysis

9. Verify the result as per the derived equation.

OBSERVATION TABLE:

R’ = R’’ =

Parameter Vi Vo Vo’ Vo’’Without FeedbackWith Feedback

FORMULA:

Av = Vo/Vin Ri = Vo’R’/(Vo-Vo’) Ro = (Vo – Vo”)R”/Vo”

Bandwidth = fH - fL

LAB MANUAL/EDC

CALCULATION:

Without feedback : With feedback :

1. Av = 1. AVf =

2. Ri = 2. Rif = 3. Ro= 3. Rof =

4. B.W= 4. B.W=

RESULT: With Feedback Without Feedback

Voltage Gain

Input Resistance

Output Resistance

Bandwidth

CONCLUSION :

QUESTIONS :

1) Verify the advantages for current shunt topologies.

2) Explain effect of negative feedback on input resistance on current shunt feedback.

3) Explain any application.

LAB MANUAL/EDC

EXPERIMENT NO: 6

AIM : Simulation of FET oscillator and calculate output voltage and frequency.

OBJECTIVES: 1. To simulate Hartley Oscillator and to calculate output voltage and frequency.

2. To simulate Colpitts Oscillator and to calculate output voltage and frequency.

APPARATUS: PC with Multisim 2001

THEORY: In a Hartley oscillator the oscillation frequency is determined by a tank circuit comprising of

two inductors and one capacitor. The inductors are connected in series and the capacitor is connected across

them in parallel. Hartley oscillators are commonly used in radio frequency (RF) oscillator applications and

the recommended frequency range is from 20KHz to 30MHz. Hartley oscillators can be operated at

frequencies lower than 20KHz, but for lower frequencies the inductor value need to be high and it has a

practical limit. The circuit diagram of a typical Hartley oscillator is shown in the figure below.

Part I: Simulation of Hartley oscillator

CIRCUIT DIAGRAM:

LAB MANUAL/EDC

PROCEDURE :

1. Make the connections on the simulator for Hartley and Colpitts Oscillator as per the

circuit diagram.

2. Measure the frequency at the output using the oscilloscope.

3. Measure the output voltage using Multimeter or Oscilloscope in simulator.

4. Verify the result as per the derived equation.

OBSERVATION TABLE:

Vout Frequency

Theoretical Frequency =

Part II : Simulation of Colpitts OscillatorTHEORY:

In Colpitts oscillator the tank circuit consists of two capacitors in series and an inductor connected in

parallel to the serial combination. The frequency of the oscillations is determined by the value of the

capcitors and inductor in the tank circuit.

Collpitts oscillator is generally used in RF applications and the typical operating range is 20KHz to

300MHz. In Colpitts oscillator, the capacitive voltage divider setup in the tank circuit works as the feed back

source and this arrangement gives better frequency stability when compared to the Hartley oscillator which

uses an inductive voltage divider setup for feedback. The circuit diagram of a typical Colpitts oscillator

using transistor is shown in the figure below.

LAB MANUAL/EDC

CIRCUIT DIAGRAM:

OBSERVATION TABLE:

Vout Frequency

Theoretical Frequency = 1. The frequency “F” of a Hartley and Colpitts oscillator can be expressed using the equation

RESULT : Theoretically From Simulation

Hartley Oscillator Vout = Vout = Frequency = Frequency =

Colpitts Oscillator Vout = Vout = Frequency = Frequency =

LAB MANUAL/EDC

CONCLUSION :

QUESTIONS :

1. State Barkhausen criteria and justify it for Hartley oscillator.

1. Explain advantages, disadvantages and applications of Hartley oscillator.

2. Write a short note on Colpitt’s oscillator.

3. Explain advantages, disadvantages and applications of Colpitt’s oscillator.

LAB MANUAL/EDC

EXPERIMENT NO: 7

AIM : Implement Wein Bridge/ RC phase shift / Hartley/ Colpitts oscillator using MOSFET

OBJECTIVE : Implement the FET circuit for RC phase shift oscillator

.

COMPONENTS:

APPARATUS :

THEORY : An oscillator acts as a generator, generating the output signal which

oscillates with constant amplitude & frequency. An oscillator does not require any input

Signal. For any circuit to act as an oscillator must satisfy Barkhausen’s criteria conditions.

1] The total phase shift around a loop is precisely 00 or 3600.

2] The magnitude of the product of the open loop gain of the amplifier (A) and the

magnitude of the feedback factor is unity i.e. A = 1.

Phase shift Oscillator:

The RC phase shift oscillator circuit can be realized by using transistorized amplifier.

In a RC phase shift oscillator, a common emitter (CE) single stage amplifier is used as a basic

Amplifier .This produces 1800 phase shift. The feedback network consists of three RC sections

each producing 1800 phase shift.

.

The output of amplifier is given to the feedback network .The output of the feedback

Name Value

JFET

Resistors

Capacitors

Instrument Range

Power Supply

CRO

Function generator

LAB MANUAL/EDC

network drives the amplifier. The total phase shift around a loop is1800 of amplifier and 1800

due to three RC network, thus 3600.This satisfies the condition for positive feedback and

circuit works as an amplifier.

. The frequency of sustained oscillations generated depends on values of R&C and is given by,

F= 1 / 2 6 RC

CIRCUIT DIAGRAM:

PROCEDURE:1. Make the connections as shown in circuit diagram.

2. Observe the sinusoidal output voltage.

3. Measure the frequency and compare with the theoretical values.

LAB MANUAL/EDC

OBSERVATION TABLE:

Theoretical Frequency =

RESULT :

CONCLUSION :

QUESTIONS :

1. Explain working of RC phase shift oscillator and Weinbridge oscillator.

2. Explain any application where it is used.

3. Justify Barkhausen’s criteria for above circuits.

EXPERIMENT NO: 8

Vout Frequency

Theoretical Practical

RC phase shift Oscillator

Vout = Vout =

Frequency = Frequency =

LAB MANUAL/EDC

AIM : Simulate MOSFET inverter (observe dynamic characteristics)

OBJECTIVE : Simulate MOSFET inverter and observe its dynamic characteristics.

APPARATUS : PC with Multisim 2001

THEORY :

CIRCUIT DIAGRAM :

LAB MANUAL/EDC

PROCEDURE : 1. Simulate the circuit on the multisim as shown in the circuit diagram.

2. Give the input as high and low and check the corresponding outputs.

OBSERVATION TABLE

CONCLUSION:-------------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------------------

QUESTIONS :

1. Write a short note on CMOS inverter.

2. Derive the expression for the power dissipated in CMOS inverter.

3. Explain dynamic characteristics of MOSFET inverter.

EXPERIMENT NO-09

Vi Vo

LAB MANUAL/EDC

AIM : MOSFET as a switch (CD 4007C)

OBJECTIVES: NMOS switch as Ohmic load

CMOS inverter

Realization of NAND using PMOS and NMOS

COMPONENTS: CD4007 CMOS dual complementary pairs, or discrete NMOS and PMOS.

APPARATUS:

THEORY:

CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and adaptable

MOSFET inverters used in chip design. They operate with very little power loss and at relatively high speed.

Furthermore, the CMOS inverter has good logic buffer characteristics, in that, its noise margins in both low

and high states are large.

This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter works. It

will cover input/output characteristics, MOSFET states at different input voltages, and power losses due to

electrical current.

A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a

supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal,

were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram). It

is important to notice that the CMOS does not contain any resistors, which makes it more power efficient

that a regular resistor-MOSFET inverter.As the voltage at the input of the CMOS device varies between 0

Instrument SpecificationsPower SupplyCROFunction GeneratorDMM

LAB MANUAL/EDC

and 5 volts, the state of the NMOS and PMOS varies accordingly. If we model each transistor as a simple

switch activated by VIN, the inverter’s operations can be seen very easily:

Transistor "switch model"

The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition on MOSFET State of MOSFET

NMOS Vgs<Vtn OFF

NMOS Vgs>Vtn ON

PMOS Vsg<Vtp OFF

PMOS Vsg>Vtp ON

When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high.

When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic low.

This model of the CMOS inverter helps to describe the inverter conceptually, but does not accurately

describe the voltage transfer characteristics to any extent. A more full description employs more calculations

and more device states.

LAB MANUAL/EDC

CIRCUIT DIAGRAM:

LAB MANUAL/EDC

PROCEDURE:

1) Make the connection as per the circuit diagram

2) Implement CMOS inverter.

3) Verify Truth table and measure current with and without ohmic load.

4) Realize NAND using PMOS and NMOS

5) Verify Truth table and measure current with and without ohmic load.

OBSEVATION TABLE: CMOS INVERTER (without Ohmic Load)

A

( Input)

Y

(Output)

Current I(mA)

LAB MANUAL/EDC

NAND using PMOS & NMOS(without Ohmic Load)

A

( Input)

B

( Input)

Y

(Output)

Current I(mA)

CONCLUSION:-------------------------------------------------------------------------------------------------------------

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-------------------------------------------------------------------------------------------------------------------

QUESTIONS:

1) Explain MOSFET as a switch

2) How NAND gate can be realized with PMOS and NMOS?

LAB MANUAL/EDC

EXPERIMENT NO. : 10

AIM : Design and implement a variable voltage regulator using three terminals IC

OBJECTIVES : 1. Design a variable voltage regulator using three terminals IC LM 317.

2. Implement a variable voltage regulator using three terminals IC LM 317.

COMPONENTS:Name Quantity

LM317

Resistors

Capacitors

Transformer

Diode

APPARATUS :

CIRCUIT DIAGRAM:

Instrument Specifications

DMM

LAB MANUAL/EDC

DESIGN :

Design of DC power supply:

1. Design of tansformer:

The transformer is used to couple the ac voltage from the source to rectifier. Design parameters for

transformer are as bellow

1. Vp (pri)=primary voltage of transformer i.e. input ac voltage

2. Vp (sec) =secondary voltage of transformer

3. Turns ratio of transformer (n) =Vp (sec)/Vp (pri)

Thus for 5v power supply,

Vp (sec) = ----V

Vp (pri) =230v, 50Hz

Thus n= ------ So as the required rectified dc constant voltage range is -----V so we have used

the transformer.

2. Design of rectifier: The rectifier can be either half wave or full wave. The rectifier converts the input

voltage to a pulsating dc voltage. In this design full wave bridge rectifier is used. In the bridge

rectifier design the diodes PIV voltages should be consider.

PIV=peak inverse voltage (specified in diode data sheet)

PIV=Vp (out) + 0.7 here Vp (out)=Vp (sec)-1.4v

So, PIV = -------

So according to data sheet of 1N4001 this diode is used for power supply, as PIV for this diode is

------V.

LAB MANUAL/EDC

3. Design for filter

The filter is simply a capacitor connected from the rectifier to ground. In design of filter following

points are considered.

a) Ripple factor:

The variation in capacitor voltage due to the charging and discharging is called as ripple. Generally ripple

is undesirable so smaller the value of ripple better will be the filtering action. The ripple factor is lower

by increasing value of filter capacitor or increasing load resistance. Thus we have selected value of filter

capacitor C=---------uF

Ripple factor(r) =Vr (pp) / Vdc

Vr (pp)=(1/f *R*C) Vp (rect) where Vp (rect)=Vp (sec)-1.4v and R= --------k

Thus Vr (pp)= --------V

Vdc = (1-1/2*f*R*C) Vp (rect)

= ----------

b) Surge current: At the instance when supply voltage is applied, this voltage is connected to bridge and

uncharged capacitor appears as short so this will induces an initial surge of current through forward bias

diodes. It is possible that the surge current could destroy the diodes for this reason the surge current limiting

diode is connected. The

minimum value of this resistance is given by

Rsurge= (Vp (sec)-1.4v)/Ifsm

Here Ifsm is maximum surge current value as given in data sheet of diode.

= --------Ω

LAB MANUAL/EDC

4. Design of LM317 regulator:

PROCEDURE : 1. Apply 230V , 50 Hz supply volatege.

2. Measure voltages at different stages like transformer secondary voltage , rectifier output

volage , filter output voltage.

3. Vary load and note down output current and voltage .

OBSERVATION TABLE:

CALCULATIONS:

LAB MANUAL/EDC

CONCLUSION

:------------------------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------

QUESTIONS :

1. Draw and explain Block Diagram of adjustable three terminal positive and negative regulators(317,

337).

2. Explain low dropout voltage regulators.

3. What is current Boosting?

4. Compare Linear power supply and SMPS.

LAB MANUAL/EDC

EXPERIMENT NO-11

AIM : Complementary symmetry push pull amplifier

OBJECTIVE : 1.To Verify dc condition.

2. To understand class of operation

3. To calculate the percentage conversation efficiency

4. To calculate power dissipation of both transistors

5. To observe and elimination of crossover distortion.

APPARATUS :

CIRCUIT DIAGRAM:

Sr. No.

Description Specifications

1. DC Power supply

2. Signal Generator

3. Dual channel CRO

LAB MANUAL/EDC

PROCEDURE :

1. 1. Make the connection as per the circuit diagram.

2. Apply sinusoidal input from the signal generator & try to get maximum undistorted output voltage

by adjusting the i/p signal level & the biasing.

3. Observe input and output waveform with cross over distortion & removing cross over distortion.

4. Measure the o/p voltage on CRO and calculate the output power.

5. Calculate Percentage efficiency.

OBSERVATION TABLE:

For Class B complementary amplifier1) DC Collector Voltage(VCC): ------------------------------------

2) Quiescent Collector current(IcQ): -----------------------------

3) Vi(peak –peak):--------------------------------------------

4) Vo(peak –peak):-------------------------------------------

For Class AB complementary amplifier

1) DC Collector Voltage(VCC): ------------------------------------

2) Quiescent bias current (IcQ):-------------------------------

LAB MANUAL/EDC

3) Vi(peak –peak):--------------------------------------------

4) Vo(peak –peak):-------------------------------------------

FORMULA :

PIN=IAVG*VCC I AVG=VAVG

R 5 VAVG=Vmπ P OUT =

(V O(rms ))R L

%η=PacPdc

∗100

CALCULATION:

RESULT :

Class B Amplifier Class A B Amplifier

PAC

PDC

% Efficiency

LAB MANUAL/EDC

CONCLUSIO

N:-------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------

QUESTIONS: 1.Compare class A, B, AB, C, D Power amplifiers. 2. Explain cross-over distortion in complementary symmetry amplifier.