VLSI DESIGN & EMBEDDED SYSTEMS 2017

TOOL FLOW

Steps of Execution

1. To Open the Project NavigatorRoot’s Home – Right click – Open Terminal-> cd.. ( press enter)-> csh (press enter)-> source .cshrc (press enter)-> dmgr_ic( press enter) ---------- Project Navigator Window

2. To Create Project

Go to File - >New- >Project

Enter Project Path

Path to Library i.e browse for generic13 (in PDK)

Configuration - > generic13

Click ok

1 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

2.1 To Add Standard Libraries

Click on “Add standard Libraries” then Press Ok

After Adding the Libraries

2 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

3. To create our own libraryProject Hierarchy->Right Click->New Library (Give library name for ex: CS and press ok)

4. To Create New Schematic

Right Click on new library->New Schematic -> Cell name -> Ok(Schematic name should be schematic and cell name can be changed for ex: CS1, by default it takes the name as of library name)

3 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

New Schematic Window Opens

4.2 To Draw a Schematic Circuit

4.2.1 Add instance (or) press i to get file browser window (to get the components) generic13->symbols- pmos ,nmos, resistance/capacitance

Generic lib-> vdd, vss, ground etc.

Source lib->dc/ac/pulse voltage/current source /Voltage source etc.

press ‘W’ to get wires for connection/ select the wire from the tool bar

4 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

After the circuit is drawn add ports from the Tool bar4.3 Schematic Diagram with ports

4.4 Check for the correctness of the schematic

Click on check & save

5. To Create Symbol

Add->Generate Symbol->Choose Shape (preferred square)

5 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

5.1 To Assign Port pins

Click on Customize Pin list->ok

5.2 Generated Symbol

6 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

6. To Create New Test Schematic

In the Project Navigator Window->right click on your library->new->schematic

6.1 Add Symbol

Add - > Instance - > Choose Symbol

6.2 To Draw Test Schematic Circuit

7 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Add the Components

Press i/Instance->source lib-> dc/ac/pulse voltage/current source etc generic lib-vdd, vss, ground etc

Add port out pin

For changing name of port

Right click on port->edit object->net name (change) ->ok

Final Test Schematic Circuit

8 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Click on Check &Save

Then After Enter into the Simulation Mode

9 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Simulation Steps

1. New Design ConfigurationNew Configuration -> Give Configuration name ( user defined) ->Ok ->Ok (Eldo should be selected)

2. Choose “Setup Environment”

Simulator->enable ez wave

10 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

viewer->Select “Start EZwave Automatically”->ok

3. Click on Setup Simulation

Analysis->deselect op DC Analysis

Select dc analysis, choose sweep type as source and select sine ac source in the test circuit

Give start, stop and step size

11 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

AC Analysis

Select ac analysis gives start frequency, stop frequency and pts./decode value

Transient AnalysisSelect transient analysis, Give start time and stop time

12 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Setup Simulation->Libraries->Typical

Deselect “$Generic/models/include_all”

13 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Setup Simulation ->Forces->From Schematic>Press ctrl and select input and output

Setup Simulation->Output->Choose Inputs and Outputs ->In Task-Select Plot->Add->Apply

14 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Save and Run

To see the Simulation Results- DC , AC and Transient Analysis (waveforms)

Run

Measurement Settings

Tool-> Measurement Tool-> Select Vin and Vout from the waveforms and then click on add-> select peak to peak and then click on apply

Add

15 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Layout Steps

1. Create New LayoutSelect Schematic->Right Click->New->Layout Give Layout Name

Click on “OK” to launch Layout Editor and press Ok

16 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

2. To get the Schematic Drivers

Setup-> Toolbars->SDL Toolbar

SDL Toolbar

To get the component Description

17 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

3. To Draw Layout Pick and Place Component from SDL Toolbar

Pick and Place Ports from SDL Toolbar

18 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Add Device->$gb_p->psub,nwell for nmos and pmos Respectively

Route for connectivity using metal layer for drain and source ,polysilicon for gate Add->Text on Ports->M1->OK

19 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

4. Save the Layout

5. DRC CheckTools->Calibre DRC->Run DRC->Ok

20 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

6. LVS CheckTools->Calibre LVS->Run LVS-> Ok

Tick Mark and Smiley Indicates No LVS Errors

21 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

7. PEX Report Check

Tools->Calibre PEX-> Input->Browse “*.src.net”

Inputs->Netlist->Enable Export from Schematic

Outputs-> Format-DSPF

22 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Run PEX

After Running the PEX, again check for LVS

23 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 1

Common Source amplifier with resistive load

Procedure:1. Design a schematic circuit in pyxis schematic window

2. Generate a Symbol of the schematic circuit

3. Draw a test Schematic Circuit using generated symbol

4. Verify the simulation Results

5. Calculate the Gain using the formulas given in calculation section

6. Draw a Layout in pyxis layout window

7. Check for DRC, LVS and PEX

Circuit Diagram:

Calculations:

Gain calculation based on Waveform

Gain Vout Vin

Gain Calculation based on Parameters

Av g m r 0 || RD Where, gm - Transconductance

r0 - Internal ResistanceRD- Load resistance

24 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Schematic Circuit

Symbol

25 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Test Schematic Circuit

Layout

26 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Results

Transient Analysis

DC Analysis

LVS Report

27 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 2

Design a Common Source amplifier with Active load using

Current mirrorProcedure:1. Design a schematic circuit in pyxis schematic window

2. Generate a Symbol of the schematic circuit

3. Draw a test Schematic Circuit using generated symbol

4. Verify the simulation Results

5. Draw a Layout in pyxis layout window

6. Check for DRC, LVS and PEX

Circuit Diagram:

Calculations:

Gain calculation based on Waveform

Gain Vout Vin

Gain Calculation based on Parameters

Av g m r 01 || r02 Where, gm - Transconductance

r01 - Internal Resistance of MOSFET Q1r02 - Internal Resistance of MOSFET Q2

28 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Schematic Circuit

Symbol

29 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Test Schematic Circuit

30 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Layout

31 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Results

Transient Analysis

DC Analysis

32 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

LVS Report

33 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 3

Common drain amplifier with Active load using Current mirror

Procedure:1. Design a schematic circuit in pyxis schematic window

2. Generate a Symbol of the schematic circuit

3. Draw a test Schematic Circuit using generated symbol

4. Verify the simulation Results

5. Draw a Layout in pyxis layout window

6. Check for DRC, LVS and PEX

Circuit Diagram:

Calculations:

Gain calculation based on Waveform

Gain Vout Vin

Gain Calculation based on Parameters

Av g m r 0 || RD Where, gm - Transconductance

r0 - Internal ResistanceRd- Load resistance

Schematic Circuit

34 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Symbol

35 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Test Schematic Circuit

Layout

36 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

ResultsTransient Analysis

37 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

DC Analysis

38 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 3

Design a Differential Amplifier with Active load using Current

mirrorProcedure:1. Design a schematic circuit in pyxis schematic window

2. Generate a Symbol of the schematic circuit

3. Draw a test Schematic Circuit using generated symbol

4. Verify the simulation Results

5. Merge the Transistors (similar Characteristics) Using MOS Sharing.

6. Draw a Layout in pyxis layout window

7. Check for DRC, LVS and PEX

Circuit Diagram:

Differential Amplifier with active load

Calculations:

Gain calculation based on Waveform

39 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Gain Vout Vin

Gain Calculation based on Parameters

Av g m r 0 || RD Where, gm - Transconductance

r0 - Internal ResistanceRd- Load resistance

Schematic Circuit

Symbol

40 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Test Schematic Circuit

For more number of similar transistors , it can be merged using mos sharing options .

41 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Select SDL tool

In setup SDL tool

select MOS sharing

setup

share all

ok

Layout

42 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Results

Transient Analysis

DC Analysis43 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

LVS Report

44 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 4

Design an Operational Amplifier with Active load using Current

mirror Schematic Circuit

Symbol

Test Schematic Circuit

Simulation Results

Layout

45 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 5

4-bit R-2R Ladder DAC Schematic Circuit

Symbol

Test Schematic Circuit

Simulation Results

Layout

46 Dept. of EIE, SIT, Tumakuru

VLSI DESIGN & EMBEDDED SYSTEMS 2017

Experiment - 5

4-bit Successive Approximation ADCSchematic Circuit

Symbol

Test Schematic Circuit

Simulation Results

Layout

47 Dept. of EIE, SIT, Tumakuru