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FreeHDL Compiler Control Data Flow

Graph and its application in waveform

compression

Dr.-Ing. Edwin Naroska

Said Mchaalia

7th August 2002

1 Intention of this document

In this document, we try to present an idea of using Control Data

Flow Graph (CDFG) to improve waveform compression.

A waveform file is a VCD (Value Change Dump) file, which is divided

in two parts: header that contains general information, which are

version, date,.. and kernel, which contains signal values belong to

each simulation step and simulation time.

Figure 1 describes a VCD file. Notice that each parameter is coded

with an ASCII code composed of 1 to 4 characters depending on

the number of parameters inside considered VHDL model. For each

VHDL model, the simulation time is written before the parameter val-

ues. For example: #0 and #100 represent the simulation times 10

and 100 us. The character b preceded parameter value describesthat this parameter value is a binary format. Thereby all parameter

values will be transformed to a binary format before that they will be

written in the VCD file.

To compress a VCD file, many techniques are developed. The basic

idea of these techniques is inspired from the Lempel-Ziv and the oth-

ers algorithms for data compression [4]. Mainly, five algorithms that

are Time-Value Separation, Time Compression Technique, Value

Compression Technique, Strength Reduction and Cross Signal Strength

Reduction (see [1] and [2]) are developed to allow a suitable VCD file

compression.

The object of this work is to get out an idea of using CDFG for devel-

oping a new waveform compression algorithm. In following sections,

we will describe this idea and present its features.


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Figure 1: VCD File

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Figure 2: VHDL model 1

Figure 3: CDFG of VHDL model 1

whether the signal a an/or the signal c change values or not. Due

to this relationship between signals and the principles of the VHDL

language, we do not need to store the d signal value.

So, a dependency knowledge a priori checks whether to store a sig-

nal value or not.

Indeed, in figure 2 we can predicate the output signal value through-

out the knowledge of the operand signal values. The CDFG of theVHDL model described in figure 2 is presented in figure 3. We see

that the CDFG shows the dependencies between all considered sig-

nals in this process.

So, we do not need to store the d and c signal values due to the de-

pendencies between those signals and the signals a and b. The idea

is to search a manner in which we must store information describ-

ing the dependencies between those signals. This can be solved by

storing these operations:

(1)

and

(2)

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that attach each set of signals to the other. The first operation (equa-

tion (1)) describes the relationship between the signals a, b and c

and the second one (equation (2)) describes the relationship be-

tween the signals a, c and d. Notice that the storage of these equa-

tions should be done just once a time for each waveform compres-

sion process.

Let see, what will happen when we consider a VHDL model, which

depends on clock signal. Figure 4 shows the previous example in

the case where the process P depends on a clock signal clk.

We see that in the VHDL model of figure 4, the considered process

depends whether the clock signal clk changes value or not to assign

signal values to c and d. Although, signals c and d will change value

with a cycle delay of clock signal compared to signals a and b. Fig-

ure 5 describes the signal assignment structures for VHDL language

in the case of ideal electrical circuits without any component delays.

We notice that there is a clock cycle delay between the two assign-

ments and the a and b signal values. I.e. that the signal assignment

will be achieved just after a delay of clock signal cycle.

In order to make synthesizable models and due to the VHDL lan-

guage structure in the signal assignment, we notice that the previousrelationship between c, a and b, and d, c and a will not be valid in

the case of this VHDL model that depends on clock signal. There-

fore, we must define new relationships between these signals, which

depend on the clock signal clk.

Figure 6 represents the CDFG of the VHDL model shown in figure 4.

Notice that this graphical representation describes the relationships

between all signals in this VHDL model. Thereby, the incoming data

edges a and b of the XOR node come from the Read Signal node,

which represents the source of out-coming data edges, however the

out-coming data edge c is an incoming edge of the Write Signal

node, which represents the source of incoming data edges. BetweenRead Signal node and Write Signal node there is just one clock

signal cycle delay. After a clock signal cycle, the value of signal c

will be transfered to Read Signal node. On the other hand, the

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Figure 5: VHDL signal assignment procedure

incoming data edges a and c of the AND node are coming from

Read Signal node. This means that there is a clock signal cycle

delay between these signals and the out-coming data edge d of this

node. Notice that the dependency of these nodes on the clock signal

is characterized with control edges true and false coming from the

Select node that is activated by the clock event node.

Let us consider the new relation as follows:

(3)

where a logical function, which is defined as follows:

(4)

as the first relation between signals c, a and b.

(5)

where

a logical function, which is defined as follows:

(6)

as the second relation between signal d, a and c.

Where n is the nth clock signal (clk) cycle.

4.1.2 Process dependency schedules

In this section, we will try to give an idea how the CDFG can solve

the dependencies between processes inside the same VHDL model

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Figure 6: CDFG of VHDL Model 2

and how which information will be used in the waveform compression

techniques.

Let us look at the example of figure 7, we see that the three pro-

cesses

,

, and

are depended each of the other. Based on

the CDFG of each process and on the knowledge that all processes

inside the same VHDL model have the same Read Signal and

Write Signal nodes, we can involve some relationships between

signals inside different processes to make a suitable optimization of

the waveform compression.

Figure 8 describes the CDFG of the VHDL model represented in

figure 7. We see that, the CDFGs allow us to get information about

the dependencies between signals inside theses processes and so

to achieve the needed optimization, which is the storage of signal a

and all relationships between considered signals such as:

(7)

where a logical function, which is defined as follows:

(8)

(9)

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where

a logical function, which is defined as follows:

(10)

(11)

Where a logical function, which is defined as follows:

(12)

Above, we presented the case when the processes depend on sig-

nals. Let us look, what will happen when there are processes, which

depend on clock signal inside a considered model.

The simple case of processes that depend on clock signal is

the case when all processes have the same clock signal and

are activated on the same clock signal cycle. This case repre-

sents a composition of the process dependencies and depen-

dency on clock signal. So, the relationship will described as

followed:

(13)

Where

represents a mathematical multi-variable func-

tion.

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The more complex case is the case where each process has

its own clock signal. In this case, we must define a relation-

ship between all clock signals, and try to write the other clocksignals function of the first one for example. If we suppose

for example that the clock signal

is slower k times than

the clock signal

, and the clock signal

is p times faster

than signal clock

, we can write the following relationships

between the distinguished clock signals:

(14)

(15)

The relationships between signals inside theses processes will

be defined as follows:

(16)

Where

is a function, which is defined as follows:

(17)

where

is the real sets and

is the natural number sets.

(18)

(19)

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Figure 9 represents a VHDL model, where considered processes

inside this model are depended on different clock signals.

The CDFG of the VHDL model described in figure 9 is shown in fig-

ure 10. Notice that in the VHDL model of figure 9, the three clocksignals

,

and

are distinct. So, to get a relationship be-

tween signals a, b, c and d, we must define relations between the

clock signals.

Suppose for example that:

(20)

and

(21)

To involve the relations between signals that are defined previously,

we can consider these equations:

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(22)

Where n is the nth clock signal

cycle.

(23)

Where k is the kth clock signal

cycle.

(24)

Where m is the mth clock signal

cycle.

Indeed, we can use these equations to minimize data storage. Thereby,

we can just store the signal value a and these relations between dif-

ferent clock signals

,

and

, and signals a, b, c and d.

Notice that these relations will be stored just only once a time dura-

tion the VHDL model simulation.

4.2 CDFG and Waveform Decompression

In this section, we will describe how the CDFG will be used in the

complex cases to improve the waveform compression techniques.

4.2.1 Compromise between decompression and signal depen-

dencies

In the previous section, we treated the case of signal dependencies

and the involved solution based on the CDFG research. In section

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4.1.1, we developed an algorithm that searches whether a signal will

be stored or not. Indeed, the storage of signal values needs a knowl-

edge a priori of the signal dependencies. Thereby, a signal value will

be stored only when this signal is independent from all other sig-

nals defined inside a given VHDL model. On the other hand, section

4.1.1 involves that only the relationship in their mathematical forms

between signals will be stored, because this will be done just once

a time during a simulation process of waveform compression. Al-

though, it is hard to achieve this task during the decompression pro-cess. Thereby, we do not know exactly the complexity of considered

mathematical functions, which link the signals to each other. In the

most case of complex VHDL models, we have mostly very complex

mathematical functions that belong a set of signals to a defined sig-

nal. This will make the process of decompression very complex and

it will take a great schedule time.

To solve this problem, we try to find an optimized solution for the

waveform compression techniques based on the signal dependen-

cies.

This solution is described as follows:

in the case of a signal that depends of a set of signals: find an

algorithm that searches to store all needed signals based on

operation numbers that identify the signal values. Thereby, let

consider the signal

that depends on a set of signals. This

signal will be written as follows:

(25)

where

are independent or primery signals and

are signals that depend of each other and the other signals.

For example, let consider the following signal dependencies:

(26)

(27)

(28)

(29)

In section 4.1.1, we will just store the signals that do not de-

pend of any other signal. For example

. There-

fore, the decompression process complexity will depend on the

complexity of the functions

. Notice that these func-tions can be as complex as possible and so the decompression

task will be so complex. To solve this problem, we can precede

as follows:

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Figure 11: Complexity of dependency functions function of signal

numbers

first, store all independent signals.

secondly, in the case of dependent signals: see whether

the dependency function

is complex or not. If it is simple then do not store the

corresponding dependent signal

. Figure 11 represents

the graph of the complexity of dependency functions.

In figure 11, we see that the complexity

of dependency

function

depends on the number of signals j that are con-

tained in this function. If this number is higher than the com-

plexity is lower and vice versa. This means that, in this case

of dependent signals, we must search the signal number to be

stored in order to reduce the complexity of the decompression

process. In the figure 11, we see that for a given dependency

functions that depend on

signal, we can find the suitable

signal number

such as

with which we can get an

optimized complexity of all considered dependency functions.

So, our object is to develop an algorithm that returns the signalnumber , which their values will be stored to allow a simple

restoration of the other signals and to identify the signals that

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must be stored.

Thirdly, optimize the compromise between the storage space of

signal values and the complexity of schedule time needed for

the decompression process. As, we describe above, we must

find the signal number

that allows a suitable complexity of all

considered dependency functions inside a given VHDL model.

Although the research of this number is so complex and in the

most time we cannot find just a number but an interval. In this

case we must resolve the solution of finding this signal number based on other information, which is the reduction of needed

storage space of signal values. Throughout these information,

we must find a signal number inside the considered interval

and which gives a less need of storage space of signal values.

Finally, store all needed signal and required dependency func-

tions.

Problem formulation: The problem we are going to consider may

be formulated as follows:

For a given signal

, which is written in the form:

(30)

minimize the dependency function complexity:

, which should

be written in the following form:

(31)

where , is the number maximal of signals, a

function to define, and:

is defined as follows:

(32)

is the weight of operation i contained inside the dependency

function

. It is defined as follows:

(33)

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Let consider the signal sets

as information model,

which will be identified. It looks like that our VHDL model is a source

of signals, which will be produced each simulation time

with distin-

guished probabilities

. These signals are dependent one of each

other and they are correlated between them. Where each signal

represents an information to be stored or not. Thereby, our problem

will be considered as a Lossless Data Compression Problem that

searches to encode each signal

with a number of bits and then

optimizes the number of the signal values, which must be stored forfurther use and that allows a suitable restoration of the all signals

during the decompression process.

On the other hand, for a given signal sets

, we con-

sider the probability of a signal

,

to be appear in the

VCD file during a simulation process and the probability

as the probability of the dependency between signals

and

. The probability

of signal

. is defined as follows:

(34)

where

is the occurrence frequency of the signal

and

is

the storage space needed for storing the signal

. It means, when

a signal

appears just once a time during simulation process,

will have the value one and so on. Although, the probability

of dependency between the signals

and

(or the conditional

probability) is defined as follows:

(35)

where

is the number of times in which the

belongs to signal

.

I.e. the number of times that the signal

is defined as a parameter

of function

.

The problem we are dealing with can be defined as an optimization

problem. So, mathematically, this problem will be written as follows:

(36)

From this optimization problem, we can say that the needed storage

space and the dependency function complexity are inversely (con-

versely) proportional. So, we can define a new space composed of

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the complexity and the probability as shown in figure 12. This allows

us to consider the function to minimize as follows:

(37)

where

is the distance between the points

and

:

(38)

where and are constants for scaling, and the distance

is

defined as follows:

(39)

The

is chosen with the manner that

is composed of independent signals only. This means that

all

are independent.

So, the problem we are dealing with can be written as follows:

(40)

This problem can be transformed to a quadratic optimization problem

in the following form:

...

...

(41)

where :

...

. . . ...

...

. . . ...

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the matrix of quadratic optimization. This matrix is

di-

mension. I.e

. We can demonstrate that the

matrix

is symmetric and positive definite, which means

and

.

...

...

, the vector of quadratic optimization.

The length of this vector is

.

...

...

is a constant vector. The length of this vector

is

.

The solution of considered problem consists to find a set of signals

where

, which satisfy the condition

below. Our object is to define the convenient signal sets with which

we have an optimal storage space that associates an optimal com-

plexity.

So, our new problem will be formulate as follows:

(42)

that succeeds:

(43)

To resolve this problem, we try to consider the optimal signal set

as

, which has a length (number of signals inside)

such as

where

is the total signal number inside the considered

VCD file.

To search

, we need to consider a discrete probability problem,

which is defined as follows:

for each

we have a chance probability to get

a solution of our

problem. This solution can be written

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Figure 12: Considered Space

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Figure 13: Variation of the chance of getting optimal solution

as follows:

. Let associate to this solution a

chance probability

that satisfies

.

we know that for our

we have the best chance to get the

optimal solution

of our

solution. So,

we have the following condition to be verified :

. The Figure 13 shows the variation of the

chance to get an optimal solution function of the considered

signal sets.

We can assume that the variation of the chance of getting an optimal

solution is a distribution. So, we can define this distribution, which

will identify the relationship between the chance probability to get an

optimal solution an the signal sets. This distribution can be writtenas follows:

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(44)

where , and are constants.

We note that the peak of the chance is found at the point

.

Although, we cannot demonstrate that the considered distribution or

density is not symmetric around

.If we assume that this density is symmetric around

, we can

demonstrate that it will be written as follows:

(45)

Proof: to prove the equation above, just consider the case of the

p-variate normal distribution for multivariate with [5].

So, we can use this equation as a constraint for the optimization

problem defined in equation (41). Always, we can fix the chance to

obtain an optimal solution of considered optimization problem, and

than search the corresponding signal sets which succeeds consid-

ered chance probability.

For example is we would like that the chance of getting an opti-

mal solution must be greater than

, we can consider the following

quadratic optimization problem:

(46)

where

represents the length of the vector

...

that must

be identified.

4.2.2 One signal restoration

In this section we try to treat the case of restoration of one signal from

a signal lists that have been compressed. We know that consideredsignal is combination of a signal sets. So, to restore this signal we

need to calculate the function link this signal to all other signals. In-

deed the complexity of the restoration depends on the calculation of

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these signals. This can be so complex so possible. To reduce this

complexity, we need to reduce the complexities of the calculation of

all signal that are dependent of each other. This means that the

restoration depends on the operation number needed to calculate all

required signals.

(47)

where

(48)

So, to calculate

we need first to calculate

. So, the com-

plexity of the function

, will be calculated based on the function

complexities

:

(49)

where

represents the weight of the operation belong to signal

This problem can be transformed to an optimization problem, which

is

(50)

4.2.3 Data base optimization

In this section we try to give an overview about the case where the

same signal depends on itself for each clock cycle and/or on signal,

which depends on clock cycle. Although the simplicity of the sim-

ulation of the relationship between considered signal and the otherassociated signal, we have to solve the problem of storage space

optimization.

Let look at the example of figure 14. We see that the signal a de-

pends on the clock signal. It changes value for each clock signal

cycle.

In the example of figure 14, we see that the signal a will change

value each cock signal cycle. So, if we like to store the signal a,

we will need more storage space. Mathematically, we can write the

following relation between the clock signal clk and the signal a

(51)

where n is the nth clock signal cycle.

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Figure 14: VHD model 5

Notice that this equation allows us to restore the signal a at the clock

signal cycle

base on the value of this signal at the clock signal

cycle

. So, we can just store the value of this signal at the first

clock signal cycle and then we can calculate the value of considered

signal recursively. Although the problem is that this calculation of the

value of signal a at the clock signal cycle is so complex and need

a great schedule time.

To solve this compromise between these problems, we need to find a

solution that reduces the schedule time needed for the restore of the

signal a at the clock signal cycle , when is so great so possibleand the storage space needed for the storage of signal a each clock

signal cycle.

Problem formulation: The problem we are going to consider may

be formulated as follows:

(52)

find

(53)

where

is the storage space needed to store a signal value.

This can be transformed as follows:

(54)

such as

(55)

For each clock signal cycle

, we will try to find an integer

, that

allows to store the signal value

that minimize the time schedule

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needed for the restoration of signal value

. Arbitrary, we can

choose as follows:

(56)

Schedule time analyses: In this paragraph, we prove our choice

of the value of

. Let consider the case, when all values of the signala will be stored. So, we need

storage space to

store all values of signal a. However, if we store just the value of a

at the clock signal cycle

, we will need

schedule time

to restore the value of signal a at the clock signal cycle . Indeed,

if we apply the developed algorithm, we need just

schedule time to restore the a signal value at the clock signal cycle

and just storage space. So, we have to reduce the

number of schedule time of and the number of storage space of

too.

4.3 Waveform Compression Software Design

In this section an overview of the developed software design is pre-

sented. Figure 15 represents the general aspect of this software.

FreeHDL Simulator: its task is to simulate a given VHDL design

in order to create the VCD and DDB files for further use.

CDFG Simulator: the CDFG simulator allows to create the

Control Data Flow Graph of considered VHDL model and write

it in a specific file.

Waveform Compressor: its task is the compression of the VCD

file based on the CDFG of considered model. The obtained file

will be stored for further use.

Waveform Decompressor: realizes the decompression of com-

pressed VCD file to view it.

Waveform viewer: allows the viewing of the decompressed

VCD file in order to get out the verification results of consid-

ered VDHL design.

Figure 16 represents the software module designs in detail.

Waveform Compressor: the waveform Compressor is com-

posed of two basic modules:

Waveform Compression module: this module interests the

compression techniques. Three compression modules

are employed:

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Figure 15: Software Design

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Header file compression module: as it is described

above, the compression of the VCD header file is

done independently of the Control Data Flow Graph.

Simulation Time Compression module: this module

interests the compression of the signal ids through-

out the knowledge of considered clock cycle and sig-

nal events. It returns the signal ids, which must be

compressed and stored.

Parameter value compression module: this module

realizes the compression of considered parameter val-

ues inside the given VCD file based on the informa-

tion returned from Dependency Scheduler and VCD

file. It returns the signal values, which must be com-

pressed and stored.

Dependency Scheduler module: this module treats the

dependency of signals and processes based on the de-

veloped CDFG of the VHDL design. This module has to

control whether a given signal Id and value will be com-

pressed and stored or not. So, it controls the ParameterValue Compression and the Simulation Time Compres-

sion modules. Thereby, it gives the needed information to

the Simulation Time module about which signal Ids that

must be compressed and these to the Parameter Value

Compression about which signal and variable values must

be compressed and stored. On the other hand, it returns

the dependency between signals and variables in math-

ematic forms to the Waveform Compression module to

be stored. Its input comes from the CDFG Scanner and

Parser.

CDFG Scanner and Parser module: this module translates theCDFG, which is written in a given file to a data base inside the

memory for further need. Its inputs are coming from the DDB

and CDFG files.

Viewer: the viewer has to get out the verification results of con-

sidered VHDL model. Basically it consists of two modules :

Waveform Decompressor: it is composed of four mod-

ules, which are needed for the decompression of com-

pressed VCD file.

Header File Decompression module: this module is

used to decompress the VCD header file.

Simulation Time Decompression module: this mod-

ule allows the decompression of the Simulation Time

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based on the information returned from the compressed

VCD file and the Dependency Simulator.

Parameter Value Decompression module: this mod-

ule decompresses all parameter values based on the

information stored in the compressed VCD file and

those returned from the Dependency simulator.

Dependency Simulator module: this module allows to

simulate the stored dependencies between parame-ters and returns either the parameter value or the the

Simulation Time.

waveform viewer: simulates decompressed VCD file to

get out the Verification results of VHDL model.

5 Time Schedule

In this section we presents the needed time to achieve each module

of this software.

VCD header file compression: already done.

Simulation time compression: one month.

Parameter value compression: one month.

Dependency scheduler: two months.

CDFG scanner and parser: already done.

VCD header file decompression: one month.

Simulation time decompression: two months.

Dependency simulator: three months.

Parameter value decompression: two months.

Waveform viewer: using Dinotrace. Already done.

6 Conclusion

In this document, we presented an idea of using CDFG to improve

the developed waveform compression technique. Two cases for us-

ing CDFG in the waveform compression are developed: simple case,

which interests the signal and process dependencies, and complexcase that interests the other VHDL statements. We can conclude

that the CDFG advantages are to allow a rapid interpretation of the

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Figure 16: Software Module Designs

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information inside a VHDL model throughout a graphical represen-

tation.

7 Reference

[1] E. Naroska, A Novel Approach for Digital Waveform Compres-

sion.

[2] E. Naroska, Waveform Compression Technique.

[3] E. Naroska and S. Mchaalia, Control Data Flow Graph for Free-

HDL compiler.

[4] J. Ziv and A. Lempel,A Universal Algorithm for Sequential Data

Compression, IEEE Transaction on Information Theory, Vol. IT-23,

No.03, May 1997. [5] The multivariate Normal Distribution, basic

course.

List of Figures

Figure 1 : VCD File.

Figure 2 : VHDL Model 1.

Figure 3 : CDFG of VHDL Model 1.


Figure 5: VHDL Signal Assignment procedure.



Figure 8 : CDFG of VHDL Model3.



Figure 15 : Software Design.

Figure 16 : Software Module Designs.

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