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IMSE

IMM

IMB

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STAFF RECENT RESULTS

PROJECTS

Hardware realization of embedded systems in smart environments

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Video de-interlacing Connected

Component Labeling (CCL)

Video Processing FPGA IP core library

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Interlaced Scanning

Progressive Scanning Video Transmission

(Interlaced scanning)

CRT TVs

LCD Displays

De-interlacing

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De-interlacing

•  De-interlacing algorithms provide non-transmitted lines during the transmission

•  Numerous devices at the receiver side require a progressive scanning

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More info:

1.  Fuzzy Logic-Based Algorithms for Video De-interlacing. P. Brox, I. Baturone, S. Sánchez-Solano, Springer, 2010

2.  Soft computing techniques for video de-interlacing . P. Brox, I. Baturone, S. Sánchez-Solano, IEEE Journal of Selected Topics in Signal Processing, vol. 5, no. 2, pp. 285-296, 2011

Fuzzy logic systems

•  Reasoning: they emulate how the human brain works

•  Uncertainties: they can deal with vague, imprecise or uncertain information

•  To deal with important features: motion, edges, or temporal pattern repetitions

Application in video

de-interlacing?

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Processor

Drivers I/O

SW

Video De-interlacing

I/O VFBC

HW

Processor: Soft-core from Xilinx

Video de-interlacing: Hardware IP module

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Design of fuzzy logic systems

Design & Verification in video sequences

Implementation HW IP

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Virtex 4 Development Board

-  Virtex 4 – 200,000 logic cells"-  3456 Kb BRAM + 64 MB DDR SDRAM"

WASC 2013 June 3-4, 2013

More info:

1.  Fuzzy Logic-Based Embedded System for Video De-interlacing. P. Brox, I. Baturone, S. Sánchez-Solano, Applied Soft Computing , 2013 (in press)

http://dx.doi.org/10.1016/j.asoc.2013.01.015

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30 fps @ VGA resolution"

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Linear Filters

Non-linear Filters

Morphological Operators

Control Logic

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Original image Enhancement Edge substraction

Median 3x3 Original image

More info:

1.  Librería de módulos IP para la implementación sobre FPGA de algoritmos de procesado de imágenes. L. M. Garcés, P. Brox, S. Sánchez-Solano, A. Cabrera. Conference Paper - XI Jornadas de Computación Reconfigurable y Aplicaciones JCRA 2011 (In Spanish)

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•  Why CCL Algorithms?

- Fundamental algorithms in intermediate level image processing

•  What is a CCL algorithm? - Goal: Assignation of a unique label to each set of connected pixels

- Exploit temporal paralelism and use vertical blanking periods

•  Implementation strategy:

Original image Binary image Image afer CCL

- CCL Algorithm is implemented as a HW IP module to accelerate its implementation

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VG is composed by ≅3-9% of the active lines

FRAME

2 Picture Improvement

3 CCL Algorithm

1 Picture adquisition (720X480)

4 Display

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More info: 1. Real-Time FPGA Connected Component Labeling System. E. Calvo, A. Cabrera, P. Brox, S. Sánchez Solano,.Conference Paper - IEEE Int. Conf. on Electronics, Circuits, and Systems ICECS 2012

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