5
JOURNAL OF MATERIALS SCIENCE: MATERIALS IN ELECTRONICS 12 (2001) 93–97 Warpage behavior of LOC-TSOP Memory Package MINJIN KO, DONGSUK SHIN, MYUNGSUN MOON, INHEE LIM, YONGJOON PARK LG Chemical Ltd./Research Park, Advanced Materials Research Institute, Taejon, Korea E-mail: [email protected] This paper describes a warpage study on LOC-TSOP memory devices. The main objectives of this study are to evaluate the impacts of epoxy mold compounds on package warpage with different sized dies. It was found that the balance of the bending between the edge side region and the die attach region controls the package warpage. The package tends to bend convex upwards in the edge side region and concave downwards in the die attach region. The various mold compounds were prepared to study the affect on the components, particularly the resin and the filler. It has been shown that the optimum mold compound can be changed according to the inner structure of the LOC-TSOP. The effect of post-mold cure on package warpage was also examined based on the cure rate. # 2001 Kluwer Academic Publishers 1. Introduction Due to the ratio of a chip size to the package size and low pin count of many DRAM designs, lead on chip (LOC) is a packaging technique that has been used over the last 10 years for memory products [1, 2]. The technique consists of attaching leadframe fingers directly on the chip surface via a double-sided adhesive tape, thus the chip density can be increased up to 90% compared to 65% in conventional packages. Other advantages in the LOC design include faster current speed associated with shorter Au wires resulting from an array of pads scattered on the center of the chips rather than periphery bonds. Plastic packaging in the electronic industry has been extensively used in the past. One of the reasons is its lower cost compared to ceramic packaging. Epoxy resins are most often used in plastic packages due to their low melt viscosity that facilitates injection and minimizes leadframe and gold wire deformation. It is known that the internal stress in epoxy resins cured at high temperature is produced by the volumetric shrinkage during the cooling process from the cure temperature to room temperature. The internal stress can reduce adhesion strength and occasionally induces die cracking if a tensile stress is built up in the die, particularly in thin packages. Along with internal stress, excess bending of the package can cause yield loss in many downstream assembly processes, such as the trim and form since lead coplanarity is necessary for device testing and for surface mount assembly [3]. Residual warpage is often used by package manufacturers as a check on the quality of the molding process [4]. As the package increases and the chip decreases in size, maintaining package planarity becomes more difficult particularly in an asymmetric structure. Since the degree of package warpage depends on the package design, materials selection, and assembly process, several methods can be used to reduce package warpage. Among these approaches, optimization of the mold compound is the least costly and most manufacturable solution although the package design would be a more effective way to minimize package warpage. It is important to know how sensitive the warpage of a particular package is to change in material properties. To date, most studies have centered on the geometric modification of package design and finite element analysis [5]. This paper discusses a study evaluating the effect of mold compounds on the package warpage of LOC-TSOP devices. The warpage behavior of LOC- TSOP is discussed based on experimental results. 2. Experimental 2.1. Package Description In our study, LOC-TSOP was evaluated for package warpage using different mold compounds. All test vehicles were 400 mil JEDEC 54 lead packages with a body size of 10.10 6 22.22 mm and a body thickness of 1.0 mm. The 54-lead device is currently the standard TSOP in 64/128/256M SDRAM production. The basic construction of the packages is shown in Fig. 1. The typical die attach and an alloy 42-leadframe with down- set depth, 50 mm, are 0.1 mm and 0.125 mm, respectively. In our experiment different sized dies with 0.28 mm die thickness were used. 24 LOC-TSOP samples (2 leadframes of 12 packages each) were assembled for each mold compound. After wire bonding, the units were transfer-molded at 175 C in a conventional mold chase with uneven top and bottom cavity thickness. The samples were then post-mold cured at 175 C for 5 h in a conventional oven. After the samples were cooled in air to room temperature, they were measured for warpage using an optical projector. The 24 0957–4522 # 2001 Kluwer Academic Publishers 93

Warpage behavior of LOC-TSOP Memory Package

Embed Size (px)

Citation preview

J O U R N A L O F M AT E R I A L S S C I E N C E : M AT E R I A L S I N E L E C T RO N I C S 1 2 ( 2 0 0 1 ) 9 3 ± 9 7

Warpage behavior of LOC-TSOP Memory Package

MINJIN KO, DONGSUK SHIN, MYUNGSUN MOON, INHEE LIM,YONGJOON PARKLG Chemical Ltd./Research Park, Advanced Materials Research Institute,Taejon, KoreaE-mail: [email protected]

This paper describes a warpage study on LOC-TSOP memory devices. The main objectives ofthis study are to evaluate the impacts of epoxy mold compounds on package warpage withdifferent sized dies. It was found that the balance of the bending between the edge sideregion and the die attach region controls the package warpage. The package tends to bendconvex upwards in the edge side region and concave downwards in the die attach region.The various mold compounds were prepared to study the affect on the components,particularly the resin and the ®ller. It has been shown that the optimum mold compound canbe changed according to the inner structure of the LOC-TSOP. The effect of post-mold cure onpackage warpage was also examined based on the cure rate.# 2001 Kluwer Academic Publishers

1. IntroductionDue to the ratio of a chip size to the package size and low

pin count of many DRAM designs, lead on chip (LOC) is

a packaging technique that has been used over the last 10

years for memory products [1, 2]. The technique consists

of attaching leadframe ®ngers directly on the chip

surface via a double-sided adhesive tape, thus the chip

density can be increased up to 90% compared to 65% in

conventional packages. Other advantages in the LOC

design include faster current speed associated with

shorter Au wires resulting from an array of pads scattered

on the center of the chips rather than periphery bonds.

Plastic packaging in the electronic industry has been

extensively used in the past. One of the reasons is its

lower cost compared to ceramic packaging. Epoxy resins

are most often used in plastic packages due to their low

melt viscosity that facilitates injection and minimizes

leadframe and gold wire deformation. It is known that the

internal stress in epoxy resins cured at high temperature

is produced by the volumetric shrinkage during the

cooling process from the cure temperature to room

temperature. The internal stress can reduce adhesion

strength and occasionally induces die cracking if a tensile

stress is built up in the die, particularly in thin packages.

Along with internal stress, excess bending of the package

can cause yield loss in many downstream assembly

processes, such as the trim and form since lead

coplanarity is necessary for device testing and for surface

mount assembly [3]. Residual warpage is often used by

package manufacturers as a check on the quality of the

molding process [4].

As the package increases and the chip decreases in

size, maintaining package planarity becomes more

dif®cult particularly in an asymmetric structure. Since

the degree of package warpage depends on the package

design, materials selection, and assembly process,

several methods can be used to reduce package warpage.

Among these approaches, optimization of the mold

compound is the least costly and most manufacturable

solution although the package design would be a more

effective way to minimize package warpage. It is

important to know how sensitive the warpage of a

particular package is to change in material properties. To

date, most studies have centered on the geometric

modi®cation of package design and ®nite element

analysis [5]. This paper discusses a study evaluating

the effect of mold compounds on the package warpage of

LOC-TSOP devices. The warpage behavior of LOC-

TSOP is discussed based on experimental results.

2. Experimental2.1. Package DescriptionIn our study, LOC-TSOP was evaluated for package

warpage using different mold compounds. All test

vehicles were 400 mil JEDEC 54 lead packages with a

body size of 10.106 22.22 mm and a body thickness of

1.0 mm. The 54-lead device is currently the standard

TSOP in 64/128/256M SDRAM production. The basic

construction of the packages is shown in Fig. 1. The

typical die attach and an alloy 42-leadframe with down-

set depth, 50 mm, are 0.1 mm and 0.125 mm, respectively.

In our experiment different sized dies with 0.28 mm die

thickness were used.

24 LOC-TSOP samples (2 leadframes of 12 packages

each) were assembled for each mold compound. After

wire bonding, the units were transfer-molded at 175 �C in

a conventional mold chase with uneven top and bottom

cavity thickness. The samples were then post-mold cured

at 175 �C for 5 h in a conventional oven. After the samples

were cooled in air to room temperature, they were

measured for warpage using an optical projector. The 24

0957±4522 # 2001 Kluwer Academic Publishers 93

packages of each test were inspected with scanning

acoustic microscopy to check for delamination and die

tilt. Any defective package was eliminated from the test.

2.2. Mold Compound CharacterizationTMA (therm-mechanical analysis): The glass transition

temperature �Tg�, and the coef®cient of thermal

expansion (CTE) below Tg �a1� and above Tg �a2� of

the epoxy molding compounds were measured with a

TMA/SS-100 Seiko therm-mechanical analyzer. The test

specimens (56 56 15 mm) were heated from 0 �C to

about 250 �C at a rate of 2 �C minÿ 1.

DSC measurement: The calorimetric measurement was

conducted using a TMA/SS-100 Seiko differential

scanning calorimeter with a microprocesser controller.

The temperature and power calibration of the DSC were

optimized for the temperature of 20±300 �C using high-

purity indium. For the isothermal cure, the DSC was ®rst

equilibrated at the present cure temperature and then the

sample was introduced into the DSC cell.

Mechanical test: Mechanical characterization of the mold

compounds was carried out using a Zwick universal

testing machine with a high-temperature chamber oper-

ated from room temperature to 350 �C. The ¯exural

modulus was measured by a three-point bending test with

span interval of 64 mm and bending speed of 1 mm minÿ 1

according to ASTM-D-790. The test specimens

(56 12.76 60 mm) were prepared by transfer-molding

at 175 �C for 120 s and cured in an oven at 175 �C.

3. Results and Discussion3.1. Warpage modeAs seen in Fig. 1, in the LOC-TSOP it is very dif®cult to

obtain a perfect balance between top and bottom sides of

the package due to the complex cavity geometry, inner

leadframe structure, size and location of the device. In

particular, the volume of the compound is intrinsically

uneven at the side edge region for the ¯at-type LOC

package. The chip occupation area will also be an

important factor. In order to investigate the warpage

mode, two kinds of TSOP, one with silicon dies and the

other with no silicon die, were tested after post-mold

cure. The typical warpage modes are shown in Fig. 2.

The package without a die is relatively uncomplicated

since it is comprised of only the metal leadframe and the

mold compound. The warpage of this package would be

easy to predict. As seen in Fig. 2a, the package without a

silicon die bends convex upwards, relative to the middle

of the package. This result is obvious in that the total

volume of the mold compound below the leadframe is

larger than that above the leadframe.

However, the warpage mode changes by the insertion

of the die, and the shape depends on the die size shown in

Fig. 2b and C; a gull shape mode for a small-sized die

and a concave mode for a large sized die. It is interesting

to see that insertion of die can make the package warpage

concave. The same trend was obtained even with no

down-set leadframe. This phenomenon is probably due to

the different interface layer at the top and bottom side of

the die. The leadframe and passivation layer contacted

with the mold compound at the top interface should be

more amenable to bend than the rigid silicon die at the

bottom side. Thus the package will tend to warp concave

downwards when the volume shrinkage between the top

and the bottom are the same. The change of warpage

mode from the gull shape to the concave appears for the

die size around 35±40%.

3.2. Mold compound evaluationWe ®rst evaluated two different grades of new-

generation, low-stress mold compounds developed for

thin plastic IC packages. The mold compounds,

identi®ed as ``EMC Grade A'' and ``EMC Grade B'',

were formulated based on a biphenyl epoxy and a high

performance conventional epoxy, which passed the

JEDEC Level I MRT (moisture resist test). Fig. 3

Figure 2 Typical warpage modes: mode A for no die, mode B for a

small-sized die, and mode C for a large-sized die.

Figure 3 TMA plot of dimension versus temperature for ``EMC Grade

A'' and ``EMC Grade B''.

Figure 1 Cross-section view of 54-lead LOC-TSOP package.

94

shows the TMA plots of ``EMC Grade A'' and ``EMC

Grade B'' from 0 �C to 250 �C at 10 �C minÿ 1, with

a1 � 0:91 ppm �Cÿ 1 and a2 � 4:1 ppm �Cÿ 1, and with

a1 � 1:15 ppm �Cÿ 1 and a2 � 5:4 ppm �Cÿ 1, respec-

tively. CTE, Tg and ¯exural modulus values are

summarized in Table I.

The average warpage value for each compound is

shown in Fig. 4. It is seen that the warpage of the samples

molded with ``EMC Grade A'' is about 30 mm for a

large-sized die and 78 mm for a small-sized die while the

warpage of the samples molded with ``EMC Grade B'' is

62 mm for a large-sized die and 64 mm for a small-sized

die. The ratio of the chip size to package size is about

60% for a large die and 30% for a small die, respectively.

By using the conventional compound, the package

warpage increased to 100% for a large-sized die, but

decreased to about 20% for a small-sized die. This is

quite interesting in that the ``EMC Grade A'' with higher

®ller content does not always give better warpage

perform-ance.

To understand these phenomena, we have tested

several model compounds. It is known that the package

warpage results primarily from internal stresses caused

by volumetric shrinkage of the resin during the curing

process and thermal expansion coef®cient mismatches

between the package components as the devices cool

from the curing temperature to room temperature. Since

volumetric shrinkage and CTE mainly depend on the

type of resin systems and the amount of ®ller in mold

compounds, we ®rst evaluated the warpage of the model

compounds designed to have different Tg. The Tg of the

compounds was changed by varying the base resin

system with ®xed ®ller content. Fig. 5 shows the TMA

plots of the three model compounds. Volumetric

shrinkage and modulus are varied only by the resin

matrix during thermal cooling, and the CTE of the

compounds is not changed signi®cantly. Warpage test

results showing the effect of the glass transition are

presented in Fig. 6. It is seen that the low-Tg resin system

helps to decrease warpage for a large-sized die, while the

high-Tg resin does this for a small-sized die. In general,

the magnitude of thermal stress, s, is dependent on both

the elastic modulus and the coef®cient of thermal

expansion;

s � k

Z T2

T1

E ? adT

Since the ratio of elastic modulus below Tg to above

Tg�E1=E2� should be much greater than the ratio of CTE

above Tg to below Tg�a2/a1�, thermal stress below Tg

would be greater than that above Tg. The stress level of

the model compounds estimated with the CTE and

¯exural modulus is shown in Fig. 7. Therefore, a low-Tg

resin system would decrease thermal stress during

volumetric shrinkage resulting in less warpage for a

T A B L E I Material properties of ``EMC Grade A'' and ``EMC

Grade B''

Material properties Units EMC A EMC B

Base resin matrix Biphenyl Conventional

Elastic modulus at 25 �C kg mmÿ2 2300 1950

Elastic modulus at 240 �C kg mmÿ2 100 140

Thermal expansion below Tg 10ÿ5 �C 0.91 1.15

Thermal expansion above Tg 10ÿ5 �C 4.1 5.4

Glass transition �C 110 147

Figure 4 Warpage of the TSOP package with different die size molded

with ``EMC Grade A'' and ``EMC Grade B''.

Figure 5 TMA plot of dimension versus temperature for three model

compounds with different Tg.

Figure 6 Effect of resin matrix on package warpage.

95

large-sized chip. In the case of the small-sized die,

however, the larger thermal stress above the die causing

the bending downwards at the center region might

suppress the opposite bending of the leadframe at the side

edge region, resulting in less warpage.

Among many components in mold compounds that

can have an in¯uence on reducing the thermal stress and

lowering chemical shrinkage, the high loading of ®llers

has been known as a most effective way [9, 10]. It is

reported that the CTE of mold compounds is a major

factor in package warpage [11]. Fig. 8 shows the

relationship between ®ller content and package warpage.

We tested model compounds designed to have different

®ller content with the same resin system. Biphenyl-type

epoxy and xylok-type hardener were used in this

experimental. Unlike the resin effect, the package

warpage increased as the ®ller content of the compounds

decreased for both a large- and small-sized die. It is

related to both the lowered CTE of the compound and the

reduced chemical or curing shrinkage due to the reduced

resin part. By adding the 4% silica ®ller the warpage was

reduced about 25% for a small-sized die and 30% for a

large-sized die.

3.3. Postmold cure effectNearly all IC mold compounds require a post-cure

treatment to ensure the package reliability. The mold

compound does not reach 100% chemical conversion in

the high production rate molding process. The reaction

rate becomes signi®cantly slower at the later stages of

conversion, making elimination of post-cure unlikely.

PMC for 5 h has been adopted in the industry to achieve

``complete'' conversion. To evaluate the PMC effect on

package warpage the three model compounds are

formulated to have similar gel time around 22 sec. It is

seen in Fig. 9 that the package warpage is reduced after

PMC by about 4 mm up to 30 mm, depending on the

compounds used. Since the extent of warpage variation

seems to be related to the degree of conversion before

and after PMC, we assess the cure rate of each compound

using an isothermal DSC measurement. Fig. 10 shows

that the cure rate of the mold compounds passes through

a maximum point and then decreases. The compound A

reaches the maximum rate earlier than other compounds.

Figure 7 Estimated stress level (CTE6E) for each compounds.

Figure 8 Effect of ®ller content on package warpage.

Figure 9 Effect of post-mold cure on package warpage.

Figure 10 Plots of cure rate and conversion versus time for the mold

compounds at 130 �C.

96

It also provides a plot of the conversion as a function of

time. The DSC data show that the compound A is cured

fastest compared to the compounds B and C. Thus the

conversion gap before and after PMC would be smaller

for the package molded with the compound A than that

with compounds B and C, resulting in a narrow variation

of material properties. The gel time has no close relation

with the warpage difference before and after PMC. Fig.

11 also shows that the ultimate warpage value can be

reached within 2 h post-cure, indicating that the lengthy

post-mold cure process often adopted in the industry may

not be necessary from the viewpoint of package warpage.

4. ConclusionThe experiments were carried out to study the impacts of

mold compounds on the package warpage of 54-lead

LOC-TSOP with different sized dies. The following

conclusions are drawn:

1. The package without a silicon die warps convex

upwards, but the warpage mode changes by the insertion

of the die, and the shape depends on die size; a gull shape

mode for a small-sized die and a concave mode for a

large-sized die. The change of warpage mode from the

gull shape to concave appears for die sizes around 35±

40%.

2. Since package warpage results primarily from

internal stress caused by volumetric shrinkage of the

resin during the curing process, the mold compound

effect has been studied. A low-Tg resin system helps to

decrease warpage for a large-sized die, while the high-Tg

resin does this for a small-sized die. However, the

package warpage increased as the ®ller content of the

compound decreased for both a large die and small die

due to the decrease in chemical shrinkage.

3. PMC is necessary after transfer-molding to reduce

package warpage. The extent of warpage improvement

relates not to gel time but to the cure rate of the mold

compound. However, the ultimate value of the warpage

can be reached within 2 h post-cure.

References1. D . H A G E N , J . M cD E R M OT T, J . B I G L E R and D . CAVA S I N in

Proceedings of IEEE CHMT International Electronics

Manufacturing Technology, Symposium, 1992, p. 39.

2. M L A M S O N , D . E D WA R D S , S , G RO OT H U I S and G . H E I N E N ,

in Proceedings of IEEE Electronic Components & Technology

Conference, 1993, p. 1045.

3. L . T. M A N Z I O N E , ``Plastic packaging of microelectronic

devices'' (Van Nostrand Reinhold, New York, 1990).

4. K I - RO K H U R , YO U N G - C H A N K I M , S H I N C H O I , C H I J O O N G

S O N G and YO U N G - G O N K I M , in Proceedings of SEMICON

Korea Technical Symposium, 1998, p. 193.

5. S U H I R , E . , in ``Predicted bow of plastic packages of integrated

circuit (IC) devices'', Vol. 12, 1993, p. 952.

6. B . K I A N G , J . W I T T M E R S H A U S , R . K A R and N . S U G A I , in

Proceedings of IEMT Symposium, 1991, p. 89.

7. G . K E L LY, C . LY D E N , W. L AW TO N and J . B A R R E T T in

Proceedings of IEEE Electronic Components & Technology

Conference, 1994, p. 102.

8. G . K E L LY, C . LY D E N , W. L AW TO N and J . B A R R E T T in

Proceedings of IEEE Electronic Components & Technology

Conference, 1995, p. 977.

9. S . E G U C H I , A . N A G A I , T. I S H I I , S . N U M A R A , M . O G ATA ,

K . N I S H I and G . M U R A K A M I , in Proceedings of SEMICON

Singapore Technical Symposium, 1994, p. 209.

10. H . F U J I TA and N . M O G I , in Proceedings of IEEE Electronic

Components & Technology Conference, 1993, p. 735.

11. L . Y I P and A H M A D H A M Z E H D O O S T, in Proceedings of IEEE

Electronic Components & Technology Conference, 1995, p. 229.

Received 20 November 2000and accepted 19 January 2001

Figure 11 Package warpage with various post-cure time.

97