Wafer Preparation

Mohammad Pourmand

Presented by:

Course Lecturer: Dr. Jafari Panah

Wafer Preparation

Actually, One of the most important stages in semiconductor technology is the preparation of wafers on which the microelectronic circuits and devices have to be implemented.

Input: Single Crystal Ingot

Output: Wafers with mirror-like surfaces

1- Cropping

The first step is to cut both tapered ends of the crystal with a saw.

Either of these ends can be used as seed in another crystal growth stage.

2- Diameter Grinding

There would be variations in diameter over the length of the crystal.

Poor diameter control may cause in warped or broken wafers.

Grinders:

grinderLathe

GrindingDiameterforUsedgrinderCenterless :

Diameter Grinder Machine

3- Basic Tests

The Crystal Orientation is determined by X-ray diffraction. An end of the crystal is etched or polished to remove saw

damage. Mounting the crystal in X-ray apparatus. Determining the crystal orientation using the resultant

pattern.

This pattern is representative of <100> orientation.

XRD (X-ray Diffraction)

The first kind of scatter process to be recognized was discovered by Max von Laue who was awarded the Nobel prize for physics in 1914 for his discovery of “the diffraction of X-rays by crystals”. Max von Laue (1897-1960)

When a periodic array of objects each scatter radiation coherently, the concerted constructive interference at specific angles is called diffraction. Input: Parallel monochromatic X-ray beam. Output: A series of diffracted beams whose directions and

intensities would be dependant upon the lattice structure of the crystal.

Photograph of the Laue pattern from a crystal. The symmetry of the crystal is indicated by the symmetry of spots.

XRD Equipment

Hot Point Probe

A simple and reliable means to determine whether a wafer is N or P type.

2 probes make ohmic contact with the wafer surface. One is heated 25-100°C hotter than the other.

A voltmeter placed across the probes will measure a potential difference whose polarity indicates whether the material is N or P type.

Four Point Probe

Resistivity measurements are made on the flat ends of the crystal by the four-point probe technique.

A current, I, is passed through the outer probes and the voltage, V, is measured between the inner probes.

R

Voltmeter

Constant current source

V

I

4- Flat Grinding

After grinding to fix the diameter, one or more flats are grounded along the length of the ingot.

The largest flat, called the "major" or "primary" flat, is usually relative to a specific crystal orientation. Serves as a mechanical locator in automated processing

equipment to position the wafer.

Other smaller flats are called "secondary" flats that serve to identify the orientation and conductivity type of the wafer.

The drawback of these flats is the reduction of the usable area on the wafer.

For some 200 mm and 300 mm diameter wafers, only a small notch is cut from the wafer to enable lithographic alignment but no dopant type or crystal orientation information is conveyed.

Notch

5- Wafer Slicing

Slicing is accomplished by Diamond coated, inside diameter saws (ID saw).

ID saws are thin but rigid circular sheets of steel. Internal cutting edge is coated with diamond.

This structure reduces kerf (cutting width) size which in turn prevents sizeable amounts of the crystal being wasted by the slicing process.

Wet lubricant is used

Internal diameter

wafer saw

Diamond Wires Instantaneous slicing of wafers + reduced kerf.

A clip of diamond wire slicing

6- Flatting and Polishing

The Surface of the wafer has to be absolutely flat because the dimensions of the surface layers making up the device is very small.

Flatting and polishing process requires two steps: - Rough Polishing - CMP (Chemical Mechanical Polishing)

Rough Grinding

A conventional mechanical abrasive slurry lapping process using SiCandOAl 32

CMP (Chemical - Mechanical Polishing)

Include Chemical etching + Mechanical Buffing

Wafers are mounted on rotating holders and lowered on to a pad surface rotating in the opposite direction.

Material: Cast and sliced polyurethane or urethane coated felt.

Slurry: Silica suspended in a mild etchant like potassium or ammonium hydroxide.

The achieved flatness is a function of polishing time, the pressure on wafer and pad, the speed of rotation, the slurry particle size, the slurry feed rate, the chemistry (pH) of the slurry and the pad material.

Backside Processing

The backside of the wafers are usually left rough or etched to a bright appearance.

For some device use the backs may receive a special process to induce crystal damage called backside damage.

Backside damage causes the growth of dislocations that radiate up into the wafer.

These dislocations can act as a trap for mobile ionic contamination introduced to the wafer during the fabrication process.

The trapping phenomenon is called gettering.

Sandblasting of the back side and deposition of a polysilicon or silicon nitride layer on the back, are another standard techniques.

Double-Sided Polishing Most manufacturers of 300-mm diameter wafers employ

double-sided polishing to achieve flatness specifications of 0.25 to 0.18 μm over 25×25 mm sites.

A downside is that all further processing must employ handling techniques that do not scratch or contaminate the backside.

Upper polishing pad

Lower polishing pad

Wafer

Slurry

7- Edge Grinding and polishing

Rounding wafer edge, minimizes wafer damage during fabrication.

Wafer damage in a sharp corner may act as a dislocation nucleus or would be a good way for particles to be introduced into the wafer.

In lithography process the PR sticks to the damaged edges of the wafer, and removing PR becomes a major concern.

8- Wafer Evaluation

Before packing, the wafers are checked for a number of parameters like physical dimensions, flatness, crystal defects and resistivity as specified by the customer.

Primary concerns are surface problems such as particles, stain and haze. These problems are detected with the use of high-intensity

lights or automated inspection machines.

Flatness Checking

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Brightfield imaging

Two-way mirror

Light source

Lens

Viewing optics

Viewing optics

Darkfield imaging

Light sourceLens

Light reflected by surface irregularities

9- Final Cleaning

Immersion Type

Immersion of wafer in SC1, then in SC2 at elevated temperatures then in dilute HF in room temperature.

SC1: NH4OH, H2O2, H2O mixture

SC2:HCL, H2O2, H2O mixture

Single wafer Spin Cleaning Includes alternate applying of ozonated water and dilute HF

in several cycles.

Features:

Continuous supply of fresh chemicals.

Reducing the volume of equipment.

Ozonated water treatment: formation of chemical oxide film.

HF: Etches the chemically grown oxide film.

Result: Removal of organic , metallic and other particles.

10- Oxidization

Si wafers maybe oxidized before shipment to the customer.

Features: Si oxide layer serves to protect the wafer surface from

scratches and contamination during shipping.

Buying the wafers with an oxide layer saves a fabrication process step.

11- Packaging

Takes Place in clean room.

Packaging material: non-static, non particle generating.

The operators and the equipments should be discharged, preventing particle attractions to the wafers.

Wafer Diameters

300 mm

200 mm

150 mm

125 mm

100 mm

75 mm

3² 4² 5² 6² 8² 12²

Increase in Number of Chips on Larger Wafer Diameters(Assume large 1.5 x 1.5 cm microprocessors)

88 die200-mm wafer

232 die300-mm wafer

Wafer Standardization Parameters

Light Point Defects (LPDs): Unwanted particles on surface of wafer. Particles measured by total number found across a certain area of wafer.

Total Thickness Variation (TTV): Absolute difference in thickness between the thickest and thinnest parts of wafer. A typical value on a 8" wafer would be less than 15 μm.

Warp: The difference between minimum and maximum values of the wafer surface measured from a reference plane (usually the backside of the wafer). Deviations include both concave and convex variations. A good warp number on an 8" wafer is less than 20 μm.

Bow: Concavity or deformation of the wafer measured from the center independent of any thickness variation. Good bow on a 8" prime wafer is less than 30 μm.

SEMI

SEMI (Semiconductor Equipment and Materials International) is a trade organization of manufacturers of equipment and materials.

Important rolls:

Generation of standards specific to the industry

Generation of long-range plans for the industry

Thickness: 525 μm

Primary flat length: 32.5 mm

Secondary flat length:

18.0 mm

Bow, max: 40 μm

Warp, max: 40 μm

TTV (flatness), max:

10 μm

Primary flat orientation

>110<

SEMI Standard for 4” wafer SEMI Standard for 6” wafer

Thickness: 675 μm

Primary flat length: 57.5 mm

Secondary flat length: 37.5 mm

Bow, max: 60 μm

Warp, max: 60 μm

TTV (flatness), max: 10 μm

Primary flat orientation: >110<

Parameter Units Nominal Some Typical

Tolerances

Diameter mm 300.00 0.20 Thickness

(center point) m 775 25

Warp m < 40

TTV m 2

Notch Depth mm 1.00 + 0.25, -0.00

Notch Angle Degree 90 +5, -1

Back Surface Finish Bright Etched/

Polished

Typical Specifications for 300 mm Silicon Wafers

Silicon Market

In terms of silicon wafer consumption - the top 10 customers consume nearly 54% of the silicon wafer area.

In terms of silicon wafer supply - the top 3 companies supply over 78% of the silicon wafer area.

In terms of wafer diameter - the 2 largest diameters comprise over 81% of the wafer area produced and almost 90% of the revenue.

Key Findings Construction of new 12” (300 mm) fabs is on the rise.

There are 57 fabs now operating and 15 new ones under construction.

Twelve inch (300 mm) wafer demand increased from 1709 million square inches in 2005 to 2829 million square inches in 2006.

Eight inch (200 mm) wafer demand increased from 3.3 billion square inches in 2005 to 3.6 billion square inches in 2006.

Semiconductor revenue was up from $225.9 billion in 2005 to $243.3 billion in the year 2006, a 7.7% increase. This is a record for semiconductor revenues.

Intel once again ranked as the world's leader in semiconductor revenue. The Korean company, Samsung Semiconductors is in second position and an American company, Texas Instruments was in third position.

Wafer consumption was 7988 million square inches in the year 2006, up 20.2% over 2005. This consumption was also an historical peak.

Polysilicon consumption increased 20.1%, from 19,949 metric tons in 2005 to 23,964 metric tons in the year 2006, an increase of over 4015 metric tons.

Market Shares Top 6 polysilicon producers' semiconductor market shares

are:- Hemlock 28.6% - Mitsubishi 11.9%- Tokuyama 18.2% - REC Silicon 10.1%- Wacker 17.5% - MEMC 9.4%

On an area basis the top 6 silicon wafer producers' market shares are:- SEH 31.9% - MEMC 11.8%- SUMCO 31.7% - LG Siltron 3.6%- Siltronic 14.9% - Others 6.1%

Semiconductor Industry Forecast

The semiconductor industry has grown from $21.3 billion in 1979 to $243.3 billion in the year 2006. This more than ten-fold (10x) increase represents an average annual growth rate of 9.1%.

The new forecast calls for the following sales levels:

- 2006 $243 billion- 2007 $247 billion- 2008 $290 billion- 2009 $315 billion- 2010 $324 billion

Global semiconductor sales forecast in billions of dollars

Silicon Wafer Forecast The silicon wafer industry has grown from 1620 million

square inches in 1984 to 7988 million square inches in the year 2006. This factor of 4.9x growth represents a compound annual growth rate of 7.2%.

This 2007 forecast calls for the following growth:- 2006 7988 MSI- 2007 8250 MSI- 2008 8590 MSI- 2009 9000 MSI- 2010 9450 MSI

The 2007 forecast calls for a 3.3% increase, followed by 4.1% increase in 2008.This is followed by a 4.8% increase in 2009. For the year 2010 the forecast calls for a growth of 5.0%.

Global silicon wafer sales forecast in millions of square inches

Semiconductor Companies

based solely on their manufacture of semiconductors on silicon wafers

Silicon Wafer Companies

Total 2006 wafer area = 7988 million square inches

Silicon Wafer Prices

300 mm Silicon Wafer Forecast

The new 12” (300 mm) fabs are starting to make themselves known in the industry.

In the year 2004, 200 mm diameter wafer consumption decreased from 57.1% of the total demand to 52.7% and in 2006 it further decreased to 45.7%.

While 200 mm wafers remain the predominant wafer used by the semiconductor industry; the move to 300 mm wafers has matured and in 2006 this diameter accounted for 35.7% of the total wafer area.

The cost of fabbing wafers is 30% cheaper in a 300 mm fab than in an 200 mm fab. However one has to fab a lot of wafers to pay back the $3 billion investment needed construct a 300 mm fab.

Today’s leaders include:- Samsung - TSMC- Toshiba - Qimonda (ex-Infineon memory)- Intel - Micron Technology- Elpida - PowerChip- Hynix Semiconductor- ProMos

Total silicon wafer area grew from 6.6 billion square inches in the year 2005 and is expected to grow to 8.6 billion square inches by the year 2010.

In the year 2003 the 300 mm share was 9.3% of the total. In 2006 the share increased to 35.4%, in 2009 it is expected to overtake 200 mm and in 2010 it is anticipated to grow to 43.9%.

In terms of wafers per month the forecast is as follows:

• 2005 1709 MSI 1,302,000 wafers per month• 2006 2829 MSI 2,156,000 wafers per month• 2007 3065 MSI 2,336,000 wafers per month• 2008 3371 MSI 2,569,000 wafers per month• 2009 3740 MSI 2,850,000 wafers per month• 2010 4125 MSI 3,144,000 wafers per month