Wafer Bonding Processes for the Manufacture of MEMS devices for

the Mobile Applications

Outline

• EV Group at a Glance• Market Drivers – MEMS• Bonding Family Tree• Requirements for Wafer Bonding Processes for

Mobile Applications• Example: Invensense MEMS device• Eutectic and TLP bonding• Low Temperature Oxide Bonding

EV Group (EVG) is a global supplier of • Wafer Bonders• Aligners• Coaters / Developers• Temporary Bonders / Debonders (Laminator)• Cleaners• Inspection Systems

EV Group (EVG) is a global supplier to• Advanced Packaging, 3D Interconnect• MEMS (MicroElectroMechanical Systems)• SOI (Silicon-On-Insulator)• Compound Semiconductor and Silicon based Power Devices• Nanotechnology

EV Group holds the dominant share of the market for wafer bonding equipment (especially SOI bonding) and is a leader in lithography for advanced packaging and nanotechnology.

EV Group at a Glance

Market Drivers - MEMS

Market Drivers - MEMS

Major growth for MEMS devices related to Mobile Applications

Market Drivers - MEMS

Price Erosion in Consumer MEMS

Drivers - Summary

• Consumer Applications are a major driver for growth in shipment volumes of MEMS devices

• Growth rate in units shipped (24%) is higher than growth rate in revenue increase (14%) Price Erosion

• “Combo Sensors“ are expected to gain significant traction starting by 2012. Higher integration density desired Capability for forming electrical connections may be required

Responses to Price Erosion

– Design libraries– Die shrinks

• More die per wafer• Smaller package and increased function per unit

area– Standard process

• Is this the beginning of the end of the “One Product, One Process” paradigm?

– Wafer size increase– Yield management– Equipment utilization

Topic for today‘s presentation

Bonding Family Tree

Requirements for Wafer Bonding Processes for Mobile Applications• Low cost

– Low space consumption• Small bond line width• Good alignment accuracy

– High throughput– Integration in existing fab environment

• Materials selection

• Technical requirements– Good hermeticity– Ability to create electrical connections– Low temperature processing

• Thermal budget to be compatible with CMOS wafers

Replace Glass Fritt

Eutectic

Use materials already established

Metal / Hybrid

Metal

Eutectic / Plasma

Bonding Family Tree

Invensense MEMS Device

Chipworks recently had a look inside their new three-axis digital gyroscope, the ITG-3200. The device is built using the Nasiri, single-chip, MEMS process, where the MEMS layer is sandwiched between a fusion-bonded cap wafer and the ASIC. The ASIC and MEMS are bonded using eutectic metal bond. The SEM image in Figure 1 provides a tilt-view of the corner of the MEMS chip, where the MEMS layer can be seen between the cap and ASIC die.Source: http://memsblog.wordpress.com/2010/08/11/a-peak-inside-the-invensense-itg-3200-three-axis-gyroscope/

Invensense MEMS Device

Fusion Bond

Eutectic Bond

Eutectics applied in Wafer Bonding

• Popular Eutectic Bonding Schemes (incl. Bond Temperature)(sorted by downward bonding temperature) – Al-Si (~600°C)– Al-Ge (~450°C)– AlCu-Ge (~400°C)– Au-Si (~400°C)– Au-Sn (~300°C)– Au-In (~275°C)– Cu-Sn (~270°C)– Pb-Sn (~190°)– In-Sn (~120°C)

EVG experience

Courtesy of Invensense

Al-Ge Eutectic Wafer Bonding

Al-Ge Bonding - Main Process Features

Both Al and Ge surfaces are covered with very stable, hard-to-strip native oxides when exposed to ambient.

Due to its high temperature, process time has to be short when using CMOS wafers.

The oxide layers must be mechanically broken. For this, the process is using high force.

Al – Ge Bonding

Al-Ge Eutectic• Eutectic Temperature 420°C• Bonding Temperature ~ 450°C

• Bonding Force: Pattern dependant. 30 to 60kN for 200mm wafers.

• Optimized thermal profile required for repeatable good bonding results.

Cu-Sn TLP Bonding - Background

- Parent Metal is deposited on both wafers.

- Deposition method may be sputtering, evaporation or electroplating

- Low melting point interlayer may be deposited on one or both of the wafers.

- Layer thicknesses have to be optimized to ensure process performance

Cu-Sn TLP Bonding - Background

- Wafers are loaded into bond chamber

- Optionally oxide removal process may be performed

- Oxide issue may also be countered by mechanically breaking native oxide of metal layers due to applied force.

Cu-Sn TLP Bonding - Background

- Wafers are heated according to recipe parameters

- Low melting point interlayer starts already to diffuse into parent metal.

- Heating ramp rate has to be reasonably fast to avoid consumption of the entire low melting point interlayer prior to reaching liquid phase

Cu-Sn TLP Bonding - Background

- Heating of wafers above melting point

- Low melting point interlayer will melt and at this stage gaps in the interface may be closed.

- In this phase, also some wafer topography may be compensated

Cu-Sn TLP Bonding - Background

- Liquid low melting point interlayer will react with parent metal and form intermetallic compounds

- Reaction into IMCs results in solidification of the bond interface

Cu-Sn TLP Bonding - Background

- During further time at temperature, the bond metal interconnect homogenizes into a uniform distribution of IMCs and parent metal.

- For some process and / or material sets, the metal stack may homogenize to a condition where the majority of the metal stack is comprised of parent metal with some IMCs dissolved in the parent metal.

Cu-Sn TLP – Results

Metal Based Wafer Bonding Processes TLP (Transient Liquid Phase) BondingSome work done at EV Group regarding Cu-Sn TLP Bonding

A B C D E

1

2

3

Advantages of TLP Bonding • More relaxed surface quality requirements than

metal diffusion bonding schemes• Capability to tolerate some surface topography • Low bonding temperature (taking advantage of the low

melting point of the “low melting point interlayer”) • High service temperature of the bond interface once the

bonding process is completed (non-reversible bond) • Low bonding force (i.e. when compared with metal

diffusion bonding) required due to the liquid phase present during the bond.

• Less flow of material in the bond interface as compared with regular eutectic bonding

Low Temperature Oxide Bonding with Plasma Activation• Plasma Activation enables the formation of

strong oxide-oxide bonds at low temperature• Oxide bonds are front end compatible

– Highly clean, no contamination risk– High temperature stable – No risk of metals diffusion – Known etching processes– Simple process integration – Oxide is well known and understood as sacrificial

material

General Process Flow

Plasma activation; Device and carrier (EVG810LT plasma activation equipment):

Megasonic cleaning (EVG3xx series single wafer cleaner):

Wafers were cleaned for particles removal using a megasonic nozzle and deionized water.

Fusion bonding

Bond front initiated e.g. at the wafer center.

Annealing (furnace): x h at yyy °C.

Carrier

Device

Bond Strength Development for Plasma Activated Bonding

EV Group Confidential and Proprietary

Microroughness Analysis: RMS

TABLE I. Surface Microroughness Comparison

Surface Orientation and Plasma Type

RMS Before Plasma RMS After Plasma

(100) – N2 0.2254 ± 0.0017nm 0.1922 ± 0.0063nm

(110) – N2 0.0979 ± 0.0073nm 0.0886 ± 0.0015nm

(111) – N2 0.0862 ± 0.0069nm 0.1009 ± 0.0078nm

(100) – O2 0.2502 ± 0.0089nm 0.2200 ± 0.0048nm

(110) – O2 0.0956 ± 0.0039nm 0.0956 ± 0.0057nm

(111) – O2 0.0712 ± 0.0023nm 0.0949 ± 0.0038nm

Silicon wafer withoutplasma treatment

Silicon wafer afterN2 plasma treatment

TEM Analysis – Fusion Bond Interface

No boundary line could be found at the interface between the two types of oxides.

TEM Analysis – Fusion Bond Interface

Summary & Conclusions • Metal based bonding schemes and direct bonding

(oxide-oxide bonding) are gaining traction as the method of choice for high volume manufacturing of MEMS devices for mobile applications.

• Eutectic bonding enables the formation of hermetic bonding interfaces with low line widths, good alignment precision at CMOS compatible bonding temperatures

• Plasma activated fusion bonding enables the formation of permanent bonding interfaces with good hermeticity at low temperatures.

EVG Value Proposition • Industry standard for wafer bonding equipment for

high volume manufacturing of MEMS devices with a dominant market share.

• Strong process expertise for all types of wafer bonding processes, including eutectic bonding and plasma activated fusion bonding.

Thank you for your attention!

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